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Merge tag 'v3.10.55' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / compressed / head.S
1 /*
2 * linux/arch/arm/boot/compressed/head.S
3 *
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
13
14 .arch armv7-a
15 /*
16 * Debugging stuff
17 *
18 * Note that these macros must not contain any code which is not
19 * 100% relocatable. Any attempt to do so will result in a crash.
20 * Please select one of the following when turning on debugging.
21 */
22 #ifdef DEBUG
23
24 #if defined(CONFIG_DEBUG_ICEDCC)
25
26 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
27 .macro loadsp, rb, tmp
28 .endm
29 .macro writeb, ch, rb
30 mcr p14, 0, \ch, c0, c5, 0
31 .endm
32 #elif defined(CONFIG_CPU_XSCALE)
33 .macro loadsp, rb, tmp
34 .endm
35 .macro writeb, ch, rb
36 mcr p14, 0, \ch, c8, c0, 0
37 .endm
38 #else
39 .macro loadsp, rb, tmp
40 .endm
41 .macro writeb, ch, rb
42 mcr p14, 0, \ch, c1, c0, 0
43 .endm
44 #endif
45
46 #else
47
48 #include CONFIG_DEBUG_LL_INCLUDE
49
50 .macro writeb, ch, rb
51 senduart \ch, \rb
52 .endm
53
54 #if defined(CONFIG_ARCH_SA1100)
55 .macro loadsp, rb, tmp
56 mov \rb, #0x80000000 @ physical base address
57 #ifdef CONFIG_DEBUG_LL_SER3
58 add \rb, \rb, #0x00050000 @ Ser3
59 #else
60 add \rb, \rb, #0x00010000 @ Ser1
61 #endif
62 .endm
63 #elif defined(CONFIG_ARCH_S3C24XX)
64 .macro loadsp, rb, tmp
65 mov \rb, #0x50000000
66 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
67 .endm
68 #else
69 .macro loadsp, rb, tmp
70 addruart \rb, \tmp
71 .endm
72 #endif
73 #endif
74 #endif
75
76 .macro kputc,val
77 mov r0, \val
78 bl putc
79 .endm
80
81 .macro kphex,val,len
82 mov r0, \val
83 mov r1, #\len
84 bl phex
85 .endm
86
87 .macro debug_reloc_start
88 #ifdef DEBUG
89 kputc #'\n'
90 kphex r6, 8 /* processor id */
91 kputc #':'
92 kphex r7, 8 /* architecture id */
93 #ifdef CONFIG_CPU_CP15
94 kputc #':'
95 mrc p15, 0, r0, c1, c0
96 kphex r0, 8 /* control reg */
97 #endif
98 kputc #'\n'
99 kphex r5, 8 /* decompressed kernel start */
100 kputc #'-'
101 kphex r9, 8 /* decompressed kernel end */
102 kputc #'>'
103 kphex r4, 8 /* kernel execution address */
104 kputc #'\n'
105 #endif
106 .endm
107
108 .macro debug_reloc_end
109 #ifdef DEBUG
110 kphex r5, 8 /* end of kernel */
111 kputc #'\n'
112 mov r0, r4
113 bl memdump /* dump 256 bytes at start of kernel */
114 #endif
115 .endm
116
117 .section ".start", #alloc, #execinstr
118 /*
119 * sort out different calling conventions
120 */
121 .align
122 .arm @ Always enter in ARM state
123 start:
124 .type start,#function
125 .rept 7
126 mov r0, r0
127 .endr
128 ARM( mov r0, r0 )
129 ARM( b 1f )
130 THUMB( adr r12, BSYM(1f) )
131 THUMB( bx r12 )
132
133 .word 0x016f2818 @ Magic numbers to help the loader
134 .word start @ absolute load/run zImage address
135 .word _edata @ zImage end address
136 THUMB( .thumb )
137 1:
138 mrs r9, cpsr
139 #ifdef CONFIG_ARM_VIRT_EXT
140 bl __hyp_stub_install @ get into SVC mode, reversibly
141 #endif
142 mov r7, r1 @ save architecture ID
143 mov r8, r2 @ save atags pointer
144
145 #ifndef __ARM_ARCH_2__
146 /*
147 * Booting from Angel - need to enter SVC mode and disable
148 * FIQs/IRQs (numeric definitions from angel arm.h source).
149 * We only do this if we were in user mode on entry.
150 */
151 mrs r2, cpsr @ get current mode
152 tst r2, #3 @ not user?
153 bne not_angel
154 mov r0, #0x17 @ angel_SWIreason_EnterSVC
155 ARM( swi 0x123456 ) @ angel_SWI_ARM
156 THUMB( svc 0xab ) @ angel_SWI_THUMB
157 not_angel:
158 safe_svcmode_maskall r0
159 msr spsr_cxsf, r9 @ Save the CPU boot mode in
160 @ SPSR
161 #else
162 teqp pc, #0x0c000003 @ turn off interrupts
163 #endif
164
165 /*
166 * Note that some cache flushing and other stuff may
167 * be needed here - is there an Angel SWI call for this?
168 */
169
170 /*
171 * some architecture specific code can be inserted
172 * by the linker here, but it should preserve r7, r8, and r9.
173 */
174
175 .text
176
177 #ifdef CONFIG_AUTO_ZRELADDR
178 @ determine final kernel image address
179 mov r4, pc
180 and r4, r4, #0xf8000000
181 add r4, r4, #TEXT_OFFSET
182 #else
183 ldr r4, =zreladdr
184 #endif
185
186 bl cache_on
187
188 restart: adr r0, LC0
189 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
190 ldr sp, [r0, #28]
191
192 /*
193 * We might be running at a different address. We need
194 * to fix up various pointers.
195 */
196 sub r0, r0, r1 @ calculate the delta offset
197 add r6, r6, r0 @ _edata
198 add r10, r10, r0 @ inflated kernel size location
199
200 /*
201 * The kernel build system appends the size of the
202 * decompressed kernel at the end of the compressed data
203 * in little-endian form.
204 */
205 ldrb r9, [r10, #0]
206 ldrb lr, [r10, #1]
207 orr r9, r9, lr, lsl #8
208 ldrb lr, [r10, #2]
209 ldrb r10, [r10, #3]
210 orr r9, r9, lr, lsl #16
211 orr r9, r9, r10, lsl #24
212
213 #ifndef CONFIG_ZBOOT_ROM
214 /* malloc space is above the relocated stack (64k max) */
215 add sp, sp, r0
216 add r10, sp, #0x10000
217 #else
218 /*
219 * With ZBOOT_ROM the bss/stack is non relocatable,
220 * but someone could still run this code from RAM,
221 * in which case our reference is _edata.
222 */
223 mov r10, r6
224 #endif
225
226 mov r5, #0 @ init dtb size to 0
227 #ifdef CONFIG_ARM_APPENDED_DTB
228 /*
229 * r0 = delta
230 * r2 = BSS start
231 * r3 = BSS end
232 * r4 = final kernel address
233 * r5 = appended dtb size (still unknown)
234 * r6 = _edata
235 * r7 = architecture ID
236 * r8 = atags/device tree pointer
237 * r9 = size of decompressed image
238 * r10 = end of this image, including bss/stack/malloc space if non XIP
239 * r11 = GOT start
240 * r12 = GOT end
241 * sp = stack pointer
242 *
243 * if there are device trees (dtb) appended to zImage, advance r10 so that the
244 * dtb data will get relocated along with the kernel if necessary.
245 */
246
247 ldr lr, [r6, #0]
248 #ifndef __ARMEB__
249 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
250 #else
251 ldr r1, =0xd00dfeed
252 #endif
253 cmp lr, r1
254 bne dtb_check_done @ not found
255
256 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
257 /*
258 * OK... Let's do some funky business here.
259 * If we do have a DTB appended to zImage, and we do have
260 * an ATAG list around, we want the later to be translated
261 * and folded into the former here. To be on the safe side,
262 * let's temporarily move the stack away into the malloc
263 * area. No GOT fixup has occurred yet, but none of the
264 * code we're about to call uses any global variable.
265 */
266 add sp, sp, #0x10000
267 stmfd sp!, {r0-r3, ip, lr}
268 mov r0, r8
269 mov r1, r6
270 sub r2, sp, r6
271 bl atags_to_fdt
272
273 /*
274 * If returned value is 1, there is no ATAG at the location
275 * pointed by r8. Try the typical 0x100 offset from start
276 * of RAM and hope for the best.
277 */
278 cmp r0, #1
279 sub r0, r4, #TEXT_OFFSET
280 add r0, r0, #0x100
281 mov r1, r6
282 sub r2, sp, r6
283 bleq atags_to_fdt
284
285 ldmfd sp!, {r0-r3, ip, lr}
286 sub sp, sp, #0x10000
287 #endif
288
289 mov r8, r6 @ use the appended device tree
290
291 /*
292 * Make sure that the DTB doesn't end up in the final
293 * kernel's .bss area. To do so, we adjust the decompressed
294 * kernel size to compensate if that .bss size is larger
295 * than the relocated code.
296 */
297 ldr r5, =_kernel_bss_size
298 adr r1, wont_overwrite
299 sub r1, r6, r1
300 subs r1, r5, r1
301 addhi r9, r9, r1
302
303 /* Get the dtb's size */
304 ldr r5, [r6, #4]
305 #ifndef __ARMEB__
306 /* convert r5 (dtb size) to little endian */
307 eor r1, r5, r5, ror #16
308 bic r1, r1, #0x00ff0000
309 mov r5, r5, ror #8
310 eor r5, r5, r1, lsr #8
311 #endif
312
313 /* preserve 64-bit alignment */
314 add r5, r5, #7
315 bic r5, r5, #7
316
317 /* relocate some pointers past the appended dtb */
318 add r6, r6, r5
319 add r10, r10, r5
320 add sp, sp, r5
321 dtb_check_done:
322 #endif
323
324 /*
325 * Check to see if we will overwrite ourselves.
326 * r4 = final kernel address
327 * r9 = size of decompressed image
328 * r10 = end of this image, including bss/stack/malloc space if non XIP
329 * We basically want:
330 * r4 - 16k page directory >= r10 -> OK
331 * r4 + image length <= address of wont_overwrite -> OK
332 */
333 add r10, r10, #16384
334 cmp r4, r10
335 bhs wont_overwrite
336 add r10, r4, r9
337 adr r9, wont_overwrite
338 cmp r10, r9
339 bls wont_overwrite
340
341 /*
342 * Relocate ourselves past the end of the decompressed kernel.
343 * r6 = _edata
344 * r10 = end of the decompressed kernel
345 * Because we always copy ahead, we need to do it from the end and go
346 * backward in case the source and destination overlap.
347 */
348 /*
349 * Bump to the next 256-byte boundary with the size of
350 * the relocation code added. This avoids overwriting
351 * ourself when the offset is small.
352 */
353 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
354 bic r10, r10, #255
355
356 /* Get start of code we want to copy and align it down. */
357 adr r5, restart
358 bic r5, r5, #31
359
360 /* Relocate the hyp vector base if necessary */
361 #ifdef CONFIG_ARM_VIRT_EXT
362 mrs r0, spsr
363 and r0, r0, #MODE_MASK
364 cmp r0, #HYP_MODE
365 bne 1f
366
367 bl __hyp_get_vectors
368 sub r0, r0, r5
369 add r0, r0, r10
370 bl __hyp_set_vectors
371 1:
372 #endif
373
374 sub r9, r6, r5 @ size to copy
375 add r9, r9, #31 @ rounded up to a multiple
376 bic r9, r9, #31 @ ... of 32 bytes
377 add r6, r9, r5
378 add r9, r9, r10
379
380 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
381 cmp r6, r5
382 stmdb r9!, {r0 - r3, r10 - r12, lr}
383 bhi 1b
384
385 /* Preserve offset to relocated code. */
386 sub r6, r9, r6
387
388 #ifndef CONFIG_ZBOOT_ROM
389 /* cache_clean_flush may use the stack, so relocate it */
390 add sp, sp, r6
391 #endif
392
393 bl cache_clean_flush
394
395 adr r0, BSYM(restart)
396 add r0, r0, r6
397 mov pc, r0
398
399 wont_overwrite:
400 /*
401 * If delta is zero, we are running at the address we were linked at.
402 * r0 = delta
403 * r2 = BSS start
404 * r3 = BSS end
405 * r4 = kernel execution address
406 * r5 = appended dtb size (0 if not present)
407 * r7 = architecture ID
408 * r8 = atags pointer
409 * r11 = GOT start
410 * r12 = GOT end
411 * sp = stack pointer
412 */
413 orrs r1, r0, r5
414 beq not_relocated
415
416 add r11, r11, r0
417 add r12, r12, r0
418
419 #ifndef CONFIG_ZBOOT_ROM
420 /*
421 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
422 * we need to fix up pointers into the BSS region.
423 * Note that the stack pointer has already been fixed up.
424 */
425 add r2, r2, r0
426 add r3, r3, r0
427
428 /*
429 * Relocate all entries in the GOT table.
430 * Bump bss entries to _edata + dtb size
431 */
432 1: ldr r1, [r11, #0] @ relocate entries in the GOT
433 add r1, r1, r0 @ This fixes up C references
434 cmp r1, r2 @ if entry >= bss_start &&
435 cmphs r3, r1 @ bss_end > entry
436 addhi r1, r1, r5 @ entry += dtb size
437 str r1, [r11], #4 @ next entry
438 cmp r11, r12
439 blo 1b
440
441 /* bump our bss pointers too */
442 add r2, r2, r5
443 add r3, r3, r5
444
445 #else
446
447 /*
448 * Relocate entries in the GOT table. We only relocate
449 * the entries that are outside the (relocated) BSS region.
450 */
451 1: ldr r1, [r11, #0] @ relocate entries in the GOT
452 cmp r1, r2 @ entry < bss_start ||
453 cmphs r3, r1 @ _end < entry
454 addlo r1, r1, r0 @ table. This fixes up the
455 str r1, [r11], #4 @ C references.
456 cmp r11, r12
457 blo 1b
458 #endif
459
460 not_relocated: mov r0, #0
461 1: str r0, [r2], #4 @ clear bss
462 str r0, [r2], #4
463 str r0, [r2], #4
464 str r0, [r2], #4
465 cmp r2, r3
466 blo 1b
467
468 /*
469 * The C runtime environment should now be setup sufficiently.
470 * Set up some pointers, and start decompressing.
471 * r4 = kernel execution address
472 * r7 = architecture ID
473 * r8 = atags pointer
474 */
475 mov r0, r4
476 mov r1, sp @ malloc space above stack
477 add r2, sp, #0x10000 @ 64k max
478 mov r3, r7
479 bl decompress_kernel
480 bl cache_clean_flush
481 bl cache_off
482 mov r1, r7 @ restore architecture number
483 mov r2, r8 @ restore atags pointer
484
485 #ifdef CONFIG_ARM_VIRT_EXT
486 mrs r0, spsr @ Get saved CPU boot mode
487 and r0, r0, #MODE_MASK
488 cmp r0, #HYP_MODE @ if not booted in HYP mode...
489 bne __enter_kernel @ boot kernel directly
490
491 adr r12, .L__hyp_reentry_vectors_offset
492 ldr r0, [r12]
493 add r0, r0, r12
494
495 bl __hyp_set_vectors
496 __HVC(0) @ otherwise bounce to hyp mode
497
498 b . @ should never be reached
499
500 .align 2
501 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
502 #else
503 b __enter_kernel
504 #endif
505
506 .align 2
507 .type LC0, #object
508 LC0: .word LC0 @ r1
509 .word __bss_start @ r2
510 .word _end @ r3
511 .word _edata @ r6
512 .word input_data_end - 4 @ r10 (inflated size location)
513 .word _got_start @ r11
514 .word _got_end @ ip
515 .word .L_user_stack_end @ sp
516 .size LC0, . - LC0
517
518 #ifdef CONFIG_ARCH_RPC
519 .globl params
520 params: ldr r0, =0x10000100 @ params_phys for RPC
521 mov pc, lr
522 .ltorg
523 .align
524 #endif
525
526 /*
527 * Turn on the cache. We need to setup some page tables so that we
528 * can have both the I and D caches on.
529 *
530 * We place the page tables 16k down from the kernel execution address,
531 * and we hope that nothing else is using it. If we're using it, we
532 * will go pop!
533 *
534 * On entry,
535 * r4 = kernel execution address
536 * r7 = architecture number
537 * r8 = atags pointer
538 * On exit,
539 * r0, r1, r2, r3, r9, r10, r12 corrupted
540 * This routine must preserve:
541 * r4, r7, r8
542 */
543 .align 5
544 cache_on: mov r3, #8 @ cache_on function
545 b call_cache_fn
546
547 /*
548 * Initialize the highest priority protection region, PR7
549 * to cover all 32bit address and cacheable and bufferable.
550 */
551 __armv4_mpu_cache_on:
552 mov r0, #0x3f @ 4G, the whole
553 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
554 mcr p15, 0, r0, c6, c7, 1
555
556 mov r0, #0x80 @ PR7
557 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
558 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
559 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
560
561 mov r0, #0xc000
562 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
563 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
564
565 mov r0, #0
566 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
567 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
568 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
569 mrc p15, 0, r0, c1, c0, 0 @ read control reg
570 @ ...I .... ..D. WC.M
571 orr r0, r0, #0x002d @ .... .... ..1. 11.1
572 orr r0, r0, #0x1000 @ ...1 .... .... ....
573
574 mcr p15, 0, r0, c1, c0, 0 @ write control reg
575
576 mov r0, #0
577 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
578 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
579 mov pc, lr
580
581 __armv3_mpu_cache_on:
582 mov r0, #0x3f @ 4G, the whole
583 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
584
585 mov r0, #0x80 @ PR7
586 mcr p15, 0, r0, c2, c0, 0 @ cache on
587 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
588
589 mov r0, #0xc000
590 mcr p15, 0, r0, c5, c0, 0 @ access permission
591
592 mov r0, #0
593 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
594 /*
595 * ?? ARMv3 MMU does not allow reading the control register,
596 * does this really work on ARMv3 MPU?
597 */
598 mrc p15, 0, r0, c1, c0, 0 @ read control reg
599 @ .... .... .... WC.M
600 orr r0, r0, #0x000d @ .... .... .... 11.1
601 /* ?? this overwrites the value constructed above? */
602 mov r0, #0
603 mcr p15, 0, r0, c1, c0, 0 @ write control reg
604
605 /* ?? invalidate for the second time? */
606 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
607 mov pc, lr
608
609 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
610 #define CB_BITS 0x08
611 #else
612 #define CB_BITS 0x0c
613 #endif
614
615 __setup_mmu: sub r3, r4, #16384 @ Page directory size
616 bic r3, r3, #0xff @ Align the pointer
617 bic r3, r3, #0x3f00
618 /*
619 * Initialise the page tables, turning on the cacheable and bufferable
620 * bits for the RAM area only.
621 */
622 mov r0, r3
623 mov r9, r0, lsr #18
624 mov r9, r9, lsl #18 @ start of RAM
625 add r10, r9, #0x10000000 @ a reasonable RAM size
626 mov r1, #0x12 @ XN|U + section mapping
627 orr r1, r1, #3 << 10 @ AP=11
628 add r2, r3, #16384
629 1: cmp r1, r9 @ if virt > start of RAM
630 cmphs r10, r1 @ && end of RAM > virt
631 bic r1, r1, #0x1c @ clear XN|U + C + B
632 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
633 orrhs r1, r1, r6 @ set RAM section settings
634 str r1, [r0], #4 @ 1:1 mapping
635 add r1, r1, #1048576
636 teq r0, r2
637 bne 1b
638 /*
639 * If ever we are running from Flash, then we surely want the cache
640 * to be enabled also for our execution instance... We map 2MB of it
641 * so there is no map overlap problem for up to 1 MB compressed kernel.
642 * If the execution is in RAM then we would only be duplicating the above.
643 */
644 orr r1, r6, #0x04 @ ensure B is set for this
645 orr r1, r1, #3 << 10
646 mov r2, pc
647 mov r2, r2, lsr #20
648 orr r1, r1, r2, lsl #20
649 add r0, r3, r2, lsl #2
650 str r1, [r0], #4
651 add r1, r1, #1048576
652 str r1, [r0]
653 mov pc, lr
654 ENDPROC(__setup_mmu)
655
656 @ Enable unaligned access on v6, to allow better code generation
657 @ for the decompressor C code:
658 __armv6_mmu_cache_on:
659 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
660 bic r0, r0, #2 @ A (no unaligned access fault)
661 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
662 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
663 b __armv4_mmu_cache_on
664
665 __arm926ejs_mmu_cache_on:
666 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
667 mov r0, #4 @ put dcache in WT mode
668 mcr p15, 7, r0, c15, c0, 0
669 #endif
670
671 __armv4_mmu_cache_on:
672 mov r12, lr
673 #ifdef CONFIG_MMU
674 mov r6, #CB_BITS | 0x12 @ U
675 bl __setup_mmu
676 mov r0, #0
677 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
678 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
679 mrc p15, 0, r0, c1, c0, 0 @ read control reg
680 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
681 orr r0, r0, #0x0030
682 #ifdef CONFIG_CPU_ENDIAN_BE8
683 orr r0, r0, #1 << 25 @ big-endian page tables
684 #endif
685 bl __common_mmu_cache_on
686 mov r0, #0
687 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
688 #endif
689 mov pc, r12
690
691 __armv7_mmu_cache_on:
692 mov r12, lr
693 #ifdef CONFIG_MMU
694 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
695 tst r11, #0xf @ VMSA
696 movne r6, #CB_BITS | 0x02 @ !XN
697 blne __setup_mmu
698 mov r0, #0
699 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
700 tst r11, #0xf @ VMSA
701 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
702 #endif
703 mrc p15, 0, r0, c1, c0, 0 @ read control reg
704 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
705 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
706 orr r0, r0, #0x003c @ write buffer
707 bic r0, r0, #2 @ A (no unaligned access fault)
708 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
709 @ (needed for ARM1176)
710 #ifdef CONFIG_MMU
711 #ifdef CONFIG_CPU_ENDIAN_BE8
712 orr r0, r0, #1 << 25 @ big-endian page tables
713 #endif
714 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
715 orrne r0, r0, #1 @ MMU enabled
716 movne r1, #0xfffffffd @ domain 0 = client
717 bic r6, r6, #1 << 31 @ 32-bit translation system
718 bic r6, r6, #3 << 0 @ use only ttbr0
719 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
720 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
721 mcr p15, 0, r0, c7, c5, 4 @ ISB
722 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
723 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
724 #endif
725 mcr p15, 0, r0, c7, c5, 4 @ ISB
726 mcr p15, 0, r0, c1, c0, 0 @ load control register
727 mrc p15, 0, r0, c1, c0, 0 @ and read it back
728 mov r0, #0
729 mcr p15, 0, r0, c7, c5, 4 @ ISB
730 mov pc, r12
731
732 __fa526_cache_on:
733 mov r12, lr
734 mov r6, #CB_BITS | 0x12 @ U
735 bl __setup_mmu
736 mov r0, #0
737 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
738 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
739 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
740 mrc p15, 0, r0, c1, c0, 0 @ read control reg
741 orr r0, r0, #0x1000 @ I-cache enable
742 bl __common_mmu_cache_on
743 mov r0, #0
744 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
745 mov pc, r12
746
747 __common_mmu_cache_on:
748 #ifndef CONFIG_THUMB2_KERNEL
749 #ifndef DEBUG
750 orr r0, r0, #0x000d @ Write buffer, mmu
751 #endif
752 mov r1, #-1
753 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
754 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
755 b 1f
756 .align 5 @ cache line aligned
757 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
758 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
759 sub pc, lr, r0, lsr #32 @ properly flush pipeline
760 #endif
761
762 #define PROC_ENTRY_SIZE (4*5)
763
764 /*
765 * Here follow the relocatable cache support functions for the
766 * various processors. This is a generic hook for locating an
767 * entry and jumping to an instruction at the specified offset
768 * from the start of the block. Please note this is all position
769 * independent code.
770 *
771 * r1 = corrupted
772 * r2 = corrupted
773 * r3 = block offset
774 * r9 = corrupted
775 * r12 = corrupted
776 */
777
778 call_cache_fn: adr r12, proc_types
779 #ifdef CONFIG_CPU_CP15
780 mrc p15, 0, r9, c0, c0 @ get processor ID
781 #else
782 ldr r9, =CONFIG_PROCESSOR_ID
783 #endif
784 1: ldr r1, [r12, #0] @ get value
785 ldr r2, [r12, #4] @ get mask
786 eor r1, r1, r9 @ (real ^ match)
787 tst r1, r2 @ & mask
788 ARM( addeq pc, r12, r3 ) @ call cache function
789 THUMB( addeq r12, r3 )
790 THUMB( moveq pc, r12 ) @ call cache function
791 add r12, r12, #PROC_ENTRY_SIZE
792 b 1b
793
794 /*
795 * Table for cache operations. This is basically:
796 * - CPU ID match
797 * - CPU ID mask
798 * - 'cache on' method instruction
799 * - 'cache off' method instruction
800 * - 'cache flush' method instruction
801 *
802 * We match an entry using: ((real_id ^ match) & mask) == 0
803 *
804 * Writethrough caches generally only need 'on' and 'off'
805 * methods. Writeback caches _must_ have the flush method
806 * defined.
807 */
808 .align 2
809 .type proc_types,#object
810 proc_types:
811 .word 0x41000000 @ old ARM ID
812 .word 0xff00f000
813 mov pc, lr
814 THUMB( nop )
815 mov pc, lr
816 THUMB( nop )
817 mov pc, lr
818 THUMB( nop )
819
820 .word 0x41007000 @ ARM7/710
821 .word 0xfff8fe00
822 mov pc, lr
823 THUMB( nop )
824 mov pc, lr
825 THUMB( nop )
826 mov pc, lr
827 THUMB( nop )
828
829 .word 0x41807200 @ ARM720T (writethrough)
830 .word 0xffffff00
831 W(b) __armv4_mmu_cache_on
832 W(b) __armv4_mmu_cache_off
833 mov pc, lr
834 THUMB( nop )
835
836 .word 0x41007400 @ ARM74x
837 .word 0xff00ff00
838 W(b) __armv3_mpu_cache_on
839 W(b) __armv3_mpu_cache_off
840 W(b) __armv3_mpu_cache_flush
841
842 .word 0x41009400 @ ARM94x
843 .word 0xff00ff00
844 W(b) __armv4_mpu_cache_on
845 W(b) __armv4_mpu_cache_off
846 W(b) __armv4_mpu_cache_flush
847
848 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
849 .word 0xff0ffff0
850 W(b) __arm926ejs_mmu_cache_on
851 W(b) __armv4_mmu_cache_off
852 W(b) __armv5tej_mmu_cache_flush
853
854 .word 0x00007000 @ ARM7 IDs
855 .word 0x0000f000
856 mov pc, lr
857 THUMB( nop )
858 mov pc, lr
859 THUMB( nop )
860 mov pc, lr
861 THUMB( nop )
862
863 @ Everything from here on will be the new ID system.
864
865 .word 0x4401a100 @ sa110 / sa1100
866 .word 0xffffffe0
867 W(b) __armv4_mmu_cache_on
868 W(b) __armv4_mmu_cache_off
869 W(b) __armv4_mmu_cache_flush
870
871 .word 0x6901b110 @ sa1110
872 .word 0xfffffff0
873 W(b) __armv4_mmu_cache_on
874 W(b) __armv4_mmu_cache_off
875 W(b) __armv4_mmu_cache_flush
876
877 .word 0x56056900
878 .word 0xffffff00 @ PXA9xx
879 W(b) __armv4_mmu_cache_on
880 W(b) __armv4_mmu_cache_off
881 W(b) __armv4_mmu_cache_flush
882
883 .word 0x56158000 @ PXA168
884 .word 0xfffff000
885 W(b) __armv4_mmu_cache_on
886 W(b) __armv4_mmu_cache_off
887 W(b) __armv5tej_mmu_cache_flush
888
889 .word 0x56050000 @ Feroceon
890 .word 0xff0f0000
891 W(b) __armv4_mmu_cache_on
892 W(b) __armv4_mmu_cache_off
893 W(b) __armv5tej_mmu_cache_flush
894
895 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
896 /* this conflicts with the standard ARMv5TE entry */
897 .long 0x41009260 @ Old Feroceon
898 .long 0xff00fff0
899 b __armv4_mmu_cache_on
900 b __armv4_mmu_cache_off
901 b __armv5tej_mmu_cache_flush
902 #endif
903
904 .word 0x66015261 @ FA526
905 .word 0xff01fff1
906 W(b) __fa526_cache_on
907 W(b) __armv4_mmu_cache_off
908 W(b) __fa526_cache_flush
909
910 @ These match on the architecture ID
911
912 .word 0x00020000 @ ARMv4T
913 .word 0x000f0000
914 W(b) __armv4_mmu_cache_on
915 W(b) __armv4_mmu_cache_off
916 W(b) __armv4_mmu_cache_flush
917
918 .word 0x00050000 @ ARMv5TE
919 .word 0x000f0000
920 W(b) __armv4_mmu_cache_on
921 W(b) __armv4_mmu_cache_off
922 W(b) __armv4_mmu_cache_flush
923
924 .word 0x00060000 @ ARMv5TEJ
925 .word 0x000f0000
926 W(b) __armv4_mmu_cache_on
927 W(b) __armv4_mmu_cache_off
928 W(b) __armv5tej_mmu_cache_flush
929
930 .word 0x0007b000 @ ARMv6
931 .word 0x000ff000
932 W(b) __armv6_mmu_cache_on
933 W(b) __armv4_mmu_cache_off
934 W(b) __armv6_mmu_cache_flush
935
936 .word 0x000f0000 @ new CPU Id
937 .word 0x000f0000
938 W(b) __armv7_mmu_cache_on
939 W(b) __armv7_mmu_cache_off
940 W(b) __armv7_mmu_cache_flush
941
942 .word 0 @ unrecognised type
943 .word 0
944 mov pc, lr
945 THUMB( nop )
946 mov pc, lr
947 THUMB( nop )
948 mov pc, lr
949 THUMB( nop )
950
951 .size proc_types, . - proc_types
952
953 /*
954 * If you get a "non-constant expression in ".if" statement"
955 * error from the assembler on this line, check that you have
956 * not accidentally written a "b" instruction where you should
957 * have written W(b).
958 */
959 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
960 .error "The size of one or more proc_types entries is wrong."
961 .endif
962
963 /*
964 * Turn off the Cache and MMU. ARMv3 does not support
965 * reading the control register, but ARMv4 does.
966 *
967 * On exit,
968 * r0, r1, r2, r3, r9, r12 corrupted
969 * This routine must preserve:
970 * r4, r7, r8
971 */
972 .align 5
973 cache_off: mov r3, #12 @ cache_off function
974 b call_cache_fn
975
976 __armv4_mpu_cache_off:
977 mrc p15, 0, r0, c1, c0
978 bic r0, r0, #0x000d
979 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
980 mov r0, #0
981 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
982 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
983 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
984 mov pc, lr
985
986 __armv3_mpu_cache_off:
987 mrc p15, 0, r0, c1, c0
988 bic r0, r0, #0x000d
989 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
990 mov r0, #0
991 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
992 mov pc, lr
993
994 __armv4_mmu_cache_off:
995 #ifdef CONFIG_MMU
996 mrc p15, 0, r0, c1, c0
997 bic r0, r0, #0x000d
998 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
999 mov r0, #0
1000 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1001 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1002 #endif
1003 mov pc, lr
1004
1005 __armv7_mmu_cache_off:
1006 mrc p15, 0, r0, c1, c0
1007 #ifdef CONFIG_MMU
1008 bic r0, r0, #0x000d
1009 #else
1010 bic r0, r0, #0x000c
1011 #endif
1012 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1013 mov r12, lr
1014 bl __armv7_mmu_cache_flush
1015 mov r0, #0
1016 #ifdef CONFIG_MMU
1017 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1018 #endif
1019 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1020 mcr p15, 0, r0, c7, c10, 4 @ DSB
1021 mcr p15, 0, r0, c7, c5, 4 @ ISB
1022 mov pc, r12
1023
1024 /*
1025 * Clean and flush the cache to maintain consistency.
1026 *
1027 * On exit,
1028 * r1, r2, r3, r9, r10, r11, r12 corrupted
1029 * This routine must preserve:
1030 * r4, r6, r7, r8
1031 */
1032 .align 5
1033 cache_clean_flush:
1034 mov r3, #16
1035 b call_cache_fn
1036
1037 __armv4_mpu_cache_flush:
1038 mov r2, #1
1039 mov r3, #0
1040 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1041 mov r1, #7 << 5 @ 8 segments
1042 1: orr r3, r1, #63 << 26 @ 64 entries
1043 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1044 subs r3, r3, #1 << 26
1045 bcs 2b @ entries 63 to 0
1046 subs r1, r1, #1 << 5
1047 bcs 1b @ segments 7 to 0
1048
1049 teq r2, #0
1050 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1051 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1052 mov pc, lr
1053
1054 __fa526_cache_flush:
1055 mov r1, #0
1056 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1057 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1058 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1059 mov pc, lr
1060
1061 __armv6_mmu_cache_flush:
1062 mov r1, #0
1063 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1064 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1065 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1066 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1067 mov pc, lr
1068
1069 __armv7_mmu_cache_flush:
1070 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1071 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1072 mov r10, #0
1073 beq hierarchical
1074 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1075 b iflush
1076 hierarchical:
1077 mcr p15, 0, r10, c7, c10, 5 @ DMB
1078 stmfd sp!, {r0-r7, r9-r11}
1079 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1080 ands r3, r0, #0x7000000 @ extract loc from clidr
1081 mov r3, r3, lsr #23 @ left align loc bit field
1082 beq finished @ if loc is 0, then no need to clean
1083 mov r10, #0 @ start clean at cache level 0
1084 loop1:
1085 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1086 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1087 and r1, r1, #7 @ mask of the bits for current cache only
1088 cmp r1, #2 @ see what cache we have at this level
1089 blt skip @ skip if no cache, or just i-cache
1090 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1091 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1092 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1093 and r2, r1, #7 @ extract the length of the cache lines
1094 add r2, r2, #4 @ add 4 (line length offset)
1095 ldr r4, =0x3ff
1096 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1097 clz r5, r4 @ find bit position of way size increment
1098 ldr r7, =0x7fff
1099 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1100 loop2:
1101 mov r9, r4 @ create working copy of max way size
1102 loop3:
1103 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1104 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1105 THUMB( lsl r6, r9, r5 )
1106 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1107 THUMB( lsl r6, r7, r2 )
1108 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1109 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1110 subs r9, r9, #1 @ decrement the way
1111 bge loop3
1112 subs r7, r7, #1 @ decrement the index
1113 bge loop2
1114 skip:
1115 add r10, r10, #2 @ increment cache number
1116 cmp r3, r10
1117 bgt loop1
1118 finished:
1119 ldmfd sp!, {r0-r7, r9-r11}
1120 mov r10, #0 @ swith back to cache level 0
1121 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1122 iflush:
1123 mcr p15, 0, r10, c7, c10, 4 @ DSB
1124 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1125 mcr p15, 0, r10, c7, c10, 4 @ DSB
1126 mcr p15, 0, r10, c7, c5, 4 @ ISB
1127 mov pc, lr
1128
1129 __armv5tej_mmu_cache_flush:
1130 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1131 bne 1b
1132 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1133 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1134 mov pc, lr
1135
1136 __armv4_mmu_cache_flush:
1137 mov r2, #64*1024 @ default: 32K dcache size (*2)
1138 mov r11, #32 @ default: 32 byte line size
1139 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1140 teq r3, r9 @ cache ID register present?
1141 beq no_cache_id
1142 mov r1, r3, lsr #18
1143 and r1, r1, #7
1144 mov r2, #1024
1145 mov r2, r2, lsl r1 @ base dcache size *2
1146 tst r3, #1 << 14 @ test M bit
1147 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1148 mov r3, r3, lsr #12
1149 and r3, r3, #3
1150 mov r11, #8
1151 mov r11, r11, lsl r3 @ cache line size in bytes
1152 no_cache_id:
1153 mov r1, pc
1154 bic r1, r1, #63 @ align to longest cache line
1155 add r2, r1, r2
1156 1:
1157 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1158 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1159 THUMB( add r1, r1, r11 )
1160 teq r1, r2
1161 bne 1b
1162
1163 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1164 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1165 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1166 mov pc, lr
1167
1168 __armv3_mmu_cache_flush:
1169 __armv3_mpu_cache_flush:
1170 mov r1, #0
1171 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1172 mov pc, lr
1173
1174 /*
1175 * Various debugging routines for printing hex characters and
1176 * memory, which again must be relocatable.
1177 */
1178 #ifdef DEBUG
1179 .align 2
1180 .type phexbuf,#object
1181 phexbuf: .space 12
1182 .size phexbuf, . - phexbuf
1183
1184 @ phex corrupts {r0, r1, r2, r3}
1185 phex: adr r3, phexbuf
1186 mov r2, #0
1187 strb r2, [r3, r1]
1188 1: subs r1, r1, #1
1189 movmi r0, r3
1190 bmi puts
1191 and r2, r0, #15
1192 mov r0, r0, lsr #4
1193 cmp r2, #10
1194 addge r2, r2, #7
1195 add r2, r2, #'0'
1196 strb r2, [r3, r1]
1197 b 1b
1198
1199 @ puts corrupts {r0, r1, r2, r3}
1200 puts: loadsp r3, r1
1201 1: ldrb r2, [r0], #1
1202 teq r2, #0
1203 moveq pc, lr
1204 2: writeb r2, r3
1205 mov r1, #0x00020000
1206 3: subs r1, r1, #1
1207 bne 3b
1208 teq r2, #'\n'
1209 moveq r2, #'\r'
1210 beq 2b
1211 teq r0, #0
1212 bne 1b
1213 mov pc, lr
1214 @ putc corrupts {r0, r1, r2, r3}
1215 putc:
1216 mov r2, r0
1217 mov r0, #0
1218 loadsp r3, r1
1219 b 2b
1220
1221 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1222 memdump: mov r12, r0
1223 mov r10, lr
1224 mov r11, #0
1225 2: mov r0, r11, lsl #2
1226 add r0, r0, r12
1227 mov r1, #8
1228 bl phex
1229 mov r0, #':'
1230 bl putc
1231 1: mov r0, #' '
1232 bl putc
1233 ldr r0, [r12, r11, lsl #2]
1234 mov r1, #8
1235 bl phex
1236 and r0, r11, #7
1237 teq r0, #3
1238 moveq r0, #' '
1239 bleq putc
1240 and r0, r11, #7
1241 add r11, r11, #1
1242 teq r0, #7
1243 bne 1b
1244 mov r0, #'\n'
1245 bl putc
1246 cmp r11, #64
1247 blt 2b
1248 mov pc, r10
1249 #endif
1250
1251 .ltorg
1252
1253 #ifdef CONFIG_ARM_VIRT_EXT
1254 .align 5
1255 __hyp_reentry_vectors:
1256 W(b) . @ reset
1257 W(b) . @ undef
1258 W(b) . @ svc
1259 W(b) . @ pabort
1260 W(b) . @ dabort
1261 W(b) __enter_kernel @ hyp
1262 W(b) . @ irq
1263 W(b) . @ fiq
1264 #endif /* CONFIG_ARM_VIRT_EXT */
1265
1266 __enter_kernel:
1267 mov r0, #0 @ must be 0
1268 ARM( mov pc, r4 ) @ call kernel
1269 THUMB( bx r4 ) @ entry point is always ARM
1270
1271 reloc_code_end:
1272
1273 .align
1274 .section ".stack", "aw", %nobits
1275 .L_user_stack: .space 4096
1276 .L_user_stack_end:
kernel source for telekom puls (alcatel/mediatek)