2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
18 * Note that these macros must not contain any code which is not
19 * 100% relocatable. Any attempt to do so will result in a crash.
20 * Please select one of the following when turning on debugging.
24 #if defined(CONFIG_DEBUG_ICEDCC)
26 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
27 .macro loadsp, rb, tmp
30 mcr p14, 0, \ch, c0, c5, 0
32 #elif defined(CONFIG_CPU_XSCALE)
33 .macro loadsp, rb, tmp
36 mcr p14, 0, \ch, c8, c0, 0
39 .macro loadsp, rb, tmp
42 mcr p14, 0, \ch, c1, c0, 0
48 #include CONFIG_DEBUG_LL_INCLUDE
54 #if defined(CONFIG_ARCH_SA1100)
55 .macro loadsp, rb, tmp
56 mov \rb, #0x80000000 @ physical base address
57 #ifdef CONFIG_DEBUG_LL_SER3
58 add \rb, \rb, #0x00050000 @ Ser3
60 add \rb, \rb, #0x00010000 @ Ser1
63 #elif defined(CONFIG_ARCH_S3C24XX)
64 .macro loadsp, rb, tmp
66 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
69 .macro loadsp, rb, tmp
87 .macro debug_reloc_start
90 kphex r6, 8 /* processor id */
92 kphex r7, 8 /* architecture id */
93 #ifdef CONFIG_CPU_CP15
95 mrc p15, 0, r0, c1, c0
96 kphex r0, 8 /* control reg */
99 kphex r5, 8 /* decompressed kernel start */
101 kphex r9, 8 /* decompressed kernel end */
103 kphex r4, 8 /* kernel execution address */
108 .macro debug_reloc_end
110 kphex r5, 8 /* end of kernel */
113 bl memdump /* dump 256 bytes at start of kernel */
117 .section ".start", #alloc, #execinstr
119 * sort out different calling conventions
122 .arm @ Always enter in ARM state
124 .type start,#function
130 THUMB( adr r12, BSYM(1f) )
133 .word 0x016f2818 @ Magic numbers to help the loader
134 .word start @ absolute load/run zImage address
135 .word _edata @ zImage end address
139 #ifdef CONFIG_ARM_VIRT_EXT
140 bl __hyp_stub_install @ get into SVC mode, reversibly
142 mov r7, r1 @ save architecture ID
143 mov r8, r2 @ save atags pointer
145 #ifndef __ARM_ARCH_2__
147 * Booting from Angel - need to enter SVC mode and disable
148 * FIQs/IRQs (numeric definitions from angel arm.h source).
149 * We only do this if we were in user mode on entry.
151 mrs r2, cpsr @ get current mode
152 tst r2, #3 @ not user?
154 mov r0, #0x17 @ angel_SWIreason_EnterSVC
155 ARM( swi 0x123456 ) @ angel_SWI_ARM
156 THUMB( svc 0xab ) @ angel_SWI_THUMB
158 safe_svcmode_maskall r0
159 msr spsr_cxsf, r9 @ Save the CPU boot mode in
162 teqp pc, #0x0c000003 @ turn off interrupts
166 * Note that some cache flushing and other stuff may
167 * be needed here - is there an Angel SWI call for this?
171 * some architecture specific code can be inserted
172 * by the linker here, but it should preserve r7, r8, and r9.
177 #ifdef CONFIG_AUTO_ZRELADDR
178 @ determine final kernel image address
180 and r4, r4, #0xf8000000
181 add r4, r4, #TEXT_OFFSET
189 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
193 * We might be running at a different address. We need
194 * to fix up various pointers.
196 sub r0, r0, r1 @ calculate the delta offset
197 add r6, r6, r0 @ _edata
198 add r10, r10, r0 @ inflated kernel size location
201 * The kernel build system appends the size of the
202 * decompressed kernel at the end of the compressed data
203 * in little-endian form.
207 orr r9, r9, lr, lsl #8
210 orr r9, r9, lr, lsl #16
211 orr r9, r9, r10, lsl #24
213 #ifndef CONFIG_ZBOOT_ROM
214 /* malloc space is above the relocated stack (64k max) */
216 add r10, sp, #0x10000
219 * With ZBOOT_ROM the bss/stack is non relocatable,
220 * but someone could still run this code from RAM,
221 * in which case our reference is _edata.
226 mov r5, #0 @ init dtb size to 0
227 #ifdef CONFIG_ARM_APPENDED_DTB
232 * r4 = final kernel address
233 * r5 = appended dtb size (still unknown)
235 * r7 = architecture ID
236 * r8 = atags/device tree pointer
237 * r9 = size of decompressed image
238 * r10 = end of this image, including bss/stack/malloc space if non XIP
243 * if there are device trees (dtb) appended to zImage, advance r10 so that the
244 * dtb data will get relocated along with the kernel if necessary.
249 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
254 bne dtb_check_done @ not found
256 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
258 * OK... Let's do some funky business here.
259 * If we do have a DTB appended to zImage, and we do have
260 * an ATAG list around, we want the later to be translated
261 * and folded into the former here. To be on the safe side,
262 * let's temporarily move the stack away into the malloc
263 * area. No GOT fixup has occurred yet, but none of the
264 * code we're about to call uses any global variable.
267 stmfd sp!, {r0-r3, ip, lr}
274 * If returned value is 1, there is no ATAG at the location
275 * pointed by r8. Try the typical 0x100 offset from start
276 * of RAM and hope for the best.
279 sub r0, r4, #TEXT_OFFSET
285 ldmfd sp!, {r0-r3, ip, lr}
289 mov r8, r6 @ use the appended device tree
292 * Make sure that the DTB doesn't end up in the final
293 * kernel's .bss area. To do so, we adjust the decompressed
294 * kernel size to compensate if that .bss size is larger
295 * than the relocated code.
297 ldr r5, =_kernel_bss_size
298 adr r1, wont_overwrite
303 /* Get the dtb's size */
306 /* convert r5 (dtb size) to little endian */
307 eor r1, r5, r5, ror #16
308 bic r1, r1, #0x00ff0000
310 eor r5, r5, r1, lsr #8
313 /* preserve 64-bit alignment */
317 /* relocate some pointers past the appended dtb */
325 * Check to see if we will overwrite ourselves.
326 * r4 = final kernel address
327 * r9 = size of decompressed image
328 * r10 = end of this image, including bss/stack/malloc space if non XIP
330 * r4 - 16k page directory >= r10 -> OK
331 * r4 + image length <= address of wont_overwrite -> OK
337 adr r9, wont_overwrite
342 * Relocate ourselves past the end of the decompressed kernel.
344 * r10 = end of the decompressed kernel
345 * Because we always copy ahead, we need to do it from the end and go
346 * backward in case the source and destination overlap.
349 * Bump to the next 256-byte boundary with the size of
350 * the relocation code added. This avoids overwriting
351 * ourself when the offset is small.
353 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
356 /* Get start of code we want to copy and align it down. */
360 /* Relocate the hyp vector base if necessary */
361 #ifdef CONFIG_ARM_VIRT_EXT
363 and r0, r0, #MODE_MASK
374 sub r9, r6, r5 @ size to copy
375 add r9, r9, #31 @ rounded up to a multiple
376 bic r9, r9, #31 @ ... of 32 bytes
380 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
382 stmdb r9!, {r0 - r3, r10 - r12, lr}
385 /* Preserve offset to relocated code. */
388 #ifndef CONFIG_ZBOOT_ROM
389 /* cache_clean_flush may use the stack, so relocate it */
395 adr r0, BSYM(restart)
401 * If delta is zero, we are running at the address we were linked at.
405 * r4 = kernel execution address
406 * r5 = appended dtb size (0 if not present)
407 * r7 = architecture ID
419 #ifndef CONFIG_ZBOOT_ROM
421 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
422 * we need to fix up pointers into the BSS region.
423 * Note that the stack pointer has already been fixed up.
429 * Relocate all entries in the GOT table.
430 * Bump bss entries to _edata + dtb size
432 1: ldr r1, [r11, #0] @ relocate entries in the GOT
433 add r1, r1, r0 @ This fixes up C references
434 cmp r1, r2 @ if entry >= bss_start &&
435 cmphs r3, r1 @ bss_end > entry
436 addhi r1, r1, r5 @ entry += dtb size
437 str r1, [r11], #4 @ next entry
441 /* bump our bss pointers too */
448 * Relocate entries in the GOT table. We only relocate
449 * the entries that are outside the (relocated) BSS region.
451 1: ldr r1, [r11, #0] @ relocate entries in the GOT
452 cmp r1, r2 @ entry < bss_start ||
453 cmphs r3, r1 @ _end < entry
454 addlo r1, r1, r0 @ table. This fixes up the
455 str r1, [r11], #4 @ C references.
460 not_relocated: mov r0, #0
461 1: str r0, [r2], #4 @ clear bss
469 * The C runtime environment should now be setup sufficiently.
470 * Set up some pointers, and start decompressing.
471 * r4 = kernel execution address
472 * r7 = architecture ID
476 mov r1, sp @ malloc space above stack
477 add r2, sp, #0x10000 @ 64k max
482 mov r1, r7 @ restore architecture number
483 mov r2, r8 @ restore atags pointer
485 #ifdef CONFIG_ARM_VIRT_EXT
486 mrs r0, spsr @ Get saved CPU boot mode
487 and r0, r0, #MODE_MASK
488 cmp r0, #HYP_MODE @ if not booted in HYP mode...
489 bne __enter_kernel @ boot kernel directly
491 adr r12, .L__hyp_reentry_vectors_offset
496 __HVC(0) @ otherwise bounce to hyp mode
498 b . @ should never be reached
501 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
509 .word __bss_start @ r2
512 .word input_data_end - 4 @ r10 (inflated size location)
513 .word _got_start @ r11
515 .word .L_user_stack_end @ sp
518 #ifdef CONFIG_ARCH_RPC
520 params: ldr r0, =0x10000100 @ params_phys for RPC
527 * Turn on the cache. We need to setup some page tables so that we
528 * can have both the I and D caches on.
530 * We place the page tables 16k down from the kernel execution address,
531 * and we hope that nothing else is using it. If we're using it, we
535 * r4 = kernel execution address
536 * r7 = architecture number
539 * r0, r1, r2, r3, r9, r10, r12 corrupted
540 * This routine must preserve:
544 cache_on: mov r3, #8 @ cache_on function
548 * Initialize the highest priority protection region, PR7
549 * to cover all 32bit address and cacheable and bufferable.
551 __armv4_mpu_cache_on:
552 mov r0, #0x3f @ 4G, the whole
553 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
554 mcr p15, 0, r0, c6, c7, 1
557 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
558 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
559 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
562 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
563 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
566 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
567 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
568 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
569 mrc p15, 0, r0, c1, c0, 0 @ read control reg
570 @ ...I .... ..D. WC.M
571 orr r0, r0, #0x002d @ .... .... ..1. 11.1
572 orr r0, r0, #0x1000 @ ...1 .... .... ....
574 mcr p15, 0, r0, c1, c0, 0 @ write control reg
577 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
578 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
581 __armv3_mpu_cache_on:
582 mov r0, #0x3f @ 4G, the whole
583 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
586 mcr p15, 0, r0, c2, c0, 0 @ cache on
587 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
590 mcr p15, 0, r0, c5, c0, 0 @ access permission
593 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
595 * ?? ARMv3 MMU does not allow reading the control register,
596 * does this really work on ARMv3 MPU?
598 mrc p15, 0, r0, c1, c0, 0 @ read control reg
599 @ .... .... .... WC.M
600 orr r0, r0, #0x000d @ .... .... .... 11.1
601 /* ?? this overwrites the value constructed above? */
603 mcr p15, 0, r0, c1, c0, 0 @ write control reg
605 /* ?? invalidate for the second time? */
606 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
609 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
615 __setup_mmu: sub r3, r4, #16384 @ Page directory size
616 bic r3, r3, #0xff @ Align the pointer
619 * Initialise the page tables, turning on the cacheable and bufferable
620 * bits for the RAM area only.
624 mov r9, r9, lsl #18 @ start of RAM
625 add r10, r9, #0x10000000 @ a reasonable RAM size
626 mov r1, #0x12 @ XN|U + section mapping
627 orr r1, r1, #3 << 10 @ AP=11
629 1: cmp r1, r9 @ if virt > start of RAM
630 cmphs r10, r1 @ && end of RAM > virt
631 bic r1, r1, #0x1c @ clear XN|U + C + B
632 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
633 orrhs r1, r1, r6 @ set RAM section settings
634 str r1, [r0], #4 @ 1:1 mapping
639 * If ever we are running from Flash, then we surely want the cache
640 * to be enabled also for our execution instance... We map 2MB of it
641 * so there is no map overlap problem for up to 1 MB compressed kernel.
642 * If the execution is in RAM then we would only be duplicating the above.
644 orr r1, r6, #0x04 @ ensure B is set for this
648 orr r1, r1, r2, lsl #20
649 add r0, r3, r2, lsl #2
656 @ Enable unaligned access on v6, to allow better code generation
657 @ for the decompressor C code:
658 __armv6_mmu_cache_on:
659 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
660 bic r0, r0, #2 @ A (no unaligned access fault)
661 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
662 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
663 b __armv4_mmu_cache_on
665 __arm926ejs_mmu_cache_on:
666 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
667 mov r0, #4 @ put dcache in WT mode
668 mcr p15, 7, r0, c15, c0, 0
671 __armv4_mmu_cache_on:
674 mov r6, #CB_BITS | 0x12 @ U
677 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
678 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
679 mrc p15, 0, r0, c1, c0, 0 @ read control reg
680 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
682 #ifdef CONFIG_CPU_ENDIAN_BE8
683 orr r0, r0, #1 << 25 @ big-endian page tables
685 bl __common_mmu_cache_on
687 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
691 __armv7_mmu_cache_on:
694 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
696 movne r6, #CB_BITS | 0x02 @ !XN
699 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
701 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
703 mrc p15, 0, r0, c1, c0, 0 @ read control reg
704 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
705 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
706 orr r0, r0, #0x003c @ write buffer
707 bic r0, r0, #2 @ A (no unaligned access fault)
708 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
709 @ (needed for ARM1176)
711 #ifdef CONFIG_CPU_ENDIAN_BE8
712 orr r0, r0, #1 << 25 @ big-endian page tables
714 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
715 orrne r0, r0, #1 @ MMU enabled
716 movne r1, #0xfffffffd @ domain 0 = client
717 bic r6, r6, #1 << 31 @ 32-bit translation system
718 bic r6, r6, #3 << 0 @ use only ttbr0
719 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
720 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
721 mcr p15, 0, r0, c7, c5, 4 @ ISB
722 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
723 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
725 mcr p15, 0, r0, c7, c5, 4 @ ISB
726 mcr p15, 0, r0, c1, c0, 0 @ load control register
727 mrc p15, 0, r0, c1, c0, 0 @ and read it back
729 mcr p15, 0, r0, c7, c5, 4 @ ISB
734 mov r6, #CB_BITS | 0x12 @ U
737 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
738 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
739 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
740 mrc p15, 0, r0, c1, c0, 0 @ read control reg
741 orr r0, r0, #0x1000 @ I-cache enable
742 bl __common_mmu_cache_on
744 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
747 __common_mmu_cache_on:
748 #ifndef CONFIG_THUMB2_KERNEL
750 orr r0, r0, #0x000d @ Write buffer, mmu
753 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
754 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
756 .align 5 @ cache line aligned
757 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
758 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
759 sub pc, lr, r0, lsr #32 @ properly flush pipeline
762 #define PROC_ENTRY_SIZE (4*5)
765 * Here follow the relocatable cache support functions for the
766 * various processors. This is a generic hook for locating an
767 * entry and jumping to an instruction at the specified offset
768 * from the start of the block. Please note this is all position
778 call_cache_fn: adr r12, proc_types
779 #ifdef CONFIG_CPU_CP15
780 mrc p15, 0, r9, c0, c0 @ get processor ID
782 ldr r9, =CONFIG_PROCESSOR_ID
784 1: ldr r1, [r12, #0] @ get value
785 ldr r2, [r12, #4] @ get mask
786 eor r1, r1, r9 @ (real ^ match)
788 ARM( addeq pc, r12, r3 ) @ call cache function
789 THUMB( addeq r12, r3 )
790 THUMB( moveq pc, r12 ) @ call cache function
791 add r12, r12, #PROC_ENTRY_SIZE
795 * Table for cache operations. This is basically:
798 * - 'cache on' method instruction
799 * - 'cache off' method instruction
800 * - 'cache flush' method instruction
802 * We match an entry using: ((real_id ^ match) & mask) == 0
804 * Writethrough caches generally only need 'on' and 'off'
805 * methods. Writeback caches _must_ have the flush method
809 .type proc_types,#object
811 .word 0x41000000 @ old ARM ID
820 .word 0x41007000 @ ARM7/710
829 .word 0x41807200 @ ARM720T (writethrough)
831 W(b) __armv4_mmu_cache_on
832 W(b) __armv4_mmu_cache_off
836 .word 0x41007400 @ ARM74x
838 W(b) __armv3_mpu_cache_on
839 W(b) __armv3_mpu_cache_off
840 W(b) __armv3_mpu_cache_flush
842 .word 0x41009400 @ ARM94x
844 W(b) __armv4_mpu_cache_on
845 W(b) __armv4_mpu_cache_off
846 W(b) __armv4_mpu_cache_flush
848 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
850 W(b) __arm926ejs_mmu_cache_on
851 W(b) __armv4_mmu_cache_off
852 W(b) __armv5tej_mmu_cache_flush
854 .word 0x00007000 @ ARM7 IDs
863 @ Everything from here on will be the new ID system.
865 .word 0x4401a100 @ sa110 / sa1100
867 W(b) __armv4_mmu_cache_on
868 W(b) __armv4_mmu_cache_off
869 W(b) __armv4_mmu_cache_flush
871 .word 0x6901b110 @ sa1110
873 W(b) __armv4_mmu_cache_on
874 W(b) __armv4_mmu_cache_off
875 W(b) __armv4_mmu_cache_flush
878 .word 0xffffff00 @ PXA9xx
879 W(b) __armv4_mmu_cache_on
880 W(b) __armv4_mmu_cache_off
881 W(b) __armv4_mmu_cache_flush
883 .word 0x56158000 @ PXA168
885 W(b) __armv4_mmu_cache_on
886 W(b) __armv4_mmu_cache_off
887 W(b) __armv5tej_mmu_cache_flush
889 .word 0x56050000 @ Feroceon
891 W(b) __armv4_mmu_cache_on
892 W(b) __armv4_mmu_cache_off
893 W(b) __armv5tej_mmu_cache_flush
895 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
896 /* this conflicts with the standard ARMv5TE entry */
897 .long 0x41009260 @ Old Feroceon
899 b __armv4_mmu_cache_on
900 b __armv4_mmu_cache_off
901 b __armv5tej_mmu_cache_flush
904 .word 0x66015261 @ FA526
906 W(b) __fa526_cache_on
907 W(b) __armv4_mmu_cache_off
908 W(b) __fa526_cache_flush
910 @ These match on the architecture ID
912 .word 0x00020000 @ ARMv4T
914 W(b) __armv4_mmu_cache_on
915 W(b) __armv4_mmu_cache_off
916 W(b) __armv4_mmu_cache_flush
918 .word 0x00050000 @ ARMv5TE
920 W(b) __armv4_mmu_cache_on
921 W(b) __armv4_mmu_cache_off
922 W(b) __armv4_mmu_cache_flush
924 .word 0x00060000 @ ARMv5TEJ
926 W(b) __armv4_mmu_cache_on
927 W(b) __armv4_mmu_cache_off
928 W(b) __armv5tej_mmu_cache_flush
930 .word 0x0007b000 @ ARMv6
932 W(b) __armv6_mmu_cache_on
933 W(b) __armv4_mmu_cache_off
934 W(b) __armv6_mmu_cache_flush
936 .word 0x000f0000 @ new CPU Id
938 W(b) __armv7_mmu_cache_on
939 W(b) __armv7_mmu_cache_off
940 W(b) __armv7_mmu_cache_flush
942 .word 0 @ unrecognised type
951 .size proc_types, . - proc_types
954 * If you get a "non-constant expression in ".if" statement"
955 * error from the assembler on this line, check that you have
956 * not accidentally written a "b" instruction where you should
959 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
960 .error "The size of one or more proc_types entries is wrong."
964 * Turn off the Cache and MMU. ARMv3 does not support
965 * reading the control register, but ARMv4 does.
968 * r0, r1, r2, r3, r9, r12 corrupted
969 * This routine must preserve:
973 cache_off: mov r3, #12 @ cache_off function
976 __armv4_mpu_cache_off:
977 mrc p15, 0, r0, c1, c0
979 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
981 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
982 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
983 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
986 __armv3_mpu_cache_off:
987 mrc p15, 0, r0, c1, c0
989 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
991 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
994 __armv4_mmu_cache_off:
996 mrc p15, 0, r0, c1, c0
998 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1000 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1001 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1005 __armv7_mmu_cache_off:
1006 mrc p15, 0, r0, c1, c0
1012 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1014 bl __armv7_mmu_cache_flush
1017 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1019 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1020 mcr p15, 0, r0, c7, c10, 4 @ DSB
1021 mcr p15, 0, r0, c7, c5, 4 @ ISB
1025 * Clean and flush the cache to maintain consistency.
1028 * r1, r2, r3, r9, r10, r11, r12 corrupted
1029 * This routine must preserve:
1037 __armv4_mpu_cache_flush:
1040 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1041 mov r1, #7 << 5 @ 8 segments
1042 1: orr r3, r1, #63 << 26 @ 64 entries
1043 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1044 subs r3, r3, #1 << 26
1045 bcs 2b @ entries 63 to 0
1046 subs r1, r1, #1 << 5
1047 bcs 1b @ segments 7 to 0
1050 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1051 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1054 __fa526_cache_flush:
1056 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1057 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1058 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1061 __armv6_mmu_cache_flush:
1063 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1064 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1065 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1066 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1069 __armv7_mmu_cache_flush:
1070 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1071 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1074 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1077 mcr p15, 0, r10, c7, c10, 5 @ DMB
1078 stmfd sp!, {r0-r7, r9-r11}
1079 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1080 ands r3, r0, #0x7000000 @ extract loc from clidr
1081 mov r3, r3, lsr #23 @ left align loc bit field
1082 beq finished @ if loc is 0, then no need to clean
1083 mov r10, #0 @ start clean at cache level 0
1085 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1086 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1087 and r1, r1, #7 @ mask of the bits for current cache only
1088 cmp r1, #2 @ see what cache we have at this level
1089 blt skip @ skip if no cache, or just i-cache
1090 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1091 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1092 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1093 and r2, r1, #7 @ extract the length of the cache lines
1094 add r2, r2, #4 @ add 4 (line length offset)
1096 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1097 clz r5, r4 @ find bit position of way size increment
1099 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1101 mov r9, r4 @ create working copy of max way size
1103 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1104 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1105 THUMB( lsl r6, r9, r5 )
1106 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1107 THUMB( lsl r6, r7, r2 )
1108 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1109 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1110 subs r9, r9, #1 @ decrement the way
1112 subs r7, r7, #1 @ decrement the index
1115 add r10, r10, #2 @ increment cache number
1119 ldmfd sp!, {r0-r7, r9-r11}
1120 mov r10, #0 @ swith back to cache level 0
1121 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1123 mcr p15, 0, r10, c7, c10, 4 @ DSB
1124 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1125 mcr p15, 0, r10, c7, c10, 4 @ DSB
1126 mcr p15, 0, r10, c7, c5, 4 @ ISB
1129 __armv5tej_mmu_cache_flush:
1130 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1132 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1133 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1136 __armv4_mmu_cache_flush:
1137 mov r2, #64*1024 @ default: 32K dcache size (*2)
1138 mov r11, #32 @ default: 32 byte line size
1139 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1140 teq r3, r9 @ cache ID register present?
1145 mov r2, r2, lsl r1 @ base dcache size *2
1146 tst r3, #1 << 14 @ test M bit
1147 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1151 mov r11, r11, lsl r3 @ cache line size in bytes
1154 bic r1, r1, #63 @ align to longest cache line
1157 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1158 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1159 THUMB( add r1, r1, r11 )
1163 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1164 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1165 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1168 __armv3_mmu_cache_flush:
1169 __armv3_mpu_cache_flush:
1171 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1175 * Various debugging routines for printing hex characters and
1176 * memory, which again must be relocatable.
1180 .type phexbuf,#object
1182 .size phexbuf, . - phexbuf
1184 @ phex corrupts {r0, r1, r2, r3}
1185 phex: adr r3, phexbuf
1199 @ puts corrupts {r0, r1, r2, r3}
1201 1: ldrb r2, [r0], #1
1214 @ putc corrupts {r0, r1, r2, r3}
1221 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1222 memdump: mov r12, r0
1225 2: mov r0, r11, lsl #2
1233 ldr r0, [r12, r11, lsl #2]
1253 #ifdef CONFIG_ARM_VIRT_EXT
1255 __hyp_reentry_vectors:
1261 W(b) __enter_kernel @ hyp
1264 #endif /* CONFIG_ARM_VIRT_EXT */
1267 mov r0, #0 @ must be 0
1268 ARM( mov pc, r4 ) @ call kernel
1269 THUMB( bx r4 ) @ entry point is always ARM
1274 .section ".stack", "aw", %nobits
1275 .L_user_stack: .space 4096