4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_SUPPORTS_ATOMIC_RMW
8 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
9 select ARCH_WANT_IPC_PARSE_VERSION
10 select ARM_HAS_SG_CHAIN if (ARCH_MT6589 || ARCH_MT6582 || ARCH_MT6572 || ARCH_MT8135 || ARCH_MT6595 || ARCH_MT6795 || ARCH_MT6752 || ARCH_MT8127)
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CPU_PM if (SUSPEND || CPU_IDLE)
13 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
14 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
15 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
16 select GENERIC_IRQ_PROBE
17 select GENERIC_IRQ_SHOW
18 select GENERIC_PCI_IOMAP
19 select GENERIC_SCHED_CLOCK
20 select GENERIC_SMP_IDLE_THREAD
21 select GENERIC_IDLE_POLL_SETUP
22 select GENERIC_STRNCPY_FROM_USER
23 select GENERIC_STRNLEN_USER
24 select HARDIRQS_SW_RESEND
25 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
27 select HAVE_ARCH_SECCOMP_FILTER
28 select HAVE_ARCH_TRACEHOOK
30 select HAVE_C_RECORDMCOUNT
31 select HAVE_DEBUG_KMEMLEAK
32 select HAVE_DMA_API_DEBUG
34 select HAVE_DMA_CONTIGUOUS if MMU
35 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
36 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
37 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
38 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
39 select HAVE_GENERIC_DMA_COHERENT
40 select HAVE_GENERIC_HARDIRQS
41 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
42 select HAVE_IDE if PCI || ISA || PCMCIA
43 select HAVE_IRQ_TIME_ACCOUNTING
44 select HAVE_KERNEL_GZIP
45 select HAVE_KERNEL_LZMA
46 select HAVE_KERNEL_LZO
48 select HAVE_KPROBES if !XIP_KERNEL
49 select HAVE_KRETPROBES if (HAVE_KPROBES)
51 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
52 select HAVE_PERF_EVENTS
53 select HAVE_REGS_AND_STACK_ACCESS_API
54 select HAVE_SYSCALL_TRACEPOINTS
57 select PERF_USE_VMALLOC
59 select SYS_SUPPORTS_APM_EMULATION
60 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
61 select MODULES_USE_ELF_REL
62 select CLONE_BACKWARDS
63 select OLD_SIGSUSPEND3
65 select HAVE_CONTEXT_TRACKING
66 select CRYPTO_AES_ARM if (ARCH_MT6752)
68 The ARM series is a line of low-power-consumption RISC chip designs
69 licensed by ARM Ltd and targeted at embedded applications and
70 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
71 manufactured, but legacy ARM-based PC hardware remains popular in
72 Europe. There is an ARM Linux project with a web page at
73 <http://www.arm.linux.org.uk/>.
75 config ARM_HAS_SG_CHAIN
78 config NEED_SG_DMA_LENGTH
81 config ARM_DMA_USE_IOMMU
83 select ARM_HAS_SG_CHAIN
84 select NEED_SG_DMA_LENGTH
88 config ARM_DMA_IOMMU_ALIGNMENT
89 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
93 DMA mapping framework by default aligns all buffers to the smallest
94 PAGE_SIZE order which is greater than or equal to the requested buffer
95 size. This works well for buffers up to a few hundreds kilobytes, but
96 for larger buffers it just a waste of address space. Drivers which has
97 relatively small addressing window (like 64Mib) might run out of
98 virtual space with just a few allocations.
100 With this parameter you can specify the maximum PAGE_SIZE order for
101 DMA IOMMU buffers. Larger buffers will be aligned only to this
102 specified order. The order is expressed as a power of two multiplied
110 config MIGHT_HAVE_PCI
113 config SYS_SUPPORTS_APM_EMULATION
118 select GENERIC_ALLOCATOR
129 The Extended Industry Standard Architecture (EISA) bus was
130 developed as an open alternative to the IBM MicroChannel bus.
132 The EISA bus provided some of the features of the IBM MicroChannel
133 bus while maintaining backward compatibility with cards made for
134 the older ISA bus. The EISA bus saw limited use between 1988 and
135 1995 when it was made obsolete by the PCI bus.
137 Say Y here if you are building a kernel for an EISA-based machine.
144 config STACKTRACE_SUPPORT
148 config HAVE_LATENCYTOP_SUPPORT
153 config LOCKDEP_SUPPORT
157 config TRACE_IRQFLAGS_SUPPORT
161 config RWSEM_GENERIC_SPINLOCK
165 config RWSEM_XCHGADD_ALGORITHM
168 config ARCH_HAS_ILOG2_U32
171 config ARCH_HAS_ILOG2_U64
174 config ARCH_HAS_CPUFREQ
177 Internal node to signify that the ARCH has CPUFREQ support
178 and that the relevant menu configurations are displayed for
181 config GENERIC_HWEIGHT
185 config GENERIC_CALIBRATE_DELAY
189 config ARCH_MAY_HAVE_PC_FDC
195 config NEED_DMA_MAP_STATE
198 config ARCH_HAS_DMA_SET_COHERENT_MASK
201 config GENERIC_ISA_DMA
207 config NEED_RET_TO_USER
215 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
216 default DRAM_BASE if REMAP_VECTORS_TO_RAM
219 The base address of exception vectors. This must be two pages
222 config ARM_PATCH_PHYS_VIRT
223 bool "Patch physical to virtual translations at runtime" if EMBEDDED
225 depends on !XIP_KERNEL && MMU
226 depends on !ARCH_REALVIEW || !SPARSEMEM
228 Patch phys-to-virt and virt-to-phys translation functions at
229 boot and module load time according to the position of the
230 kernel in system memory.
232 This can only be used with non-XIP MMU kernels where the base
233 of physical memory is at a 16MB boundary.
235 Only disable this option if you know that you do not require
236 this feature (eg, building a kernel for a single machine) and
237 you need to shrink the kernel to the minimal size.
239 config NEED_MACH_GPIO_H
242 Select this when mach/gpio.h is required to provide special
243 definitions for this platform. The need for mach/gpio.h should
244 be avoided when possible.
246 config NEED_MACH_IO_H
249 Select this when mach/io.h is required to provide special
250 definitions for this platform. The need for mach/io.h should
251 be avoided when possible.
253 config NEED_MACH_MEMORY_H
256 Select this when mach/memory.h is required to provide special
257 definitions for this platform. The need for mach/memory.h should
258 be avoided when possible.
261 hex "Physical address of main memory" if MMU
262 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
263 default DRAM_BASE if !MMU
265 Please provide the physical address corresponding to the
266 location of main memory in your system.
272 source "init/Kconfig"
274 source "kernel/Kconfig.freezer"
279 bool "MMU-based Paged Memory Management Support"
282 Select if you want MMU-based virtualised addressing space
283 support by paged memory management. If unsure, say 'Y'.
286 # The "ARM system type" choice list is ordered alphabetically by option
287 # text. Please add new entries in the option alphabetic order.
290 prompt "ARM system type"
291 default ARCH_VERSATILE if !MMU
292 default ARCH_MULTIPLATFORM if MMU
294 config ARCH_MULTIPLATFORM
295 bool "Allow multiple platforms to be selected"
297 select ARM_PATCH_PHYS_VIRT
300 select MULTI_IRQ_HANDLER
304 config ARCH_INTEGRATOR
305 bool "ARM Ltd. Integrator family"
306 select ARCH_HAS_CPUFREQ
309 select COMMON_CLK_VERSATILE
310 select GENERIC_CLOCKEVENTS
313 select MULTI_IRQ_HANDLER
314 select NEED_MACH_MEMORY_H
315 select PLAT_VERSATILE
317 select VERSATILE_FPGA_IRQ
319 Support for ARM's Integrator platform.
322 bool "ARM Ltd. RealView family"
323 select ARCH_WANT_OPTIONAL_GPIOLIB
325 select ARM_TIMER_SP804
327 select COMMON_CLK_VERSATILE
328 select GENERIC_CLOCKEVENTS
329 select GPIO_PL061 if GPIOLIB
331 select NEED_MACH_MEMORY_H
332 select PLAT_VERSATILE
333 select PLAT_VERSATILE_CLCD
335 This enables support for ARM Ltd RealView boards.
337 config ARCH_VERSATILE
338 bool "ARM Ltd. Versatile family"
339 select ARCH_WANT_OPTIONAL_GPIOLIB
341 select ARM_TIMER_SP804
344 select GENERIC_CLOCKEVENTS
345 select HAVE_MACH_CLKDEV
347 select PLAT_VERSATILE
348 select PLAT_VERSATILE_CLCD
349 select PLAT_VERSATILE_CLOCK
350 select VERSATILE_FPGA_IRQ
352 This enables support for ARM Ltd Versatile board.
356 select ARCH_REQUIRE_GPIOLIB
360 select NEED_MACH_GPIO_H
361 select NEED_MACH_IO_H if PCCARD
363 select PINCTRL_AT91 if USE_OF
365 This enables support for systems based on Atmel
366 AT91RM9200 and AT91SAM9* processors.
369 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
370 select ARCH_REQUIRE_GPIOLIB
375 select GENERIC_CLOCKEVENTS
376 select MULTI_IRQ_HANDLER
377 select NEED_MACH_MEMORY_H
380 Support for Cirrus Logic 711x/721x/731x based boards.
383 bool "Cortina Systems Gemini"
384 select ARCH_REQUIRE_GPIOLIB
385 select ARCH_USES_GETTIMEOFFSET
386 select NEED_MACH_GPIO_H
389 Support for the Cortina Systems Gemini family SoCs
393 select ARCH_USES_GETTIMEOFFSET
396 select NEED_MACH_IO_H
397 select NEED_MACH_MEMORY_H
400 This is an evaluation board for the StrongARM processor available
401 from Digital. It has limited hardware on-board, including an
402 Ethernet interface, two PCMCIA sockets, two serial ports and a
407 select ARCH_HAS_HOLES_MEMORYMODEL
408 select ARCH_REQUIRE_GPIOLIB
409 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_MEMORY_H
416 This enables support for the Cirrus EP93xx series of CPUs.
418 config ARCH_FOOTBRIDGE
422 select GENERIC_CLOCKEVENTS
424 select NEED_MACH_IO_H if !MMU
425 select NEED_MACH_MEMORY_H
427 Support for systems based on the DC21285 companion chip
428 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
431 bool "Hilscher NetX based"
435 select GENERIC_CLOCKEVENTS
437 This enables support for systems based on the Hilscher NetX Soc
442 select ARCH_SUPPORTS_MSI
444 select NEED_MACH_MEMORY_H
445 select NEED_RET_TO_USER
450 Support for Intel's IOP13XX (XScale) family of processors.
455 select ARCH_REQUIRE_GPIOLIB
457 select NEED_MACH_GPIO_H
458 select NEED_RET_TO_USER
462 Support for Intel's 80219 and IOP32X (XScale) family of
468 select ARCH_REQUIRE_GPIOLIB
470 select NEED_MACH_GPIO_H
471 select NEED_RET_TO_USER
475 Support for Intel's IOP33X (XScale) family of processors.
480 select ARCH_HAS_DMA_SET_COHERENT_MASK
481 select ARCH_REQUIRE_GPIOLIB
484 select DMABOUNCE if PCI
485 select GENERIC_CLOCKEVENTS
486 select MIGHT_HAVE_PCI
487 select NEED_MACH_IO_H
488 select USB_EHCI_BIG_ENDIAN_MMIO
489 select USB_EHCI_BIG_ENDIAN_DESC
491 Support for Intel's IXP4XX (XScale) family of processors.
495 select ARCH_REQUIRE_GPIOLIB
497 select GENERIC_CLOCKEVENTS
498 select MIGHT_HAVE_PCI
501 select PLAT_ORION_LEGACY
502 select USB_ARCH_HAS_EHCI
505 Support for the Marvell Dove SoC 88AP510
508 bool "Marvell Kirkwood"
509 select ARCH_REQUIRE_GPIOLIB
511 select GENERIC_CLOCKEVENTS
515 select PINCTRL_KIRKWOOD
516 select PLAT_ORION_LEGACY
519 Support for the following Marvell Kirkwood series SoCs:
520 88F6180, 88F6192 and 88F6281.
523 bool "Marvell MV78xx0"
524 select ARCH_REQUIRE_GPIOLIB
526 select GENERIC_CLOCKEVENTS
528 select PLAT_ORION_LEGACY
531 Support for the following Marvell MV78xx0 series SoCs:
537 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
541 select PLAT_ORION_LEGACY
544 Support for the following Marvell Orion 5x series SoCs:
545 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
546 Orion-2 (5281), Orion-1-90 (6183).
549 bool "Marvell PXA168/910/MMP2"
551 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_ALLOCATOR
554 select GENERIC_CLOCKEVENTS
557 select NEED_MACH_GPIO_H
562 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
565 bool "Micrel/Kendin KS8695"
566 select ARCH_REQUIRE_GPIOLIB
569 select GENERIC_CLOCKEVENTS
570 select NEED_MACH_MEMORY_H
572 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
573 System-on-Chip devices.
576 bool "Nuvoton W90X900 CPU"
577 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
583 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
584 At present, the w90x900 has been renamed nuc900, regarding
585 the ARM series product line, you can login the following
586 link address to know more.
588 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
589 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
593 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
601 select USB_ARCH_HAS_OHCI
604 Support for the NXP LPC32XX family of processors
607 bool "PXA2xx/PXA3xx-based"
609 select ARCH_HAS_CPUFREQ
611 select ARCH_REQUIRE_GPIOLIB
612 select ARM_CPU_SUSPEND if PM
616 select GENERIC_CLOCKEVENTS
619 select MULTI_IRQ_HANDLER
620 select NEED_MACH_GPIO_H
624 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
628 select ARCH_REQUIRE_GPIOLIB
630 select GENERIC_CLOCKEVENTS
633 Support for Qualcomm MSM/QSD based systems. This runs on the
634 apps processor of the MSM/QSD and depends on a shared memory
635 interface to the modem processor which runs the baseband
636 stack and controls some vital subsystems
637 (clock and power control, etc).
640 bool "MediaTek MT6572"
642 select GENERIC_CLOCKEVENTS
643 select ARCH_HAS_CPUFREQ
647 select NEED_MACH_MEMORY_H
650 This enable support for MediaTek MT6572
653 bool "MediaTek MT6595"
655 select GENERIC_CLOCKEVENTS
656 select ARCH_HAS_CPUFREQ
660 select NEED_MACH_MEMORY_H
663 select IRQ_DOMAIN_DEBUG
664 select ARCH_REQUIRE_GPIOLIB
665 select ARM_ERRATA_828419
666 select ARM_ERRATA_828420
667 select ARM_ERRATA_831171
669 select MTK_CPU_STRESS
671 select MTK_SYSTRACKER
672 select ZONE_DMA if ARM_LPAE
674 This enable support for MediaTek MT6595
677 bool "MediaTek MT6582"
679 select GENERIC_CLOCKEVENTS
680 select ARCH_HAS_CPUFREQ
684 select NEED_MACH_MEMORY_H
687 select HAVE_TRUSTONIC_TEE_SUPPORT
688 select MTK_CPU_STRESS
690 select MTK_KERNEL_IN_SECURE_MODE if ((!TRUSTONIC_TEE_SUPPORT) && (!ARM_PSCI))
691 select FIQ_GLUE if TRUSTONIC_TEE_SUPPORT
693 This enable support for MediaTek MT6582.
696 bool "MediaTek MT6592"
698 select GENERIC_CLOCKEVENTS
699 select ARCH_HAS_CPUFREQ
703 select NEED_MACH_MEMORY_H
704 select ARM_HAS_SG_CHAIN
706 select HAVE_TRUSTONIC_TEE_SUPPORT
709 This enable support for MediaTek MT6592.
712 bool "MediaTek MT6752"
714 select GENERIC_CLOCKEVENTS
715 select ARCH_HAS_CPUFREQ
719 select NEED_MACH_MEMORY_H
721 select IRQ_DOMAIN_DEBUG
722 select GENERIC_SCHED_CLOCK
724 select MTK_SYSTRACKER
726 select ARM_ERRATA_824069
727 select ARM_ERRATA_826319
728 select ARCH_REQUIRE_GPIOLIB
732 This enable support for MediaTek MT6752
735 bool "MediaTek MT6795"
737 select GENERIC_CLOCKEVENTS
738 select ARCH_HAS_CPUFREQ
742 select NEED_MACH_MEMORY_H
745 select IRQ_DOMAIN_DEBUG
746 select GENERIC_SCHED_CLOCK
747 select ARM_ERRATA_828419
748 select ARM_ERRATA_828420
751 This enable support for MediaTek MT6795
754 bool "MediaTek MT8127"
756 select GENERIC_CLOCKEVENTS
757 select ARCH_HAS_CPUFREQ
761 select NEED_MACH_MEMORY_H
764 select IRQ_DOMAIN_DEBUG
765 select ARCH_REQUIRE_GPIOLIB
767 select HAVE_MTK_IN_HOUSE_TEE_SUPPORT
769 This enable support for MediaTek MT8127
772 bool "Renesas SH-Mobile / R-Mobile"
774 select GENERIC_CLOCKEVENTS
775 select HAVE_ARM_SCU if SMP
776 select HAVE_ARM_TWD if LOCAL_TIMERS
778 select HAVE_MACH_CLKDEV
780 select MIGHT_HAVE_CACHE_L2X0
781 select MULTI_IRQ_HANDLER
782 select NEED_MACH_MEMORY_H
784 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
785 select PM_GENERIC_DOMAINS if PM
788 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
793 select ARCH_MAY_HAVE_PC_FDC
794 select ARCH_SPARSEMEM_ENABLE
795 select ARCH_USES_GETTIMEOFFSET
798 select HAVE_PATA_PLATFORM
800 select NEED_MACH_IO_H
801 select NEED_MACH_MEMORY_H
805 On the Acorn Risc-PC, Linux can support the internal IDE disk and
806 CD-ROM interface, serial and parallel port, and the floppy drive.
810 select ARCH_HAS_CPUFREQ
812 select ARCH_REQUIRE_GPIOLIB
813 select ARCH_SPARSEMEM_ENABLE
818 select GENERIC_CLOCKEVENTS
821 select NEED_MACH_GPIO_H
822 select NEED_MACH_MEMORY_H
825 Support for StrongARM 11x0 based boards.
828 bool "Samsung S3C24XX SoCs"
829 select ARCH_HAS_CPUFREQ
830 select ARCH_REQUIRE_GPIOLIB
833 select GENERIC_CLOCKEVENTS
835 select HAVE_S3C2410_I2C if I2C
836 select HAVE_S3C2410_WATCHDOG if WATCHDOG
837 select HAVE_S3C_RTC if RTC_CLASS
838 select MULTI_IRQ_HANDLER
839 select NEED_MACH_GPIO_H
840 select NEED_MACH_IO_H
842 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
843 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
844 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
845 Samsung SMDK2410 development board (and derivatives).
848 bool "Samsung S3C64XX"
849 select ARCH_HAS_CPUFREQ
850 select ARCH_REQUIRE_GPIOLIB
855 select GENERIC_CLOCKEVENTS
857 select HAVE_S3C2410_I2C if I2C
858 select HAVE_S3C2410_WATCHDOG if WATCHDOG
860 select NEED_MACH_GPIO_H
864 select S3C_GPIO_TRACK
865 select SAMSUNG_CLKSRC
866 select SAMSUNG_GPIOLIB_4BIT
867 select SAMSUNG_IRQ_VIC_TIMER
868 select USB_ARCH_HAS_OHCI
870 Samsung S3C64XX series based systems
873 bool "Samsung S5P6440 S5P6450"
877 select GENERIC_CLOCKEVENTS
879 select HAVE_S3C2410_I2C if I2C
880 select HAVE_S3C2410_WATCHDOG if WATCHDOG
881 select HAVE_S3C_RTC if RTC_CLASS
882 select NEED_MACH_GPIO_H
884 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
888 bool "Samsung S5PC100"
889 select ARCH_REQUIRE_GPIOLIB
893 select GENERIC_CLOCKEVENTS
895 select HAVE_S3C2410_I2C if I2C
896 select HAVE_S3C2410_WATCHDOG if WATCHDOG
897 select HAVE_S3C_RTC if RTC_CLASS
898 select NEED_MACH_GPIO_H
900 Samsung S5PC100 series based systems
903 bool "Samsung S5PV210/S5PC110"
904 select ARCH_HAS_CPUFREQ
905 select ARCH_HAS_HOLES_MEMORYMODEL
906 select ARCH_SPARSEMEM_ENABLE
910 select GENERIC_CLOCKEVENTS
912 select HAVE_S3C2410_I2C if I2C
913 select HAVE_S3C2410_WATCHDOG if WATCHDOG
914 select HAVE_S3C_RTC if RTC_CLASS
915 select NEED_MACH_GPIO_H
916 select NEED_MACH_MEMORY_H
918 Samsung S5PV210/S5PC110 series based systems
921 bool "Samsung EXYNOS"
922 select ARCH_HAS_CPUFREQ
923 select ARCH_HAS_HOLES_MEMORYMODEL
924 select ARCH_SPARSEMEM_ENABLE
928 select GENERIC_CLOCKEVENTS
930 select HAVE_S3C2410_I2C if I2C
931 select HAVE_S3C2410_WATCHDOG if WATCHDOG
932 select HAVE_S3C_RTC if RTC_CLASS
933 select NEED_MACH_GPIO_H
934 select NEED_MACH_MEMORY_H
936 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
940 select ARCH_USES_GETTIMEOFFSET
944 select NEED_MACH_MEMORY_H
949 Support for the StrongARM based Digital DNARD machine, also known
950 as "Shark" (<http://www.shark-linux.de/shark.html>).
953 bool "ST-Ericsson U300 Series"
955 select ARCH_REQUIRE_GPIOLIB
957 select ARM_PATCH_PHYS_VIRT
963 select GENERIC_CLOCKEVENTS
967 Support for ST-Ericsson U300 series mobile platforms.
971 select ARCH_HAS_HOLES_MEMORYMODEL
972 select ARCH_REQUIRE_GPIOLIB
974 select GENERIC_ALLOCATOR
975 select GENERIC_CLOCKEVENTS
976 select GENERIC_IRQ_CHIP
978 select NEED_MACH_GPIO_H
982 Support for TI's DaVinci platform.
987 select ARCH_HAS_CPUFREQ
988 select ARCH_HAS_HOLES_MEMORYMODEL
990 select ARCH_REQUIRE_GPIOLIB
993 select GENERIC_CLOCKEVENTS
994 select GENERIC_IRQ_CHIP
998 select NEED_MACH_IO_H if PCCARD
999 select NEED_MACH_MEMORY_H
1001 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
1005 menu "Multiple platform selection"
1006 depends on ARCH_MULTIPLATFORM
1008 comment "CPU Core family selection"
1010 config ARCH_MULTI_V4
1011 bool "ARMv4 based platforms (FA526, StrongARM)"
1012 depends on !ARCH_MULTI_V6_V7
1013 select ARCH_MULTI_V4_V5
1015 config ARCH_MULTI_V4T
1016 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
1017 depends on !ARCH_MULTI_V6_V7
1018 select ARCH_MULTI_V4_V5
1020 config ARCH_MULTI_V5
1021 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1022 depends on !ARCH_MULTI_V6_V7
1023 select ARCH_MULTI_V4_V5
1025 config ARCH_MULTI_V4_V5
1028 config ARCH_MULTI_V6
1029 bool "ARMv6 based platforms (ARM11)"
1030 select ARCH_MULTI_V6_V7
1033 config ARCH_MULTI_V7
1034 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
1036 select ARCH_MULTI_V6_V7
1039 config ARCH_MULTI_V6_V7
1042 config ARCH_MULTI_CPU_AUTO
1043 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1044 select ARCH_MULTI_V5
1049 # This is sorted alphabetically by mach-* pathname. However, plat-*
1050 # Kconfigs may be included either alphabetically (according to the
1051 # plat- suffix) or along side the corresponding mach-* source.
1053 source "arch/arm/mach-mvebu/Kconfig"
1055 source "arch/arm/mach-at91/Kconfig"
1057 source "arch/arm/mach-bcm/Kconfig"
1059 source "arch/arm/mach-bcm2835/Kconfig"
1061 source "arch/arm/mach-clps711x/Kconfig"
1063 source "arch/arm/mach-cns3xxx/Kconfig"
1065 source "arch/arm/mach-davinci/Kconfig"
1067 source "arch/arm/mach-dove/Kconfig"
1069 source "arch/arm/mach-ep93xx/Kconfig"
1071 source "arch/arm/mach-footbridge/Kconfig"
1073 source "arch/arm/mach-gemini/Kconfig"
1075 source "arch/arm/mach-highbank/Kconfig"
1077 source "arch/arm/mach-integrator/Kconfig"
1079 source "arch/arm/mach-iop32x/Kconfig"
1081 source "arch/arm/mach-iop33x/Kconfig"
1083 source "arch/arm/mach-iop13xx/Kconfig"
1085 source "arch/arm/mach-ixp4xx/Kconfig"
1087 source "arch/arm/mach-kirkwood/Kconfig"
1089 source "arch/arm/mach-ks8695/Kconfig"
1091 source "arch/arm/mach-msm/Kconfig"
1094 #source "arch/arm/mach-mt6572/Kconfig"
1098 #source "arch/arm/mach-mt6582/Kconfig"
1102 #source "arch/arm/mach-mt6592/Kconfig"
1106 source "arch/arm/mach-mt8127/Kconfig"
1109 source "drivers/misc/mediatek/mach/Kconfig"
1111 source "arch/arm/mach-mv78xx0/Kconfig"
1113 source "arch/arm/mach-imx/Kconfig"
1115 source "arch/arm/mach-mxs/Kconfig"
1117 source "arch/arm/mach-netx/Kconfig"
1119 source "arch/arm/mach-nomadik/Kconfig"
1121 source "arch/arm/plat-omap/Kconfig"
1123 source "arch/arm/mach-omap1/Kconfig"
1125 source "arch/arm/mach-omap2/Kconfig"
1127 source "arch/arm/mach-orion5x/Kconfig"
1129 source "arch/arm/mach-picoxcell/Kconfig"
1131 source "arch/arm/mach-pxa/Kconfig"
1132 source "arch/arm/plat-pxa/Kconfig"
1134 source "arch/arm/mach-mmp/Kconfig"
1136 source "arch/arm/mach-realview/Kconfig"
1138 source "arch/arm/mach-sa1100/Kconfig"
1140 source "arch/arm/plat-samsung/Kconfig"
1142 source "arch/arm/mach-socfpga/Kconfig"
1144 source "arch/arm/mach-spear/Kconfig"
1146 source "arch/arm/mach-s3c24xx/Kconfig"
1149 source "arch/arm/mach-s3c64xx/Kconfig"
1152 source "arch/arm/mach-s5p64x0/Kconfig"
1154 source "arch/arm/mach-s5pc100/Kconfig"
1156 source "arch/arm/mach-s5pv210/Kconfig"
1158 source "arch/arm/mach-exynos/Kconfig"
1160 source "arch/arm/mach-shmobile/Kconfig"
1162 source "arch/arm/mach-sunxi/Kconfig"
1164 source "arch/arm/mach-prima2/Kconfig"
1166 source "arch/arm/mach-tegra/Kconfig"
1168 source "arch/arm/mach-u300/Kconfig"
1170 source "arch/arm/mach-ux500/Kconfig"
1172 source "arch/arm/mach-versatile/Kconfig"
1174 source "arch/arm/mach-vexpress/Kconfig"
1175 source "arch/arm/plat-versatile/Kconfig"
1177 source "arch/arm/mach-virt/Kconfig"
1179 source "arch/arm/mach-vt8500/Kconfig"
1181 source "arch/arm/mach-w90x900/Kconfig"
1183 source "arch/arm/mach-zynq/Kconfig"
1185 # Definitions to make life easier
1191 select GENERIC_CLOCKEVENTS
1197 select GENERIC_IRQ_CHIP
1200 config PLAT_ORION_LEGACY
1207 config PLAT_VERSATILE
1210 config ARM_TIMER_SP804
1213 select CLKSRC_OF if OF
1215 source arch/arm/mm/Kconfig
1219 default 16 if ARCH_EP93XX
1223 bool "Enable iWMMXt support" if !CPU_PJ4
1224 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1225 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1227 Enable support for iWMMXt context switching at run time if
1228 running on a CPU that supports it.
1232 depends on CPU_XSCALE
1235 config MULTI_IRQ_HANDLER
1238 Allow each machine to specify it's own IRQ handler at run time.
1241 source "arch/arm/Kconfig-nommu"
1244 config MTK_KERNEL_IN_SECURE_MODE
1245 bool "MTK's kernel runs in secure mode"
1246 depends on ((!TRUSTONIC_TEE_SUPPORT) && (!ARM_PSCI))
1248 Indication to kernel's mode. (secure or non-secure)
1251 bool "MTK's cache operation fixup"
1253 Use two stages of cache operations to do flush
1255 config PJ4B_ERRATA_4742
1256 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1257 depends on CPU_PJ4B && MACH_ARMADA_370
1260 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1261 Event (WFE) IDLE states, a specific timing sensitivity exists between
1262 the retiring WFI/WFE instructions and the newly issued subsequent
1263 instructions. This sensitivity can result in a CPU hang scenario.
1265 The software must insert either a Data Synchronization Barrier (DSB)
1266 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1269 config ARM_ERRATA_326103
1270 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1273 Executing a SWP instruction to read-only memory does not set bit 11
1274 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1275 treat the access as a read, preventing a COW from occurring and
1276 causing the faulting task to livelock.
1278 config ARM_ERRATA_411920
1279 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1280 depends on CPU_V6 || CPU_V6K
1282 Invalidation of the Instruction Cache operation can
1283 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1284 It does not affect the MPCore. This option enables the ARM Ltd.
1285 recommended workaround.
1287 config ARM_ERRATA_430973
1288 bool "ARM errata: Stale prediction on replaced interworking branch"
1291 This option enables the workaround for the 430973 Cortex-A8
1292 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1293 interworking branch is replaced with another code sequence at the
1294 same virtual address, whether due to self-modifying code or virtual
1295 to physical address re-mapping, Cortex-A8 does not recover from the
1296 stale interworking branch prediction. This results in Cortex-A8
1297 executing the new code sequence in the incorrect ARM or Thumb state.
1298 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1299 and also flushes the branch target cache at every context switch.
1300 Note that setting specific bits in the ACTLR register may not be
1301 available in non-secure mode.
1303 config ARM_ERRATA_458693
1304 bool "ARM errata: Processor deadlock when a false hazard is created"
1306 depends on !ARCH_MULTIPLATFORM
1308 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1309 erratum. For very specific sequences of memory operations, it is
1310 possible for a hazard condition intended for a cache line to instead
1311 be incorrectly associated with a different cache line. This false
1312 hazard might then cause a processor deadlock. The workaround enables
1313 the L1 caching of the NEON accesses and disables the PLD instruction
1314 in the ACTLR register. Note that setting specific bits in the ACTLR
1315 register may not be available in non-secure mode.
1317 config ARM_ERRATA_460075
1318 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1320 depends on !ARCH_MULTIPLATFORM
1322 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1323 erratum. Any asynchronous access to the L2 cache may encounter a
1324 situation in which recent store transactions to the L2 cache are lost
1325 and overwritten with stale memory contents from external memory. The
1326 workaround disables the write-allocate mode for the L2 cache via the
1327 ACTLR register. Note that setting specific bits in the ACTLR register
1328 may not be available in non-secure mode.
1330 config ARM_ERRATA_742230
1331 bool "ARM errata: DMB operation may be faulty"
1332 depends on CPU_V7 && SMP
1333 depends on !ARCH_MULTIPLATFORM
1335 This option enables the workaround for the 742230 Cortex-A9
1336 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1337 between two write operations may not ensure the correct visibility
1338 ordering of the two writes. This workaround sets a specific bit in
1339 the diagnostic register of the Cortex-A9 which causes the DMB
1340 instruction to behave as a DSB, ensuring the correct behaviour of
1343 config ARM_ERRATA_742231
1344 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1345 depends on CPU_V7 && SMP
1346 depends on !ARCH_MULTIPLATFORM
1348 This option enables the workaround for the 742231 Cortex-A9
1349 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1350 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1351 accessing some data located in the same cache line, may get corrupted
1352 data due to bad handling of the address hazard when the line gets
1353 replaced from one of the CPUs at the same time as another CPU is
1354 accessing it. This workaround sets specific bits in the diagnostic
1355 register of the Cortex-A9 which reduces the linefill issuing
1356 capabilities of the processor.
1358 config PL310_ERRATA_588369
1359 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1360 depends on CACHE_L2X0
1362 The PL310 L2 cache controller implements three types of Clean &
1363 Invalidate maintenance operations: by Physical Address
1364 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1365 They are architecturally defined to behave as the execution of a
1366 clean operation followed immediately by an invalidate operation,
1367 both performing to the same memory location. This functionality
1368 is not correctly implemented in PL310 as clean lines are not
1369 invalidated as a result of these operations.
1371 config ARM_ERRATA_643719
1372 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1373 depends on CPU_V7 && SMP
1375 This option enables the workaround for the 643719 Cortex-A9 (prior to
1376 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1377 register returns zero when it should return one. The workaround
1378 corrects this value, ensuring cache maintenance operations which use
1379 it behave as intended and avoiding data corruption.
1381 config ARM_ERRATA_720789
1382 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1385 This option enables the workaround for the 720789 Cortex-A9 (prior to
1386 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1387 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1388 As a consequence of this erratum, some TLB entries which should be
1389 invalidated are not, resulting in an incoherency in the system page
1390 tables. The workaround changes the TLB flushing routines to invalidate
1391 entries regardless of the ASID.
1393 config PL310_ERRATA_727915
1394 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1395 depends on CACHE_L2X0
1397 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1398 operation (offset 0x7FC). This operation runs in background so that
1399 PL310 can handle normal accesses while it is in progress. Under very
1400 rare circumstances, due to this erratum, write data can be lost when
1401 PL310 treats a cacheable write transaction during a Clean &
1402 Invalidate by Way operation.
1404 config ARM_ERRATA_743622
1405 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1407 depends on !ARCH_MULTIPLATFORM
1409 This option enables the workaround for the 743622 Cortex-A9
1410 (r2p*) erratum. Under very rare conditions, a faulty
1411 optimisation in the Cortex-A9 Store Buffer may lead to data
1412 corruption. This workaround sets a specific bit in the diagnostic
1413 register of the Cortex-A9 which disables the Store Buffer
1414 optimisation, preventing the defect from occurring. This has no
1415 visible impact on the overall performance or power consumption of the
1418 config ARM_ERRATA_751472
1419 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1421 depends on !ARCH_MULTIPLATFORM
1423 This option enables the workaround for the 751472 Cortex-A9 (prior
1424 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1425 completion of a following broadcasted operation if the second
1426 operation is received by a CPU before the ICIALLUIS has completed,
1427 potentially leading to corrupted entries in the cache or TLB.
1429 config PL310_ERRATA_753970
1430 bool "PL310 errata: cache sync operation may be faulty"
1431 depends on CACHE_PL310
1433 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1435 Under some condition the effect of cache sync operation on
1436 the store buffer still remains when the operation completes.
1437 This means that the store buffer is always asked to drain and
1438 this prevents it from merging any further writes. The workaround
1439 is to replace the normal offset of cache sync operation (0x730)
1440 by another offset targeting an unmapped PL310 register 0x740.
1441 This has the same effect as the cache sync operation: store buffer
1442 drain and waiting for all buffers empty.
1444 config ARM_ERRATA_754322
1445 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1448 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1449 r3p*) erratum. A speculative memory access may cause a page table walk
1450 which starts prior to an ASID switch but completes afterwards. This
1451 can populate the micro-TLB with a stale entry which may be hit with
1452 the new ASID. This workaround places two dsb instructions in the mm
1453 switching code so that no page table walks can cross the ASID switch.
1455 config ARM_ERRATA_754327
1456 bool "ARM errata: no automatic Store Buffer drain"
1457 depends on CPU_V7 && SMP
1459 This option enables the workaround for the 754327 Cortex-A9 (prior to
1460 r2p0) erratum. The Store Buffer does not have any automatic draining
1461 mechanism and therefore a livelock may occur if an external agent
1462 continuously polls a memory location waiting to observe an update.
1463 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1464 written polling loops from denying visibility of updates to memory.
1466 config ARM_ERRATA_364296
1467 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1468 depends on CPU_V6 && !SMP
1470 This options enables the workaround for the 364296 ARM1136
1471 r0p2 erratum (possible cache data corruption with
1472 hit-under-miss enabled). It sets the undocumented bit 31 in
1473 the auxiliary control register and the FI bit in the control
1474 register, thus disabling hit-under-miss without putting the
1475 processor into full low interrupt latency mode. ARM11MPCore
1478 config ARM_ERRATA_764369
1479 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1480 depends on CPU_V7 && SMP
1482 This option enables the workaround for erratum 764369
1483 affecting Cortex-A9 MPCore with two or more processors (all
1484 current revisions). Under certain timing circumstances, a data
1485 cache line maintenance operation by MVA targeting an Inner
1486 Shareable memory region may fail to proceed up to either the
1487 Point of Coherency or to the Point of Unification of the
1488 system. This workaround adds a DSB instruction before the
1489 relevant cache maintenance functions and sets a specific bit
1490 in the diagnostic control register of the SCU.
1492 config PL310_ERRATA_769419
1493 bool "PL310 errata: no automatic Store Buffer drain"
1494 depends on CACHE_L2X0
1496 On revisions of the PL310 prior to r3p2, the Store Buffer does
1497 not automatically drain. This can cause normal, non-cacheable
1498 writes to be retained when the memory system is idle, leading
1499 to suboptimal I/O performance for drivers using coherent DMA.
1500 This option adds a write barrier to the cpu_idle loop so that,
1501 on systems with an outer cache, the store buffer is drained
1504 config ARM_ERRATA_775420
1505 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1508 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1509 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1510 operation aborts with MMU exception, it might cause the processor
1511 to deadlock. This workaround puts DSB before executing ISB if
1512 an abort may occur on cache maintenance.
1514 config ARM_ERRATA_798181
1515 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1516 depends on CPU_V7 && SMP
1518 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1519 adequately shooting down all use of the old entries. This
1520 option enables the Linux kernel workaround for this erratum
1521 which sends an IPI to the CPUs that are running the same ASID
1522 as the one being invalidated.
1524 config ARM_ERRATA_828419
1526 depends on CPU_V7 && SMP
1528 ARM errata: A Instruction Cache Maintenance Operation by MVA with an incorrect NS descriptor
1529 This workaround is to replace ICIMVAU operations by ICIALLUIS operations
1531 config ARM_ERRATA_828420
1533 depends on CPU_V7 && SMP
1535 ARM errata: Cache Clean by MVA to PoC might not be correctly executed
1536 The software workaround is to treat every Data Clean by MVA to PoC
1537 as Data Clean Invalidate by MVA to PoC.
1539 config ARM_ERRATA_831171
1541 depends on CPU_V7 && SMP
1543 ARM errata: Within rare timing constraints, a DSB following a TLB or ICache invalidation might complete
1544 before the TLB or ICache invalidation has effectively completed on other CPUs within the cluster
1545 The software workaround is to issue the TLB or ICache maintenance invalidation twice before the DSB
1547 config ARM_ERRATA_824069
1551 This option enables the workaround for erratum 824069
1552 affecting Cortex-A53 MPCore with two or more processors (r0p0..r0p2).
1553 If a Cortex-A53 processor is executing a store or PLDW instruction at the same time
1554 as a processor in another cluster is executing a cache maintenance operation
1555 to the same address, then this erratum might cause a clean cache line to be
1556 incorrectly marked as dirty. This workaround replaces all cache clean opeartion
1557 to clean & invalidate.
1559 config ARM_ERRATA_826319
1563 This option enables the workaround for erratum 826319
1564 affecting Cortex-A53 MPCore with two or more processors (r0p0..r0p2).
1565 This erratum only affects configurations of the Cortex-A53 processor with an ABMA 4 ACE or AXI master interface and an L2 cache.
1566 To be affected by this erratum, the system that Cortex-A53 is connected to must also contain a peripheral or
1567 other component that contains a dependency between the read and write channels. The dependency must
1568 prevent the peripheral from accepting or responding to a write until it finishes processing a read.
1572 source "arch/arm/common/Kconfig"
1582 Find out whether you have ISA slots on your motherboard. ISA is the
1583 name of a bus system, i.e. the way the CPU talks to the other stuff
1584 inside your box. Other bus systems are PCI, EISA, MicroChannel
1585 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1586 newer boards don't support it. If you have ISA, say Y, otherwise N.
1588 # Select ISA DMA controller support
1593 # Select ISA DMA interface
1598 bool "PCI support" if MIGHT_HAVE_PCI
1600 Find out whether you have a PCI motherboard. PCI is the name of a
1601 bus system, i.e. the way the CPU talks to the other stuff inside
1602 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1603 VESA. If you have PCI, say Y, otherwise N.
1609 config PCI_NANOENGINE
1610 bool "BSE nanoEngine PCI support"
1611 depends on SA1100_NANOENGINE
1613 Enable PCI on the BSE nanoEngine board.
1618 # Select the host bridge type
1619 config PCI_HOST_VIA82C505
1621 depends on PCI && ARCH_SHARK
1624 config PCI_HOST_ITE8152
1626 depends on PCI && MACH_ARMCORE
1630 source "drivers/pci/Kconfig"
1632 source "drivers/pcmcia/Kconfig"
1636 menu "Kernel Features"
1641 This option should be selected by machines which have an SMP-
1644 The only effect of this option is to make the SMP-related
1645 options available to the user for configuration.
1648 bool "Symmetric Multi-Processing"
1649 depends on CPU_V6K || CPU_V7
1650 depends on GENERIC_CLOCKEVENTS
1653 select USE_GENERIC_SMP_HELPERS
1655 This enables support for systems with more than one CPU. If you have
1656 a system with only one CPU, like most personal computers, say N. If
1657 you have a system with more than one CPU, say Y.
1659 If you say N here, the kernel will run on single and multiprocessor
1660 machines, but will use only one CPU of a multiprocessor machine. If
1661 you say Y here, the kernel will run on many, but not all, single
1662 processor machines. On a single processor machine, the kernel will
1663 run faster if you say N here.
1665 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1666 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1667 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1669 If you don't know what to do here, say N.
1672 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1673 depends on SMP && !XIP_KERNEL
1676 SMP kernels contain instructions which fail on non-SMP processors.
1677 Enabling this option allows the kernel to modify itself to make
1678 these instructions safe. Disabling it allows about 1K of space
1681 If you don't know what to do here, say Y.
1683 config ARM_CPU_TOPOLOGY
1684 bool "Support cpu topology definition"
1685 depends on SMP && CPU_V7
1688 Support ARM cpu topology definition. The MPIDR register defines
1689 affinity between processors which is then used to describe the cpu
1690 topology of an ARM System.
1693 bool "Multi-core scheduler support"
1694 depends on ARM_CPU_TOPOLOGY
1696 Multi-core scheduler support improves the CPU scheduler's decision
1697 making when dealing with multi-core CPU chips at a cost of slightly
1698 increased overhead in some places. If unsure say N here.
1701 bool "SMT scheduler support"
1702 depends on ARM_CPU_TOPOLOGY
1704 Improves the CPU scheduler's decision making when dealing with
1705 MultiThreading at a cost of slightly increased overhead in some
1706 places. If unsure say N here.
1708 config DISABLE_CPU_SCHED_DOMAIN_BALANCE
1709 bool "(EXPERIMENTAL) Disable CPU level scheduler load-balancing"
1711 Disables scheduler load-balancing at CPU sched domain level.
1714 bool "(EXPERIMENTAL) Heterogenous multiprocessor scheduling"
1715 depends on DISABLE_CPU_SCHED_DOMAIN_BALANCE && SCHED_MC && FAIR_GROUP_SCHED && !SCHED_AUTOGROUP
1717 Experimental scheduler optimizations for heterogeneous platforms.
1718 Attempts to introspectively select task affinity to optimize power
1719 and performance. Basic support for multiple (>2) cpu types is in place,
1720 but it has only been tested with two types of cpus.
1721 There is currently no support for migration of task groups, hence
1722 !SCHED_AUTOGROUP. Furthermore, normal load-balancing must be disabled
1723 between cpus of different type (DISABLE_CPU_SCHED_DOMAIN_BALANCE).
1725 config SCHED_HMP_PRIO_FILTER
1726 bool "(EXPERIMENTAL) Filter HMP migrations by task priority"
1727 depends on SCHED_HMP
1729 Enables task priority based HMP migration filter. Any task with
1730 a NICE value above the threshold will always be on low-power cpus
1731 with less compute capacity.
1733 config SCHED_HMP_PRIO_FILTER_VAL
1734 int "NICE priority threshold"
1736 depends on SCHED_HMP_PRIO_FILTER
1738 config HMP_FAST_CPU_MASK
1739 string "HMP scheduler fast CPU mask"
1740 depends on SCHED_HMP
1742 Leave empty to use device tree information.
1743 Specify the cpuids of the fast CPUs in the system as a list string,
1744 e.g. cpuid 0+1 should be specified as 0-1.
1746 config HMP_SLOW_CPU_MASK
1747 string "HMP scheduler slow CPU mask"
1748 depends on SCHED_HMP
1750 Leave empty to use device tree information.
1751 Specify the cpuids of the slow CPUs in the system as a list string,
1752 e.g. cpuid 0+1 should be specified as 0-1.
1754 config HMP_VARIABLE_SCALE
1755 bool "Allows changing the load tracking scale through sysfs"
1756 depends on SCHED_HMP
1758 When turned on, this option exports the thresholds and load average
1759 period value for the load tracking patches through sysfs.
1760 The values can be modified to change the rate of load accumulation
1761 and the thresholds used for HMP migration.
1762 The load_avg_period_ms is the time in ms to reach a load average of
1763 0.5 for an idle task of 0 load average ratio that start a busy loop.
1764 The up_threshold and down_threshold is the value to go to a faster
1765 CPU or to go back to a slower cpu.
1766 The {up,down}_threshold are devided by 1024 before being compared
1767 to the load average.
1768 For examples, with load_avg_period_ms = 128 and up_threshold = 512,
1769 a running task with a load of 0 will be migrated to a bigger CPU after
1770 128ms, because after 128ms its load_avg_ratio is 0.5 and the real
1771 up_threshold is 0.5.
1772 This patch has the same behavior as changing the Y of the load
1773 average computation to
1774 (1002/1024)^(LOAD_AVG_PERIOD/load_avg_period_ms)
1775 but it remove intermadiate overflows in computation.
1777 config MET_SCHED_HMP
1778 bool "(EXPERIMENTAL) MET SCHED HMP Info"
1779 depends on SCHED_HMP_ENHANCEMENT
1780 depends on HMP_TRACER
1784 config HMP_FREQUENCY_INVARIANT_SCALE
1785 bool "(EXPERIMENTAL) Frequency-Invariant Tracked Load for HMP"
1786 depends on HMP_VARIABLE_SCALE && CPU_FREQ
1787 depends on !ARCH_SCALE_INVARIANT_CPU_CAPACITY
1789 Scales the current load contribution in line with the frequency
1790 of the CPU that the task was executed on.
1791 In this version, we use a simple linear scale derived from the
1792 maximum frequency reported by CPUFreq.
1793 Restricting tracked load to be scaled by the CPU's frequency
1794 represents the consumption of possible compute capacity
1795 (rather than consumption of actual instantaneous capacity as
1796 normal) and allows the HMP migration's simple threshold
1797 migration strategy to interact more predictably with CPUFreq's
1798 asynchronous compute capacity changes.
1800 config SCHED_HMP_ENHANCEMENT
1801 bool "(EXPERIMENTAL) HMP Ennhancement"
1802 depends on SCHED_HMP
1807 bool "(EXPERIMENTAL) Profile HMP scheduler"
1808 depends on SCHED_HMP_ENHANCEMENT
1810 Profile HMP scheduler
1812 config HMP_DYNAMIC_THRESHOLD
1813 bool "(EXPERIMENTAL) Dynamically adjust task migration threshold"
1814 depends on SCHED_HMP_ENHANCEMENT
1816 Dynamically adjust task migration threshold according to current system load
1818 config HMP_GLOBAL_BALANCE
1819 bool "(EXPERIMENTAL) Enhance HMP global load balance"
1820 depends on SCHED_HMP_ENHANCEMENT
1822 Enhance HMP global load balance
1824 config HMP_TASK_ASSIGNMENT
1825 bool "(EXPERIMENTAL) Enhance HMP task assignment"
1826 depends on SCHED_HMP_ENHANCEMENT
1828 Enhance HMP task assignment
1830 config HMP_DISCARD_CFS_SELECTION_RESULT
1831 bool "(EXPERIMENTAL) Discard CFS runqueue selection result"
1832 depends on SCHED_HMP_ENHANCEMENT && HMP_TASK_ASSIGNMENT
1834 Discard CFS runqueue selection result even if only one cluster exists
1836 config HMP_PACK_SMALL_TASK
1837 bool "(EXPERIMENTAL) Packing Small Tasks"
1838 depends on SCHED_HMP_ENHANCEMENT
1840 This option enables Packing Small Tasks
1842 config HMP_PACK_BUDDY_INFO
1843 bool "(EXPERIMENTAL) Packing Small Tasks Buddy Information Log"
1844 depends on SCHED_HMP_ENHANCEMENT && HMP_PACK_SMALL_TASK
1846 This option enables Packing Small Tasks Buddy Information Log
1848 config HMP_LAZY_BALANCE
1849 bool "(EXPERIMENTAL) Lazy Balance"
1850 depends on SCHED_HMP_ENHANCEMENT && HMP_PACK_SMALL_TASK
1852 This option enables Lazy Balance
1854 config HMP_POWER_AWARE_CONTROLLER
1855 bool "(EXPERIMENTAL) Power-aware Scheduler for b.L MP Controller"
1856 depends on SCHED_HMP_ENHANCEMENT && HMP_PACK_SMALL_TASK && HMP_LAZY_BALANCE
1858 Power-aware scheduler for b.L MP controller and status interface
1860 config HEVTASK_INTERFACE
1861 bool "task status interface"
1863 The option provide an interface to show task status
1865 config ARCH_SCALE_INVARIANT_CPU_CAPACITY
1866 bool "(EXPERIMENTAL) Scale-Invariant CPU Compute Capacity Recording"
1869 Provides a new measure of maximum and instantaneous CPU compute
1870 capacity, derived from a table of relative compute performance
1871 for each core type present in the system. The table is an
1872 estimate and specific core performance may be different for
1873 any particular workload. The measure includes the relative
1874 performance and a linear scale of current to maximum frequency
1875 such that at maximum frequency (as expressed in the DTB) the
1876 reported compute capacity will be equal to the estimated
1877 performance from the table. Values range between 0 and 1023 where
1878 1023 is the highest capacity available in the system.
1883 This option enables support for the ARM system coherency unit
1885 config HAVE_ARM_ARCH_TIMER
1886 bool "Architected timer support"
1888 select ARM_ARCH_TIMER
1890 This option enables support for the ARM architected timer
1895 select CLKSRC_OF if OF
1897 This options enables support for the ARM timer and watchdog unit
1900 bool "Multi-Cluster Power Management"
1901 depends on CPU_V7 && SMP
1903 This option provides the common power management infrastructure
1904 for (multi-)cluster based systems, such as big.LITTLE based
1908 prompt "Memory split"
1911 Select the desired split between kernel and user memory.
1913 If you are not absolutely sure what you are doing, leave this
1917 bool "3G/1G user/kernel split"
1919 bool "2G/2G user/kernel split"
1921 bool "1G/3G user/kernel split"
1926 default 0x40000000 if VMSPLIT_1G
1927 default 0x80000000 if VMSPLIT_2G
1931 int "Maximum number of CPUs (2-32)"
1937 bool "Support for hot-pluggable CPUs"
1938 depends on SMP && HOTPLUG
1940 Say Y here to experiment with turning CPUs off and on. CPUs
1941 can be controlled through /sys/devices/system/cpu.
1944 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1947 Say Y here if you want Linux to communicate with system firmware
1948 implementing the PSCI specification for CPU-centric power
1949 management operations described in ARM document number ARM DEN
1950 0022A ("Power State Coordination Interface System Software on
1954 bool "Use local timer interrupts"
1957 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT && !ARCH_MT6589 && !ARCH_MT6582 && !ARCH_MT8135 && !ARCH_MT6592 && !ARCH_MT6595 && !ARCH_MT6795 && !ARCH_MT6752 && !ARCH_MT8127 && !ARCH_MT6572)
1959 Enable support for local timers on SMP platforms, rather then the
1960 legacy IPI broadcast method. Local timers allows the system
1961 accounting to be spread across the timer interval, preventing a
1962 "thundering herd" at every timer tick.
1964 # The GPIO number here must be sorted by descending number. In case of
1965 # a multiplatform kernel, we just want the highest value required by the
1966 # selected platforms.
1969 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1970 default 512 if SOC_OMAP5
1971 default 392 if ARCH_U8500
1972 default 352 if ARCH_VT8500
1973 default 288 if ARCH_SUNXI
1974 default 264 if MACH_H4700
1977 Maximum number of GPIOs in the system.
1979 If unsure, leave the default value.
1981 source kernel/Kconfig.preempt
1985 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1986 ARCH_S5PV210 || ARCH_EXYNOS4
1987 default AT91_TIMER_HZ if ARCH_AT91
1988 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1992 def_bool HIGH_RES_TIMERS
1994 config THUMB2_KERNEL
1995 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1996 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1997 default y if CPU_THUMBONLY
1999 select ARM_ASM_UNIFIED
2002 By enabling this option, the kernel will be compiled in
2003 Thumb-2 mode. A compiler/assembler that understand the unified
2004 ARM-Thumb syntax is needed.
2008 config THUMB2_AVOID_R_ARM_THM_JUMP11
2009 bool "Work around buggy Thumb-2 short branch relocations in gas"
2010 depends on THUMB2_KERNEL && MODULES
2013 Various binutils versions can resolve Thumb-2 branches to
2014 locally-defined, preemptible global symbols as short-range "b.n"
2015 branch instructions.
2017 This is a problem, because there's no guarantee the final
2018 destination of the symbol, or any candidate locations for a
2019 trampoline, are within range of the branch. For this reason, the
2020 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
2021 relocation in modules at all, and it makes little sense to add
2024 The symptom is that the kernel fails with an "unsupported
2025 relocation" error when loading some modules.
2027 Until fixed tools are available, passing
2028 -fno-optimize-sibling-calls to gcc should prevent gcc generating
2029 code which hits this problem, at the cost of a bit of extra runtime
2030 stack usage in some cases.
2032 The problem is described in more detail at:
2033 https://bugs.launchpad.net/binutils-linaro/+bug/725126
2035 Only Thumb-2 kernels are affected.
2037 Unless you are sure your tools don't have this problem, say Y.
2039 config ARM_ASM_UNIFIED
2043 bool "Use the ARM EABI to compile the kernel"
2045 This option allows for the kernel to be compiled using the latest
2046 ARM ABI (aka EABI). This is only useful if you are using a user
2047 space environment that is also compiled with EABI.
2049 Since there are major incompatibilities between the legacy ABI and
2050 EABI, especially with regard to structure member alignment, this
2051 option also changes the kernel syscall calling convention to
2052 disambiguate both ABIs and allow for backward compatibility support
2053 (selected with CONFIG_OABI_COMPAT).
2055 To use this you need GCC version 4.0.0 or later.
2058 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
2059 depends on AEABI && !THUMB2_KERNEL
2062 This option preserves the old syscall interface along with the
2063 new (ARM EABI) one. It also provides a compatibility layer to
2064 intercept syscalls that have structure arguments which layout
2065 in memory differs between the legacy ABI and the new ARM EABI
2066 (only for non "thumb" binaries). This option adds a tiny
2067 overhead to all syscalls and produces a slightly larger kernel.
2068 If you know you'll be using only pure EABI user space then you
2069 can say N here. If this option is not selected and you attempt
2070 to execute a legacy ABI binary then the result will be
2071 UNPREDICTABLE (in fact it can be predicted that it won't work
2072 at all). If in doubt say Y.
2074 config ARCH_HAS_HOLES_MEMORYMODEL
2077 config ARCH_SPARSEMEM_ENABLE
2080 config ARCH_SPARSEMEM_DEFAULT
2081 def_bool ARCH_SPARSEMEM_ENABLE
2083 config ARCH_SELECT_MEMORY_MODEL
2084 def_bool ARCH_SPARSEMEM_ENABLE
2086 config HAVE_ARCH_PFN_VALID
2087 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
2090 bool "High Memory Support"
2093 The address space of ARM processors is only 4 Gigabytes large
2094 and it has to accommodate user address space, kernel address
2095 space as well as some memory mapped IO. That means that, if you
2096 have a large amount of physical memory and/or IO, not all of the
2097 memory can be "permanently mapped" by the kernel. The physical
2098 memory that is not permanently mapped is called "high memory".
2100 Depending on the selected kernel/user memory split, minimum
2101 vmalloc space and actual amount of RAM, you may not need this
2102 option which should result in a slightly faster kernel.
2107 bool "Allocate 2nd-level pagetables from highmem"
2110 config HW_PERF_EVENTS
2111 bool "Enable hardware performance counter support for perf events"
2112 depends on PERF_EVENTS
2115 Enable hardware performance counter support for perf events. If
2116 disabled, perf events will use software events only.
2120 config FORCE_MAX_ZONEORDER
2121 int "Maximum zone order" if ARCH_SHMOBILE
2122 range 11 64 if ARCH_SHMOBILE
2123 default "12" if SOC_AM33XX
2124 default "9" if SA1111
2127 The kernel memory allocator divides physically contiguous memory
2128 blocks into "zones", where each zone is a power of two number of
2129 pages. This option selects the largest power of two that the kernel
2130 keeps in the memory allocator. If you need to allocate very large
2131 blocks of physically contiguous memory, then you may need to
2132 increase this value.
2134 This config option is actually maximum order plus one. For example,
2135 a value of 11 means that the largest free memory block is 2^10 pages.
2137 config ALIGNMENT_TRAP
2139 depends on CPU_CP15_MMU
2140 default y if !ARCH_EBSA110
2141 select HAVE_PROC_CPU if PROC_FS
2143 ARM processors cannot fetch/store information which is not
2144 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
2145 address divisible by 4. On 32-bit ARM processors, these non-aligned
2146 fetch/store instructions will be emulated in software if you say
2147 here, which has a severe performance impact. This is necessary for
2148 correct operation of some network protocols. With an IP-only
2149 configuration it is safe to say N, otherwise say Y.
2151 config UACCESS_WITH_MEMCPY
2152 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
2154 default y if CPU_FEROCEON
2156 Implement faster copy_to_user and clear_user methods for CPU
2157 cores where a 8-word STM instruction give significantly higher
2158 memory write throughput than a sequence of individual 32bit stores.
2160 A possible side effect is a slight increase in scheduling latency
2161 between threads sharing the same address space if they invoke
2162 such copy operations with large buffers.
2164 However, if the CPU data cache is using a write-allocate mode,
2165 this option is unlikely to provide any performance gain.
2169 prompt "Enable seccomp to safely compute untrusted bytecode"
2171 This kernel feature is useful for number crunching applications
2172 that may need to compute untrusted bytecode during their
2173 execution. By using pipes or other transports made available to
2174 the process as file descriptors supporting the read/write
2175 syscalls, it's possible to isolate those applications in
2176 their own address space using seccomp. Once seccomp is
2177 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
2178 and the task is only allowed to execute a few safe syscalls
2179 defined by each seccomp mode.
2181 config CC_STACKPROTECTOR
2182 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
2184 This option turns on the -fstack-protector GCC feature. This
2185 feature puts, at the beginning of functions, a canary value on
2186 the stack just before the return address, and validates
2187 the value just before actually returning. Stack based buffer
2188 overflows (that need to overwrite this return address) now also
2189 overwrite the canary, which gets detected and the attack is then
2190 neutralized via a kernel panic.
2191 This feature requires gcc version 4.2 or above.
2198 bool "Xen guest support on ARM (EXPERIMENTAL)"
2199 depends on ARM && AEABI && OF
2200 depends on CPU_V7 && !CPU_V6
2201 depends on !GENERIC_ATOMIC64
2204 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
2206 config ARM_FLUSH_CONSOLE_ON_RESTART
2207 bool "Force flush the console on restart"
2209 If the console is locked while the system is rebooted, the messages
2210 in the temporary logbuffer would not have propogated to all the
2211 console drivers. This option forces the console lock to be
2212 released if it failed to be acquired, which will cause all the
2213 pending messages to be flushed.
2220 bool "Flattened Device Tree support"
2223 select OF_EARLY_FLATTREE
2224 select OF_RESERVED_MEM
2226 Include support for flattened device tree machine descriptions.
2229 bool "Support for the traditional ATAGS boot data passing" if USE_OF
2232 This is the traditional way of passing data to the kernel at boot
2233 time. If you are solely relying on the flattened device tree (or
2234 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
2235 to remove ATAGS support from your kernel binary. If unsure,
2238 config DEPRECATED_PARAM_STRUCT
2239 bool "Provide old way to pass kernel parameters"
2242 This was deprecated in 2001 and announced to live on for 5 years.
2243 Some old boot loaders still use this way.
2245 config BUILD_ARM_APPENDED_DTB_IMAGE
2246 bool "Build a concatenated zImage/dtb by default"
2249 Enabling this option will cause a concatenated zImage and list of
2250 DTBs to be built by default (instead of a standalone zImage.)
2251 The image will built in arch/arm/boot/zImage-dtb
2253 config BUILD_ARM_APPENDED_DTB_IMAGE_NAMES
2254 string "Default dtb names"
2255 depends on BUILD_ARM_APPENDED_DTB_IMAGE
2257 Space separated list of names of dtbs to append when
2258 building a concatenated zImage-dtb.
2260 # Compressed boot loader in ROM. Yes, we really want to ask about
2261 # TEXT and BSS so we preserve their values in the config files.
2262 config ZBOOT_ROM_TEXT
2263 hex "Compressed ROM boot loader base address"
2266 The physical address at which the ROM-able zImage is to be
2267 placed in the target. Platforms which normally make use of
2268 ROM-able zImage formats normally set this to a suitable
2269 value in their defconfig file.
2271 If ZBOOT_ROM is not enabled, this has no effect.
2273 config ZBOOT_ROM_BSS
2274 hex "Compressed ROM boot loader BSS address"
2277 The base address of an area of read/write memory in the target
2278 for the ROM-able zImage which must be available while the
2279 decompressor is running. It must be large enough to hold the
2280 entire decompressed kernel plus an additional 128 KiB.
2281 Platforms which normally make use of ROM-able zImage formats
2282 normally set this to a suitable value in their defconfig file.
2284 If ZBOOT_ROM is not enabled, this has no effect.
2287 bool "Compressed boot loader in ROM/flash"
2288 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
2290 Say Y here if you intend to execute your compressed kernel image
2291 (zImage) directly from ROM or flash. If unsure, say N.
2293 config COMPAT_CPUINFO
2294 bool "Show /proc/cpuinfo in old form"
2297 Show old style /proc/cpuinfo. Do not show cpu features with each
2302 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
2303 depends on ZBOOT_ROM && ARCH_SH7372
2304 default ZBOOT_ROM_NONE
2306 Include experimental SD/MMC loading code in the ROM-able zImage.
2307 With this enabled it is possible to write the ROM-able zImage
2308 kernel image to an MMC or SD card and boot the kernel straight
2309 from the reset vector. At reset the processor Mask ROM will load
2310 the first part of the ROM-able zImage which in turn loads the
2311 rest the kernel image to RAM.
2313 config ZBOOT_ROM_NONE
2314 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2316 Do not load image from SD or MMC
2318 config ZBOOT_ROM_MMCIF
2319 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2321 Load image from MMCIF hardware block.
2323 config ZBOOT_ROM_SH_MOBILE_SDHI
2324 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2326 Load image from SDHI hardware block
2330 config ARM_APPENDED_DTB
2331 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2332 depends on OF && !ZBOOT_ROM
2334 With this option, the boot code will look for a device tree binary
2335 (DTB) appended to zImage
2336 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2338 This is meant as a backward compatibility convenience for those
2339 systems with a bootloader that can't be upgraded to accommodate
2340 the documented boot protocol using a device tree.
2342 Beware that there is very little in terms of protection against
2343 this option being confused by leftover garbage in memory that might
2344 look like a DTB header after a reboot if no actual DTB is appended
2345 to zImage. Do not leave this option active in a production kernel
2346 if you don't intend to always append a DTB. Proper passing of the
2347 location into r2 of a bootloader provided DTB is always preferable
2350 config ARM_ATAG_DTB_COMPAT
2351 bool "Supplement the appended DTB with traditional ATAG information"
2352 depends on ARM_APPENDED_DTB
2354 Some old bootloaders can't be updated to a DTB capable one, yet
2355 they provide ATAGs with memory configuration, the ramdisk address,
2356 the kernel cmdline string, etc. Such information is dynamically
2357 provided by the bootloader and can't always be stored in a static
2358 DTB. To allow a device tree enabled kernel to be used with such
2359 bootloaders, this option allows zImage to extract the information
2360 from the ATAG list and store it at run time into the appended DTB.
2363 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2364 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2366 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2367 bool "Use bootloader kernel arguments if available"
2369 Uses the command-line options passed by the boot loader instead of
2370 the device tree bootargs property. If the boot loader doesn't provide
2371 any, the device tree bootargs property will be used.
2373 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2374 bool "Extend with bootloader kernel arguments"
2376 The command-line arguments provided by the boot loader will be
2377 appended to the the device tree bootargs property.
2382 string "Default kernel command string"
2385 On some architectures (EBSA110 and CATS), there is currently no way
2386 for the boot loader to pass arguments to the kernel. For these
2387 architectures, you should supply some command-line options at build
2388 time by entering them here. As a minimum, you should specify the
2389 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2392 prompt "Kernel command line type" if CMDLINE != ""
2393 default CMDLINE_FROM_BOOTLOADER
2396 config CMDLINE_FROM_BOOTLOADER
2397 bool "Use bootloader kernel arguments if available"
2399 Uses the command-line options passed by the boot loader. If
2400 the boot loader doesn't provide any, the default kernel command
2401 string provided in CMDLINE will be used.
2403 config CMDLINE_EXTEND
2404 bool "Extend bootloader kernel arguments"
2406 The command-line arguments provided by the boot loader will be
2407 appended to the default kernel command string.
2409 config CMDLINE_FORCE
2410 bool "Always use the default kernel command string"
2412 Always use the default kernel command string, even if the boot
2413 loader passes other arguments to the kernel.
2414 This is useful if you cannot or don't want to change the
2415 command-line options your boot loader passes to the kernel.
2419 bool "Kernel Execute-In-Place from ROM"
2420 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2422 Execute-In-Place allows the kernel to run from non-volatile storage
2423 directly addressable by the CPU, such as NOR flash. This saves RAM
2424 space since the text section of the kernel is not loaded from flash
2425 to RAM. Read-write sections, such as the data section and stack,
2426 are still copied to RAM. The XIP kernel is not compressed since
2427 it has to run directly from flash, so it will take more space to
2428 store it. The flash address used to link the kernel object files,
2429 and for storing it, is configuration dependent. Therefore, if you
2430 say Y here, you must know the proper physical address where to
2431 store the kernel image depending on your own flash memory usage.
2433 Also note that the make target becomes "make xipImage" rather than
2434 "make zImage" or "make Image". The final kernel binary to put in
2435 ROM memory will be arch/arm/boot/xipImage.
2439 config XIP_PHYS_ADDR
2440 hex "XIP Kernel Physical Location"
2441 depends on XIP_KERNEL
2442 default "0x00080000"
2444 This is the physical address in your flash memory the kernel will
2445 be linked for and stored to. This address is dependent on your
2449 bool "Kexec system call (EXPERIMENTAL)"
2450 depends on (!SMP || PM_SLEEP_SMP)
2452 kexec is a system call that implements the ability to shutdown your
2453 current kernel, and to start another kernel. It is like a reboot
2454 but it is independent of the system firmware. And like a reboot
2455 you can start any kernel with it, not just Linux.
2457 It is an ongoing process to be certain the hardware in a machine
2458 is properly shutdown, so do not be surprised if this code does not
2459 initially work for you. It may help to enable device hotplugging
2463 bool "Export atags in procfs"
2464 depends on ATAGS && KEXEC
2467 Should the atags used to boot the kernel be exported in an "atags"
2468 file in procfs. Useful with kexec.
2471 bool "Build kdump crash kernel (EXPERIMENTAL)"
2473 Generate crash dump after being started by kexec. This should
2474 be normally only set in special crash dump kernels which are
2475 loaded in the main kernel with kexec-tools into a specially
2476 reserved region and then later executed after a crash by
2477 kdump/kexec. The crash dump kernel must be compiled to a
2478 memory address not used by the main kernel
2480 For more details see Documentation/kdump/kdump.txt
2482 config RESTART_DISABLE_CACHE
2483 bool "Disable cache in arm_machine_restart"
2486 Whther to disable DCache in arm_machine_restart().
2487 This is a temporary solution before MTK change to use new kernel
2490 config AUTO_ZRELADDR
2491 bool "Auto calculation of the decompressed kernel image address"
2492 depends on !ZBOOT_ROM && !ARCH_U300
2494 ZRELADDR is the physical address where the decompressed kernel
2495 image will be placed. If AUTO_ZRELADDR is selected, the address
2496 will be determined at run-time by masking the current IP with
2497 0xf8000000. This assumes the zImage being placed in the first 128MB
2498 from start of memory.
2502 menu "CPU Power Management"
2505 source "drivers/cpufreq/Kconfig"
2510 Internal configuration node for common cpufreq on Samsung SoC
2512 config CPU_FREQ_S3C24XX
2513 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2514 depends on ARCH_S3C24XX && CPU_FREQ
2517 This enables the CPUfreq driver for the Samsung S3C24XX family
2520 For details, take a look at <file:Documentation/cpu-freq>.
2524 config CPU_FREQ_S3C24XX_PLL
2525 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2526 depends on CPU_FREQ_S3C24XX
2528 Compile in support for changing the PLL frequency from the
2529 S3C24XX series CPUfreq driver. The PLL takes time to settle
2530 after a frequency change, so by default it is not enabled.
2532 This also means that the PLL tables for the selected CPU(s) will
2533 be built which may increase the size of the kernel image.
2535 config CPU_FREQ_S3C24XX_DEBUG
2536 bool "Debug CPUfreq Samsung driver core"
2537 depends on CPU_FREQ_S3C24XX
2539 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2541 config CPU_FREQ_S3C24XX_IODEBUG
2542 bool "Debug CPUfreq Samsung driver IO timing"
2543 depends on CPU_FREQ_S3C24XX
2545 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2547 config CPU_FREQ_S3C24XX_DEBUGFS
2548 bool "Export debugfs for CPUFreq"
2549 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2551 Export status information via debugfs.
2555 source "drivers/cpuidle/Kconfig"
2559 menu "Floating point emulation"
2561 comment "At least one emulation must be selected"
2564 bool "NWFPE math emulation"
2565 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2567 Say Y to include the NWFPE floating point emulator in the kernel.
2568 This is necessary to run most binaries. Linux does not currently
2569 support floating point hardware so you need to say Y here even if
2570 your machine has an FPA or floating point co-processor podule.
2572 You may say N here if you are going to load the Acorn FPEmulator
2573 early in the bootup.
2576 bool "Support extended precision"
2577 depends on FPE_NWFPE
2579 Say Y to include 80-bit support in the kernel floating-point
2580 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2581 Note that gcc does not generate 80-bit operations by default,
2582 so in most cases this option only enlarges the size of the
2583 floating point emulator without any good reason.
2585 You almost surely want to say N here.
2588 bool "FastFPE math emulation (EXPERIMENTAL)"
2589 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2591 Say Y here to include the FAST floating point emulator in the kernel.
2592 This is an experimental much faster emulator which now also has full
2593 precision for the mantissa. It does not support any exceptions.
2594 It is very simple, and approximately 3-6 times faster than NWFPE.
2596 It should be sufficient for most programs. It may be not suitable
2597 for scientific calculations, but you have to check this for yourself.
2598 If you do not feel you need a faster FP emulation you should better
2602 bool "VFP-format floating point maths"
2603 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2605 Say Y to include VFP support code in the kernel. This is needed
2606 if your hardware includes a VFP unit.
2608 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2609 release notes and additional status information.
2611 Say N if your target does not have VFP hardware.
2617 Say Y if you want to enable VFP/NEON always
2625 bool "Advanced SIMD (NEON) Extension support"
2626 depends on VFPv3 && CPU_V7
2628 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2633 menu "Userspace binary formats"
2635 source "fs/Kconfig.binfmt"
2638 tristate "RISC OS personality"
2641 Say Y here to include the kernel code necessary if you want to run
2642 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2643 experimental; if this sounds frightening, say N and sleep in peace.
2644 You can also say M here to compile this support as a module (which
2645 will be called arthur).
2649 menu "Power management options"
2651 source "kernel/power/Kconfig"
2653 config ARCH_SUSPEND_POSSIBLE
2654 depends on !ARCH_S5PC100
2655 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2656 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2659 config ARM_CPU_SUSPEND
2662 config ARCH_HIBERNATION_POSSIBLE
2665 default y if ARCH_SUSPEND_POSSIBLE
2669 source "net/Kconfig"
2671 source "drivers/Kconfig"
2675 source "arch/arm/Kconfig.debug"
2677 source "security/Kconfig"
2679 source "crypto/Kconfig"
2681 source "lib/Kconfig"
2683 source "arch/arm/kvm/Kconfig"