Documentation/devicetree/bindings/arm/pmu.txt

   1 * ARM Performance Monitor Units
   2
   3 ARM cores often have a PMU for counting cpu and cache events like cache misses
   4 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
   5 representation in the device tree should be done as under:-
   6
   7 Required properties:
   8
   9 - compatible : should be one of
  10         "arm,cortex-a15-pmu"
  11         "arm,cortex-a9-pmu"
  12         "arm,cortex-a8-pmu"
  13         "arm,cortex-a7-pmu"
  14         "arm,cortex-a5-pmu"
  15         "arm,arm11mpcore-pmu"
  16         "arm,arm1176-pmu"
  17         "arm,arm1136-pmu"
  18 - interrupts : 1 combined interrupt or 1 per core.
  19 - cluster : a phandle to the cluster to which it belongs
  20         If there are more than one cluster with same CPU type
  21         then there should be separate PMU nodes per cluster.
  22
  23 Example:
  24
  25 pmu {
  26         compatible = "arm,cortex-a9-pmu";
  27         interrupts = <100 101>;
  28 };