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Merge tag 'v3.10.107' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / ast / ast_post.c
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <drm/drmP.h>
30#include "ast_drv.h"
31
32#include "ast_dram_tables.h"
33
34static void ast_init_dram_2300(struct drm_device *dev);
35
36static void
37ast_enable_vga(struct drm_device *dev)
38{
39 struct ast_private *ast = dev->dev_private;
40
41 ast_io_write8(ast, 0x43, 0x01);
42 ast_io_write8(ast, 0x42, 0x01);
43}
44
45#if 0 /* will use later */
46static bool
47ast_is_vga_enabled(struct drm_device *dev)
48{
49 struct ast_private *ast = dev->dev_private;
50 u8 ch;
51
52 if (ast->chip == AST1180) {
53 /* TODO 1180 */
54 } else {
55 ch = ast_io_read8(ast, 0x43);
56 return !!(ch & 0x01);
57 }
58 return false;
59}
60#endif
61
62static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
63static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
64static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
65
66static void
67ast_set_def_ext_reg(struct drm_device *dev)
68{
69 struct ast_private *ast = dev->dev_private;
70 u8 i, index, reg;
71 const u8 *ext_reg_info;
72
73 /* reset scratch */
74 for (i = 0x81; i <= 0x8f; i++)
75 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
76
77 if (ast->chip == AST2300) {
78 if (dev->pdev->revision >= 0x20)
79 ext_reg_info = extreginfo_ast2300;
80 else
81 ext_reg_info = extreginfo_ast2300a0;
82 } else
83 ext_reg_info = extreginfo;
84
85 index = 0xa0;
86 while (*ext_reg_info != 0xff) {
87 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
88 index++;
89 ext_reg_info++;
90 }
91
92 /* disable standard IO/MEM decode if secondary */
93 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
94
95 /* Set Ext. Default */
96 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
97 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
98
99 /* Enable RAMDAC for A1 */
100 reg = 0x04;
101 if (ast->chip == AST2300)
102 reg |= 0x20;
103 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
104}
105
106static inline u32 mindwm(struct ast_private *ast, u32 r)
107{
108 ast_write32(ast, 0xf004, r & 0xffff0000);
109 ast_write32(ast, 0xf000, 0x1);
110
111 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
112}
113
114static inline void moutdwm(struct ast_private *ast, u32 r, u32 v)
115{
116 ast_write32(ast, 0xf004, r & 0xffff0000);
117 ast_write32(ast, 0xf000, 0x1);
118 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
119}
120
121/*
122 * AST2100/2150 DLL CBR Setting
123 */
124#define CBR_SIZE_AST2150 ((16 << 10) - 1)
125#define CBR_PASSNUM_AST2150 5
126#define CBR_THRESHOLD_AST2150 10
127#define CBR_THRESHOLD2_AST2150 10
128#define TIMEOUT_AST2150 5000000
129
130#define CBR_PATNUM_AST2150 8
131
132static const u32 pattern_AST2150[14] = {
133 0xFF00FF00,
134 0xCC33CC33,
135 0xAA55AA55,
136 0xFFFE0001,
137 0x683501FE,
138 0x0F1929B0,
139 0x2D0B4346,
140 0x60767F02,
141 0x6FBE36A6,
142 0x3A253035,
143 0x3019686D,
144 0x41C6167E,
145 0x620152BF,
146 0x20F050E0
147};
148
149static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
150{
151 u32 data, timeout;
152
153 moutdwm(ast, 0x1e6e0070, 0x00000000);
154 moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
155 timeout = 0;
156 do {
157 data = mindwm(ast, 0x1e6e0070) & 0x40;
158 if (++timeout > TIMEOUT_AST2150) {
159 moutdwm(ast, 0x1e6e0070, 0x00000000);
160 return 0xffffffff;
161 }
162 } while (!data);
163 moutdwm(ast, 0x1e6e0070, 0x00000000);
164 moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
165 timeout = 0;
166 do {
167 data = mindwm(ast, 0x1e6e0070) & 0x40;
168 if (++timeout > TIMEOUT_AST2150) {
169 moutdwm(ast, 0x1e6e0070, 0x00000000);
170 return 0xffffffff;
171 }
172 } while (!data);
173 data = (mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
174 moutdwm(ast, 0x1e6e0070, 0x00000000);
175 return data;
176}
177
178#if 0 /* unused in DDX driver - here for completeness */
179static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
180{
181 u32 data, timeout;
182
183 moutdwm(ast, 0x1e6e0070, 0x00000000);
184 moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
185 timeout = 0;
186 do {
187 data = mindwm(ast, 0x1e6e0070) & 0x40;
188 if (++timeout > TIMEOUT_AST2150) {
189 moutdwm(ast, 0x1e6e0070, 0x00000000);
190 return 0xffffffff;
191 }
192 } while (!data);
193 data = (mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
194 moutdwm(ast, 0x1e6e0070, 0x00000000);
195 return data;
196}
197#endif
198
199static int cbrtest_ast2150(struct ast_private *ast)
200{
201 int i;
202
203 for (i = 0; i < 8; i++)
204 if (mmctestburst2_ast2150(ast, i))
205 return 0;
206 return 1;
207}
208
209static int cbrscan_ast2150(struct ast_private *ast, int busw)
210{
211 u32 patcnt, loop;
212
213 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
214 moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
215 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
216 if (cbrtest_ast2150(ast))
217 break;
218 }
219 if (loop == CBR_PASSNUM_AST2150)
220 return 0;
221 }
222 return 1;
223}
224
225
226static void cbrdlli_ast2150(struct ast_private *ast, int busw)
227{
228 u32 dll_min[4], dll_max[4], dlli, data, passcnt;
229
230cbr_start:
231 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
232 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
233 passcnt = 0;
234
235 for (dlli = 0; dlli < 100; dlli++) {
236 moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
237 data = cbrscan_ast2150(ast, busw);
238 if (data != 0) {
239 if (data & 0x1) {
240 if (dll_min[0] > dlli)
241 dll_min[0] = dlli;
242 if (dll_max[0] < dlli)
243 dll_max[0] = dlli;
244 }
245 passcnt++;
246 } else if (passcnt >= CBR_THRESHOLD_AST2150)
247 goto cbr_start;
248 }
249 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
250 goto cbr_start;
251
252 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
253 moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
254}
255
256
257
258static void ast_init_dram_reg(struct drm_device *dev)
259{
260 struct ast_private *ast = dev->dev_private;
261 u8 j;
262 u32 data, temp, i;
263 const struct ast_dramstruct *dram_reg_info;
264
265 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
266
267 if ((j & 0x80) == 0) { /* VGA only */
268 if (ast->chip == AST2000) {
269 dram_reg_info = ast2000_dram_table_data;
270 ast_write32(ast, 0xf004, 0x1e6e0000);
271 ast_write32(ast, 0xf000, 0x1);
272 ast_write32(ast, 0x10100, 0xa8);
273
274 do {
275 ;
276 } while (ast_read32(ast, 0x10100) != 0xa8);
277 } else {/* AST2100/1100 */
278 if (ast->chip == AST2100 || ast->chip == 2200)
279 dram_reg_info = ast2100_dram_table_data;
280 else
281 dram_reg_info = ast1100_dram_table_data;
282
283 ast_write32(ast, 0xf004, 0x1e6e0000);
284 ast_write32(ast, 0xf000, 0x1);
285 ast_write32(ast, 0x12000, 0x1688A8A8);
286 do {
287 ;
288 } while (ast_read32(ast, 0x12000) != 0x01);
289
290 ast_write32(ast, 0x10000, 0xfc600309);
291 do {
292 ;
293 } while (ast_read32(ast, 0x10000) != 0x01);
294 }
295
296 while (dram_reg_info->index != 0xffff) {
297 if (dram_reg_info->index == 0xff00) {/* delay fn */
298 for (i = 0; i < 15; i++)
299 udelay(dram_reg_info->data);
300 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) {
301 data = dram_reg_info->data;
302 if (ast->dram_type == AST_DRAM_1Gx16)
303 data = 0x00000d89;
304 else if (ast->dram_type == AST_DRAM_1Gx32)
305 data = 0x00000c8d;
306
307 temp = ast_read32(ast, 0x12070);
308 temp &= 0xc;
309 temp <<= 2;
310 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
311 } else
312 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
313 dram_reg_info++;
314 }
315
316 /* AST 2100/2150 DRAM calibration */
317 data = ast_read32(ast, 0x10120);
318 if (data == 0x5061) { /* 266Mhz */
319 data = ast_read32(ast, 0x10004);
320 if (data & 0x40)
321 cbrdlli_ast2150(ast, 16); /* 16 bits */
322 else
323 cbrdlli_ast2150(ast, 32); /* 32 bits */
324 }
325
326 switch (ast->chip) {
327 case AST2000:
328 temp = ast_read32(ast, 0x10140);
329 ast_write32(ast, 0x10140, temp | 0x40);
330 break;
331 case AST1100:
332 case AST2100:
333 case AST2200:
334 case AST2150:
335 temp = ast_read32(ast, 0x1200c);
336 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
337 temp = ast_read32(ast, 0x12040);
338 ast_write32(ast, 0x12040, temp | 0x40);
339 break;
340 default:
341 break;
342 }
343 }
344
345 /* wait ready */
346 do {
347 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
348 } while ((j & 0x40) == 0);
349}
350
351void ast_post_gpu(struct drm_device *dev)
352{
353 u32 reg;
354 struct ast_private *ast = dev->dev_private;
355
356 pci_read_config_dword(ast->dev->pdev, 0x04, &reg);
357 reg |= 0x3;
358 pci_write_config_dword(ast->dev->pdev, 0x04, reg);
359
360 ast_enable_vga(dev);
361 ast_open_key(ast);
362 ast_set_def_ext_reg(dev);
363
364 if (ast->chip == AST2300)
365 ast_init_dram_2300(dev);
366 else
367 ast_init_dram_reg(dev);
368}
369
370/* AST 2300 DRAM settings */
371#define AST_DDR3 0
372#define AST_DDR2 1
373
374struct ast2300_dram_param {
375 u32 dram_type;
376 u32 dram_chipid;
377 u32 dram_freq;
378 u32 vram_size;
379 u32 odt;
380 u32 wodt;
381 u32 rodt;
382 u32 dram_config;
383 u32 reg_PERIOD;
384 u32 reg_MADJ;
385 u32 reg_SADJ;
386 u32 reg_MRS;
387 u32 reg_EMRS;
388 u32 reg_AC1;
389 u32 reg_AC2;
390 u32 reg_DQSIC;
391 u32 reg_DRV;
392 u32 reg_IOZ;
393 u32 reg_DQIDLY;
394 u32 reg_FREQ;
395 u32 madj_max;
396 u32 dll2_finetune_step;
397};
398
399/*
400 * DQSI DLL CBR Setting
401 */
402#define CBR_SIZE1 ((4 << 10) - 1)
403#define CBR_SIZE2 ((64 << 10) - 1)
404#define CBR_PASSNUM 5
405#define CBR_PASSNUM2 5
406#define CBR_THRESHOLD 10
407#define CBR_THRESHOLD2 10
408#define TIMEOUT 5000000
409#define CBR_PATNUM 8
410
411static const u32 pattern[8] = {
412 0xFF00FF00,
413 0xCC33CC33,
414 0xAA55AA55,
415 0x88778877,
416 0x92CC4D6E,
417 0x543D3CDE,
418 0xF1E843C7,
419 0x7C61D253
420};
421
422#if 0 /* unused in DDX, included for completeness */
423static int mmc_test_burst(struct ast_private *ast, u32 datagen)
424{
425 u32 data, timeout;
426
427 moutdwm(ast, 0x1e6e0070, 0x00000000);
428 moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
429 timeout = 0;
430 do {
431 data = mindwm(ast, 0x1e6e0070) & 0x3000;
432 if (data & 0x2000) {
433 return 0;
434 }
435 if (++timeout > TIMEOUT) {
436 moutdwm(ast, 0x1e6e0070, 0x00000000);
437 return 0;
438 }
439 } while (!data);
440 moutdwm(ast, 0x1e6e0070, 0x00000000);
441 return 1;
442}
443#endif
444
445static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
446{
447 u32 data, timeout;
448
449 moutdwm(ast, 0x1e6e0070, 0x00000000);
450 moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
451 timeout = 0;
452 do {
453 data = mindwm(ast, 0x1e6e0070) & 0x1000;
454 if (++timeout > TIMEOUT) {
455 moutdwm(ast, 0x1e6e0070, 0x0);
456 return -1;
457 }
458 } while (!data);
459 data = mindwm(ast, 0x1e6e0078);
460 data = (data | (data >> 16)) & 0xffff;
461 moutdwm(ast, 0x1e6e0070, 0x0);
462 return data;
463}
464
465#if 0 /* Unused in DDX here for completeness */
466static int mmc_test_single(struct ast_private *ast, u32 datagen)
467{
468 u32 data, timeout;
469
470 moutdwm(ast, 0x1e6e0070, 0x00000000);
471 moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
472 timeout = 0;
473 do {
474 data = mindwm(ast, 0x1e6e0070) & 0x3000;
475 if (data & 0x2000)
476 return 0;
477 if (++timeout > TIMEOUT) {
478 moutdwm(ast, 0x1e6e0070, 0x0);
479 return 0;
480 }
481 } while (!data);
482 moutdwm(ast, 0x1e6e0070, 0x0);
483 return 1;
484}
485#endif
486
487static int mmc_test_single2(struct ast_private *ast, u32 datagen)
488{
489 u32 data, timeout;
490
491 moutdwm(ast, 0x1e6e0070, 0x00000000);
492 moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
493 timeout = 0;
494 do {
495 data = mindwm(ast, 0x1e6e0070) & 0x1000;
496 if (++timeout > TIMEOUT) {
497 moutdwm(ast, 0x1e6e0070, 0x0);
498 return -1;
499 }
500 } while (!data);
501 data = mindwm(ast, 0x1e6e0078);
502 data = (data | (data >> 16)) & 0xffff;
503 moutdwm(ast, 0x1e6e0070, 0x0);
504 return data;
505}
506
507static int cbr_test(struct ast_private *ast)
508{
509 u32 data;
510 int i;
511 data = mmc_test_single2(ast, 0);
512 if ((data & 0xff) && (data & 0xff00))
513 return 0;
514 for (i = 0; i < 8; i++) {
515 data = mmc_test_burst2(ast, i);
516 if ((data & 0xff) && (data & 0xff00))
517 return 0;
518 }
519 if (!data)
520 return 3;
521 else if (data & 0xff)
522 return 2;
523 return 1;
524}
525
526static int cbr_scan(struct ast_private *ast)
527{
528 u32 data, data2, patcnt, loop;
529
530 data2 = 3;
531 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
532 moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
533 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
534 if ((data = cbr_test(ast)) != 0) {
535 data2 &= data;
536 if (!data2)
537 return 0;
538 break;
539 }
540 }
541 if (loop == CBR_PASSNUM2)
542 return 0;
543 }
544 return data2;
545}
546
547static u32 cbr_test2(struct ast_private *ast)
548{
549 u32 data;
550
551 data = mmc_test_burst2(ast, 0);
552 if (data == 0xffff)
553 return 0;
554 data |= mmc_test_single2(ast, 0);
555 if (data == 0xffff)
556 return 0;
557
558 return ~data & 0xffff;
559}
560
561static u32 cbr_scan2(struct ast_private *ast)
562{
563 u32 data, data2, patcnt, loop;
564
565 data2 = 0xffff;
566 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
567 moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
568 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
569 if ((data = cbr_test2(ast)) != 0) {
570 data2 &= data;
571 if (!data)
572 return 0;
573 break;
574 }
575 }
576 if (loop == CBR_PASSNUM2)
577 return 0;
578 }
579 return data2;
580}
581
582#if 0 /* unused in DDX - added for completeness */
583static void finetuneDQI(struct ast_private *ast, struct ast2300_dram_param *param)
584{
585 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt;
586
587 gold_sadj[0] = (mindwm(ast, 0x1E6E0024) >> 16) & 0xffff;
588 gold_sadj[1] = gold_sadj[0] >> 8;
589 gold_sadj[0] = gold_sadj[0] & 0xff;
590 gold_sadj[0] = (gold_sadj[0] + gold_sadj[1]) >> 1;
591 gold_sadj[1] = gold_sadj[0];
592
593 for (cnt = 0; cnt < 16; cnt++) {
594 dllmin[cnt] = 0xff;
595 dllmax[cnt] = 0x0;
596 }
597 passcnt = 0;
598 for (dlli = 0; dlli < 76; dlli++) {
599 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
600 /* Wait DQSI latch phase calibration */
601 moutdwm(ast, 0x1E6E0074, 0x00000010);
602 moutdwm(ast, 0x1E6E0070, 0x00000003);
603 do {
604 data = mindwm(ast, 0x1E6E0070);
605 } while (!(data & 0x00001000));
606 moutdwm(ast, 0x1E6E0070, 0x00000000);
607
608 moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
609 data = cbr_scan2(ast);
610 if (data != 0) {
611 mask = 0x00010001;
612 for (cnt = 0; cnt < 16; cnt++) {
613 if (data & mask) {
614 if (dllmin[cnt] > dlli) {
615 dllmin[cnt] = dlli;
616 }
617 if (dllmax[cnt] < dlli) {
618 dllmax[cnt] = dlli;
619 }
620 }
621 mask <<= 1;
622 }
623 passcnt++;
624 } else if (passcnt >= CBR_THRESHOLD) {
625 break;
626 }
627 }
628 data = 0;
629 for (cnt = 0; cnt < 8; cnt++) {
630 data >>= 3;
631 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)) {
632 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
633 if (gold_sadj[0] >= dlli) {
634 dlli = (gold_sadj[0] - dlli) >> 1;
635 if (dlli > 3) {
636 dlli = 3;
637 }
638 } else {
639 dlli = (dlli - gold_sadj[0]) >> 1;
640 if (dlli > 4) {
641 dlli = 4;
642 }
643 dlli = (8 - dlli) & 0x7;
644 }
645 data |= dlli << 21;
646 }
647 }
648 moutdwm(ast, 0x1E6E0080, data);
649
650 data = 0;
651 for (cnt = 8; cnt < 16; cnt++) {
652 data >>= 3;
653 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)) {
654 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
655 if (gold_sadj[1] >= dlli) {
656 dlli = (gold_sadj[1] - dlli) >> 1;
657 if (dlli > 3) {
658 dlli = 3;
659 } else {
660 dlli = (dlli - 1) & 0x7;
661 }
662 } else {
663 dlli = (dlli - gold_sadj[1]) >> 1;
664 dlli += 1;
665 if (dlli > 4) {
666 dlli = 4;
667 }
668 dlli = (8 - dlli) & 0x7;
669 }
670 data |= dlli << 21;
671 }
672 }
673 moutdwm(ast, 0x1E6E0084, data);
674
675} /* finetuneDQI */
676#endif
677
678static void finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
679{
680 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt;
681
682FINETUNE_START:
683 for (cnt = 0; cnt < 16; cnt++) {
684 dllmin[cnt] = 0xff;
685 dllmax[cnt] = 0x0;
686 }
687 passcnt = 0;
688 for (dlli = 0; dlli < 76; dlli++) {
689 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
690 /* Wait DQSI latch phase calibration */
691 moutdwm(ast, 0x1E6E0074, 0x00000010);
692 moutdwm(ast, 0x1E6E0070, 0x00000003);
693 do {
694 data = mindwm(ast, 0x1E6E0070);
695 } while (!(data & 0x00001000));
696 moutdwm(ast, 0x1E6E0070, 0x00000000);
697
698 moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
699 data = cbr_scan2(ast);
700 if (data != 0) {
701 mask = 0x00010001;
702 for (cnt = 0; cnt < 16; cnt++) {
703 if (data & mask) {
704 if (dllmin[cnt] > dlli) {
705 dllmin[cnt] = dlli;
706 }
707 if (dllmax[cnt] < dlli) {
708 dllmax[cnt] = dlli;
709 }
710 }
711 mask <<= 1;
712 }
713 passcnt++;
714 } else if (passcnt >= CBR_THRESHOLD2) {
715 break;
716 }
717 }
718 gold_sadj[0] = 0x0;
719 passcnt = 0;
720 for (cnt = 0; cnt < 16; cnt++) {
721 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
722 gold_sadj[0] += dllmin[cnt];
723 passcnt++;
724 }
725 }
726 if (passcnt != 16) {
727 goto FINETUNE_START;
728 }
729 gold_sadj[0] = gold_sadj[0] >> 4;
730 gold_sadj[1] = gold_sadj[0];
731
732 data = 0;
733 for (cnt = 0; cnt < 8; cnt++) {
734 data >>= 3;
735 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
736 dlli = dllmin[cnt];
737 if (gold_sadj[0] >= dlli) {
738 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
739 if (dlli > 3) {
740 dlli = 3;
741 }
742 } else {
743 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
744 if (dlli > 4) {
745 dlli = 4;
746 }
747 dlli = (8 - dlli) & 0x7;
748 }
749 data |= dlli << 21;
750 }
751 }
752 moutdwm(ast, 0x1E6E0080, data);
753
754 data = 0;
755 for (cnt = 8; cnt < 16; cnt++) {
756 data >>= 3;
757 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
758 dlli = dllmin[cnt];
759 if (gold_sadj[1] >= dlli) {
760 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
761 if (dlli > 3) {
762 dlli = 3;
763 } else {
764 dlli = (dlli - 1) & 0x7;
765 }
766 } else {
767 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
768 dlli += 1;
769 if (dlli > 4) {
770 dlli = 4;
771 }
772 dlli = (8 - dlli) & 0x7;
773 }
774 data |= dlli << 21;
775 }
776 }
777 moutdwm(ast, 0x1E6E0084, data);
778
779} /* finetuneDQI_L */
780
781static void finetuneDQI_L2(struct ast_private *ast, struct ast2300_dram_param *param)
782{
783 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, data2;
784
785 for (cnt = 0; cnt < 16; cnt++) {
786 dllmin[cnt] = 0xff;
787 dllmax[cnt] = 0x0;
788 }
789 passcnt = 0;
790 for (dlli = 0; dlli < 76; dlli++) {
791 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
792 /* Wait DQSI latch phase calibration */
793 moutdwm(ast, 0x1E6E0074, 0x00000010);
794 moutdwm(ast, 0x1E6E0070, 0x00000003);
795 do {
796 data = mindwm(ast, 0x1E6E0070);
797 } while (!(data & 0x00001000));
798 moutdwm(ast, 0x1E6E0070, 0x00000000);
799
800 moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
801 data = cbr_scan2(ast);
802 if (data != 0) {
803 mask = 0x00010001;
804 for (cnt = 0; cnt < 16; cnt++) {
805 if (data & mask) {
806 if (dllmin[cnt] > dlli) {
807 dllmin[cnt] = dlli;
808 }
809 if (dllmax[cnt] < dlli) {
810 dllmax[cnt] = dlli;
811 }
812 }
813 mask <<= 1;
814 }
815 passcnt++;
816 } else if (passcnt >= CBR_THRESHOLD2) {
817 break;
818 }
819 }
820 gold_sadj[0] = 0x0;
821 gold_sadj[1] = 0xFF;
822 for (cnt = 0; cnt < 8; cnt++) {
823 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
824 if (gold_sadj[0] < dllmin[cnt]) {
825 gold_sadj[0] = dllmin[cnt];
826 }
827 if (gold_sadj[1] > dllmax[cnt]) {
828 gold_sadj[1] = dllmax[cnt];
829 }
830 }
831 }
832 gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1;
833 gold_sadj[1] = mindwm(ast, 0x1E6E0080);
834
835 data = 0;
836 for (cnt = 0; cnt < 8; cnt++) {
837 data >>= 3;
838 data2 = gold_sadj[1] & 0x7;
839 gold_sadj[1] >>= 3;
840 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
841 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
842 if (gold_sadj[0] >= dlli) {
843 dlli = (gold_sadj[0] - dlli) >> 1;
844 if (dlli > 0) {
845 dlli = 1;
846 }
847 if (data2 != 3) {
848 data2 = (data2 + dlli) & 0x7;
849 }
850 } else {
851 dlli = (dlli - gold_sadj[0]) >> 1;
852 if (dlli > 0) {
853 dlli = 1;
854 }
855 if (data2 != 4) {
856 data2 = (data2 - dlli) & 0x7;
857 }
858 }
859 }
860 data |= data2 << 21;
861 }
862 moutdwm(ast, 0x1E6E0080, data);
863
864 gold_sadj[0] = 0x0;
865 gold_sadj[1] = 0xFF;
866 for (cnt = 8; cnt < 16; cnt++) {
867 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
868 if (gold_sadj[0] < dllmin[cnt]) {
869 gold_sadj[0] = dllmin[cnt];
870 }
871 if (gold_sadj[1] > dllmax[cnt]) {
872 gold_sadj[1] = dllmax[cnt];
873 }
874 }
875 }
876 gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1;
877 gold_sadj[1] = mindwm(ast, 0x1E6E0084);
878
879 data = 0;
880 for (cnt = 8; cnt < 16; cnt++) {
881 data >>= 3;
882 data2 = gold_sadj[1] & 0x7;
883 gold_sadj[1] >>= 3;
884 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
885 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
886 if (gold_sadj[0] >= dlli) {
887 dlli = (gold_sadj[0] - dlli) >> 1;
888 if (dlli > 0) {
889 dlli = 1;
890 }
891 if (data2 != 3) {
892 data2 = (data2 + dlli) & 0x7;
893 }
894 } else {
895 dlli = (dlli - gold_sadj[0]) >> 1;
896 if (dlli > 0) {
897 dlli = 1;
898 }
899 if (data2 != 4) {
900 data2 = (data2 - dlli) & 0x7;
901 }
902 }
903 }
904 data |= data2 << 21;
905 }
906 moutdwm(ast, 0x1E6E0084, data);
907
908} /* finetuneDQI_L2 */
909
910static void cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
911{
912 u32 dllmin[2], dllmax[2], dlli, data, data2, passcnt;
913
914
915 finetuneDQI_L(ast, param);
916 finetuneDQI_L2(ast, param);
917
918CBR_START2:
919 dllmin[0] = dllmin[1] = 0xff;
920 dllmax[0] = dllmax[1] = 0x0;
921 passcnt = 0;
922 for (dlli = 0; dlli < 76; dlli++) {
923 moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
924 /* Wait DQSI latch phase calibration */
925 moutdwm(ast, 0x1E6E0074, 0x00000010);
926 moutdwm(ast, 0x1E6E0070, 0x00000003);
927 do {
928 data = mindwm(ast, 0x1E6E0070);
929 } while (!(data & 0x00001000));
930 moutdwm(ast, 0x1E6E0070, 0x00000000);
931
932 moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
933 data = cbr_scan(ast);
934 if (data != 0) {
935 if (data & 0x1) {
936 if (dllmin[0] > dlli) {
937 dllmin[0] = dlli;
938 }
939 if (dllmax[0] < dlli) {
940 dllmax[0] = dlli;
941 }
942 }
943 if (data & 0x2) {
944 if (dllmin[1] > dlli) {
945 dllmin[1] = dlli;
946 }
947 if (dllmax[1] < dlli) {
948 dllmax[1] = dlli;
949 }
950 }
951 passcnt++;
952 } else if (passcnt >= CBR_THRESHOLD) {
953 break;
954 }
955 }
956 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
957 goto CBR_START2;
958 }
959 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
960 goto CBR_START2;
961 }
962 dlli = (dllmin[1] + dllmax[1]) >> 1;
963 dlli <<= 8;
964 dlli += (dllmin[0] + dllmax[0]) >> 1;
965 moutdwm(ast, 0x1E6E0068, (mindwm(ast, 0x1E6E0068) & 0xFFFF) | (dlli << 16));
966
967 data = (mindwm(ast, 0x1E6E0080) >> 24) & 0x1F;
968 data2 = (mindwm(ast, 0x1E6E0018) & 0xff80ffff) | (data << 16);
969 moutdwm(ast, 0x1E6E0018, data2);
970 moutdwm(ast, 0x1E6E0024, 0x8001 | (data << 1) | (param->dll2_finetune_step << 8));
971
972 /* Wait DQSI latch phase calibration */
973 moutdwm(ast, 0x1E6E0074, 0x00000010);
974 moutdwm(ast, 0x1E6E0070, 0x00000003);
975 do {
976 data = mindwm(ast, 0x1E6E0070);
977 } while (!(data & 0x00001000));
978 moutdwm(ast, 0x1E6E0070, 0x00000000);
979 moutdwm(ast, 0x1E6E0070, 0x00000003);
980 do {
981 data = mindwm(ast, 0x1E6E0070);
982 } while (!(data & 0x00001000));
983 moutdwm(ast, 0x1E6E0070, 0x00000000);
984} /* CBRDLL2 */
985
986static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
987{
988 u32 trap, trap_AC2, trap_MRS;
989
990 moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
991
992 /* Ger trap info */
993 trap = (mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
994 trap_AC2 = 0x00020000 + (trap << 16);
995 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
996 trap_MRS = 0x00000010 + (trap << 4);
997 trap_MRS |= ((trap & 0x2) << 18);
998
999 param->reg_MADJ = 0x00034C4C;
1000 param->reg_SADJ = 0x00001800;
1001 param->reg_DRV = 0x000000F0;
1002 param->reg_PERIOD = param->dram_freq;
1003 param->rodt = 0;
1004
1005 switch (param->dram_freq) {
1006 case 336:
1007 moutdwm(ast, 0x1E6E2020, 0x0190);
1008 param->wodt = 0;
1009 param->reg_AC1 = 0x22202725;
1010 param->reg_AC2 = 0xAA007613 | trap_AC2;
1011 param->reg_DQSIC = 0x000000BA;
1012 param->reg_MRS = 0x04001400 | trap_MRS;
1013 param->reg_EMRS = 0x00000000;
1014 param->reg_IOZ = 0x00000034;
1015 param->reg_DQIDLY = 0x00000074;
1016 param->reg_FREQ = 0x00004DC0;
1017 param->madj_max = 96;
1018 param->dll2_finetune_step = 3;
1019 break;
1020 default:
1021 case 396:
1022 moutdwm(ast, 0x1E6E2020, 0x03F1);
1023 param->wodt = 1;
1024 param->reg_AC1 = 0x33302825;
1025 param->reg_AC2 = 0xCC009617 | trap_AC2;
1026 param->reg_DQSIC = 0x000000E2;
1027 param->reg_MRS = 0x04001600 | trap_MRS;
1028 param->reg_EMRS = 0x00000000;
1029 param->reg_IOZ = 0x00000034;
1030 param->reg_DRV = 0x000000FA;
1031 param->reg_DQIDLY = 0x00000089;
1032 param->reg_FREQ = 0x000050C0;
1033 param->madj_max = 96;
1034 param->dll2_finetune_step = 4;
1035
1036 switch (param->dram_chipid) {
1037 default:
1038 case AST_DRAM_512Mx16:
1039 case AST_DRAM_1Gx16:
1040 param->reg_AC2 = 0xCC009617 | trap_AC2;
1041 break;
1042 case AST_DRAM_2Gx16:
1043 param->reg_AC2 = 0xCC009622 | trap_AC2;
1044 break;
1045 case AST_DRAM_4Gx16:
1046 param->reg_AC2 = 0xCC00963F | trap_AC2;
1047 break;
1048 }
1049 break;
1050
1051 case 408:
1052 moutdwm(ast, 0x1E6E2020, 0x01F0);
1053 param->wodt = 1;
1054 param->reg_AC1 = 0x33302825;
1055 param->reg_AC2 = 0xCC009617 | trap_AC2;
1056 param->reg_DQSIC = 0x000000E2;
1057 param->reg_MRS = 0x04001600 | trap_MRS;
1058 param->reg_EMRS = 0x00000000;
1059 param->reg_IOZ = 0x00000034;
1060 param->reg_DRV = 0x000000FA;
1061 param->reg_DQIDLY = 0x00000089;
1062 param->reg_FREQ = 0x000050C0;
1063 param->madj_max = 96;
1064 param->dll2_finetune_step = 4;
1065
1066 switch (param->dram_chipid) {
1067 default:
1068 case AST_DRAM_512Mx16:
1069 case AST_DRAM_1Gx16:
1070 param->reg_AC2 = 0xCC009617 | trap_AC2;
1071 break;
1072 case AST_DRAM_2Gx16:
1073 param->reg_AC2 = 0xCC009622 | trap_AC2;
1074 break;
1075 case AST_DRAM_4Gx16:
1076 param->reg_AC2 = 0xCC00963F | trap_AC2;
1077 break;
1078 }
1079
1080 break;
1081 case 456:
1082 moutdwm(ast, 0x1E6E2020, 0x0230);
1083 param->wodt = 0;
1084 param->reg_AC1 = 0x33302926;
1085 param->reg_AC2 = 0xCD44961A;
1086 param->reg_DQSIC = 0x000000FC;
1087 param->reg_MRS = 0x00081830;
1088 param->reg_EMRS = 0x00000000;
1089 param->reg_IOZ = 0x00000045;
1090 param->reg_DQIDLY = 0x00000097;
1091 param->reg_FREQ = 0x000052C0;
1092 param->madj_max = 88;
1093 param->dll2_finetune_step = 4;
1094 break;
1095 case 504:
1096 moutdwm(ast, 0x1E6E2020, 0x0270);
1097 param->wodt = 1;
1098 param->reg_AC1 = 0x33302926;
1099 param->reg_AC2 = 0xDE44A61D;
1100 param->reg_DQSIC = 0x00000117;
1101 param->reg_MRS = 0x00081A30;
1102 param->reg_EMRS = 0x00000000;
1103 param->reg_IOZ = 0x070000BB;
1104 param->reg_DQIDLY = 0x000000A0;
1105 param->reg_FREQ = 0x000054C0;
1106 param->madj_max = 79;
1107 param->dll2_finetune_step = 4;
1108 break;
1109 case 528:
1110 moutdwm(ast, 0x1E6E2020, 0x0290);
1111 param->wodt = 1;
1112 param->rodt = 1;
1113 param->reg_AC1 = 0x33302926;
1114 param->reg_AC2 = 0xEF44B61E;
1115 param->reg_DQSIC = 0x00000125;
1116 param->reg_MRS = 0x00081A30;
1117 param->reg_EMRS = 0x00000040;
1118 param->reg_DRV = 0x000000F5;
1119 param->reg_IOZ = 0x00000023;
1120 param->reg_DQIDLY = 0x00000088;
1121 param->reg_FREQ = 0x000055C0;
1122 param->madj_max = 76;
1123 param->dll2_finetune_step = 3;
1124 break;
1125 case 576:
1126 moutdwm(ast, 0x1E6E2020, 0x0140);
1127 param->reg_MADJ = 0x00136868;
1128 param->reg_SADJ = 0x00004534;
1129 param->wodt = 1;
1130 param->rodt = 1;
1131 param->reg_AC1 = 0x33302A37;
1132 param->reg_AC2 = 0xEF56B61E;
1133 param->reg_DQSIC = 0x0000013F;
1134 param->reg_MRS = 0x00101A50;
1135 param->reg_EMRS = 0x00000040;
1136 param->reg_DRV = 0x000000FA;
1137 param->reg_IOZ = 0x00000023;
1138 param->reg_DQIDLY = 0x00000078;
1139 param->reg_FREQ = 0x000057C0;
1140 param->madj_max = 136;
1141 param->dll2_finetune_step = 3;
1142 break;
1143 case 600:
1144 moutdwm(ast, 0x1E6E2020, 0x02E1);
1145 param->reg_MADJ = 0x00136868;
1146 param->reg_SADJ = 0x00004534;
1147 param->wodt = 1;
1148 param->rodt = 1;
1149 param->reg_AC1 = 0x32302A37;
1150 param->reg_AC2 = 0xDF56B61F;
1151 param->reg_DQSIC = 0x0000014D;
1152 param->reg_MRS = 0x00101A50;
1153 param->reg_EMRS = 0x00000004;
1154 param->reg_DRV = 0x000000F5;
1155 param->reg_IOZ = 0x00000023;
1156 param->reg_DQIDLY = 0x00000078;
1157 param->reg_FREQ = 0x000058C0;
1158 param->madj_max = 132;
1159 param->dll2_finetune_step = 3;
1160 break;
1161 case 624:
1162 moutdwm(ast, 0x1E6E2020, 0x0160);
1163 param->reg_MADJ = 0x00136868;
1164 param->reg_SADJ = 0x00004534;
1165 param->wodt = 1;
1166 param->rodt = 1;
1167 param->reg_AC1 = 0x32302A37;
1168 param->reg_AC2 = 0xEF56B621;
1169 param->reg_DQSIC = 0x0000015A;
1170 param->reg_MRS = 0x02101A50;
1171 param->reg_EMRS = 0x00000004;
1172 param->reg_DRV = 0x000000F5;
1173 param->reg_IOZ = 0x00000034;
1174 param->reg_DQIDLY = 0x00000078;
1175 param->reg_FREQ = 0x000059C0;
1176 param->madj_max = 128;
1177 param->dll2_finetune_step = 3;
1178 break;
1179 } /* switch freq */
1180
1181 switch (param->dram_chipid) {
1182 case AST_DRAM_512Mx16:
1183 param->dram_config = 0x130;
1184 break;
1185 default:
1186 case AST_DRAM_1Gx16:
1187 param->dram_config = 0x131;
1188 break;
1189 case AST_DRAM_2Gx16:
1190 param->dram_config = 0x132;
1191 break;
1192 case AST_DRAM_4Gx16:
1193 param->dram_config = 0x133;
1194 break;
1195 }; /* switch size */
1196
1197 switch (param->vram_size) {
1198 default:
1199 case AST_VIDMEM_SIZE_8M:
1200 param->dram_config |= 0x00;
1201 break;
1202 case AST_VIDMEM_SIZE_16M:
1203 param->dram_config |= 0x04;
1204 break;
1205 case AST_VIDMEM_SIZE_32M:
1206 param->dram_config |= 0x08;
1207 break;
1208 case AST_VIDMEM_SIZE_64M:
1209 param->dram_config |= 0x0c;
1210 break;
1211 }
1212
1213}
1214
1215static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1216{
1217 u32 data, data2;
1218
1219 moutdwm(ast, 0x1E6E0000, 0xFC600309);
1220 moutdwm(ast, 0x1E6E0018, 0x00000100);
1221 moutdwm(ast, 0x1E6E0024, 0x00000000);
1222 moutdwm(ast, 0x1E6E0034, 0x00000000);
1223 udelay(10);
1224 moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1225 moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1226 udelay(10);
1227 moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1228 udelay(10);
1229
1230 moutdwm(ast, 0x1E6E0004, param->dram_config);
1231 moutdwm(ast, 0x1E6E0008, 0x90040f);
1232 moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1233 moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1234 moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1235 moutdwm(ast, 0x1E6E0080, 0x00000000);
1236 moutdwm(ast, 0x1E6E0084, 0x00000000);
1237 moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1238 moutdwm(ast, 0x1E6E0018, 0x4040A170);
1239 moutdwm(ast, 0x1E6E0018, 0x20402370);
1240 moutdwm(ast, 0x1E6E0038, 0x00000000);
1241 moutdwm(ast, 0x1E6E0040, 0xFF444444);
1242 moutdwm(ast, 0x1E6E0044, 0x22222222);
1243 moutdwm(ast, 0x1E6E0048, 0x22222222);
1244 moutdwm(ast, 0x1E6E004C, 0x00000002);
1245 moutdwm(ast, 0x1E6E0050, 0x80000000);
1246 moutdwm(ast, 0x1E6E0050, 0x00000000);
1247 moutdwm(ast, 0x1E6E0054, 0);
1248 moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1249 moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1250 moutdwm(ast, 0x1E6E0070, 0x00000000);
1251 moutdwm(ast, 0x1E6E0074, 0x00000000);
1252 moutdwm(ast, 0x1E6E0078, 0x00000000);
1253 moutdwm(ast, 0x1E6E007C, 0x00000000);
1254 /* Wait MCLK2X lock to MCLK */
1255 do {
1256 data = mindwm(ast, 0x1E6E001C);
1257 } while (!(data & 0x08000000));
1258 moutdwm(ast, 0x1E6E0034, 0x00000001);
1259 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1260 udelay(10);
1261 moutdwm(ast, 0x1E6E000C, 0x00000000);
1262 moutdwm(ast, 0x1E6E0034, 0x00000000);
1263 data = mindwm(ast, 0x1E6E001C);
1264 data = (data >> 8) & 0xff;
1265 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1266 data2 = (mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1267 if ((data2 & 0xff) > param->madj_max) {
1268 break;
1269 }
1270 moutdwm(ast, 0x1E6E0064, data2);
1271 if (data2 & 0x00100000) {
1272 data2 = ((data2 & 0xff) >> 3) + 3;
1273 } else {
1274 data2 = ((data2 & 0xff) >> 2) + 5;
1275 }
1276 data = mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1277 data2 += data & 0xff;
1278 data = data | (data2 << 8);
1279 moutdwm(ast, 0x1E6E0068, data);
1280 udelay(10);
1281 moutdwm(ast, 0x1E6E0064, mindwm(ast, 0x1E6E0064) | 0xC0000);
1282 udelay(10);
1283 data = mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1284 moutdwm(ast, 0x1E6E0018, data);
1285 data = data | 0x200;
1286 moutdwm(ast, 0x1E6E0018, data);
1287 do {
1288 data = mindwm(ast, 0x1E6E001C);
1289 } while (!(data & 0x08000000));
1290
1291 moutdwm(ast, 0x1E6E0034, 0x00000001);
1292 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1293 udelay(10);
1294 moutdwm(ast, 0x1E6E000C, 0x00000000);
1295 moutdwm(ast, 0x1E6E0034, 0x00000000);
1296 data = mindwm(ast, 0x1E6E001C);
1297 data = (data >> 8) & 0xff;
1298 }
1299 data = mindwm(ast, 0x1E6E0018) | 0xC00;
1300 moutdwm(ast, 0x1E6E0018, data);
1301
1302 moutdwm(ast, 0x1E6E0034, 0x00000001);
1303 moutdwm(ast, 0x1E6E000C, 0x00000040);
1304 udelay(50);
1305 /* Mode Register Setting */
1306 moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1307 moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1308 moutdwm(ast, 0x1E6E0028, 0x00000005);
1309 moutdwm(ast, 0x1E6E0028, 0x00000007);
1310 moutdwm(ast, 0x1E6E0028, 0x00000003);
1311 moutdwm(ast, 0x1E6E0028, 0x00000001);
1312 moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1313 moutdwm(ast, 0x1E6E000C, 0x00005C08);
1314 moutdwm(ast, 0x1E6E0028, 0x00000001);
1315
1316 moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1317 data = 0;
1318 if (param->wodt) {
1319 data = 0x300;
1320 }
1321 if (param->rodt) {
1322 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1323 }
1324 moutdwm(ast, 0x1E6E0034, data | 0x3);
1325
1326 /* Wait DQI delay lock */
1327 do {
1328 data = mindwm(ast, 0x1E6E0080);
1329 } while (!(data & 0x40000000));
1330 /* Wait DQSI delay lock */
1331 do {
1332 data = mindwm(ast, 0x1E6E0020);
1333 } while (!(data & 0x00000800));
1334 /* Calibrate the DQSI delay */
1335 cbr_dll2(ast, param);
1336
1337 moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1338 /* ECC Memory Initialization */
1339#ifdef ECC
1340 moutdwm(ast, 0x1E6E007C, 0x00000000);
1341 moutdwm(ast, 0x1E6E0070, 0x221);
1342 do {
1343 data = mindwm(ast, 0x1E6E0070);
1344 } while (!(data & 0x00001000));
1345 moutdwm(ast, 0x1E6E0070, 0x00000000);
1346 moutdwm(ast, 0x1E6E0050, 0x80000000);
1347 moutdwm(ast, 0x1E6E0050, 0x00000000);
1348#endif
1349
1350
1351}
1352
1353static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
1354{
1355 u32 trap, trap_AC2, trap_MRS;
1356
1357 moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1358
1359 /* Ger trap info */
1360 trap = (mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1361 trap_AC2 = (trap << 20) | (trap << 16);
1362 trap_AC2 += 0x00110000;
1363 trap_MRS = 0x00000040 | (trap << 4);
1364
1365
1366 param->reg_MADJ = 0x00034C4C;
1367 param->reg_SADJ = 0x00001800;
1368 param->reg_DRV = 0x000000F0;
1369 param->reg_PERIOD = param->dram_freq;
1370 param->rodt = 0;
1371
1372 switch (param->dram_freq) {
1373 case 264:
1374 moutdwm(ast, 0x1E6E2020, 0x0130);
1375 param->wodt = 0;
1376 param->reg_AC1 = 0x11101513;
1377 param->reg_AC2 = 0x78117011;
1378 param->reg_DQSIC = 0x00000092;
1379 param->reg_MRS = 0x00000842;
1380 param->reg_EMRS = 0x00000000;
1381 param->reg_DRV = 0x000000F0;
1382 param->reg_IOZ = 0x00000034;
1383 param->reg_DQIDLY = 0x0000005A;
1384 param->reg_FREQ = 0x00004AC0;
1385 param->madj_max = 138;
1386 param->dll2_finetune_step = 3;
1387 break;
1388 case 336:
1389 moutdwm(ast, 0x1E6E2020, 0x0190);
1390 param->wodt = 1;
1391 param->reg_AC1 = 0x22202613;
1392 param->reg_AC2 = 0xAA009016 | trap_AC2;
1393 param->reg_DQSIC = 0x000000BA;
1394 param->reg_MRS = 0x00000A02 | trap_MRS;
1395 param->reg_EMRS = 0x00000040;
1396 param->reg_DRV = 0x000000FA;
1397 param->reg_IOZ = 0x00000034;
1398 param->reg_DQIDLY = 0x00000074;
1399 param->reg_FREQ = 0x00004DC0;
1400 param->madj_max = 96;
1401 param->dll2_finetune_step = 3;
1402 break;
1403 default:
1404 case 396:
1405 moutdwm(ast, 0x1E6E2020, 0x03F1);
1406 param->wodt = 1;
1407 param->rodt = 0;
1408 param->reg_AC1 = 0x33302714;
1409 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1410 param->reg_DQSIC = 0x000000E2;
1411 param->reg_MRS = 0x00000C02 | trap_MRS;
1412 param->reg_EMRS = 0x00000040;
1413 param->reg_DRV = 0x000000FA;
1414 param->reg_IOZ = 0x00000034;
1415 param->reg_DQIDLY = 0x00000089;
1416 param->reg_FREQ = 0x000050C0;
1417 param->madj_max = 96;
1418 param->dll2_finetune_step = 4;
1419
1420 switch (param->dram_chipid) {
1421 case AST_DRAM_512Mx16:
1422 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1423 break;
1424 default:
1425 case AST_DRAM_1Gx16:
1426 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1427 break;
1428 case AST_DRAM_2Gx16:
1429 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1430 break;
1431 case AST_DRAM_4Gx16:
1432 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1433 break;
1434 }
1435
1436 break;
1437
1438 case 408:
1439 moutdwm(ast, 0x1E6E2020, 0x01F0);
1440 param->wodt = 1;
1441 param->rodt = 0;
1442 param->reg_AC1 = 0x33302714;
1443 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1444 param->reg_DQSIC = 0x000000E2;
1445 param->reg_MRS = 0x00000C02 | trap_MRS;
1446 param->reg_EMRS = 0x00000040;
1447 param->reg_DRV = 0x000000FA;
1448 param->reg_IOZ = 0x00000034;
1449 param->reg_DQIDLY = 0x00000089;
1450 param->reg_FREQ = 0x000050C0;
1451 param->madj_max = 96;
1452 param->dll2_finetune_step = 4;
1453
1454 switch (param->dram_chipid) {
1455 case AST_DRAM_512Mx16:
1456 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1457 break;
1458 default:
1459 case AST_DRAM_1Gx16:
1460 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1461 break;
1462 case AST_DRAM_2Gx16:
1463 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1464 break;
1465 case AST_DRAM_4Gx16:
1466 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1467 break;
1468 }
1469
1470 break;
1471 case 456:
1472 moutdwm(ast, 0x1E6E2020, 0x0230);
1473 param->wodt = 0;
1474 param->reg_AC1 = 0x33302815;
1475 param->reg_AC2 = 0xCD44B01E;
1476 param->reg_DQSIC = 0x000000FC;
1477 param->reg_MRS = 0x00000E72;
1478 param->reg_EMRS = 0x00000000;
1479 param->reg_DRV = 0x00000000;
1480 param->reg_IOZ = 0x00000034;
1481 param->reg_DQIDLY = 0x00000097;
1482 param->reg_FREQ = 0x000052C0;
1483 param->madj_max = 88;
1484 param->dll2_finetune_step = 3;
1485 break;
1486 case 504:
1487 moutdwm(ast, 0x1E6E2020, 0x0261);
1488 param->wodt = 1;
1489 param->rodt = 1;
1490 param->reg_AC1 = 0x33302815;
1491 param->reg_AC2 = 0xDE44C022;
1492 param->reg_DQSIC = 0x00000117;
1493 param->reg_MRS = 0x00000E72;
1494 param->reg_EMRS = 0x00000040;
1495 param->reg_DRV = 0x0000000A;
1496 param->reg_IOZ = 0x00000045;
1497 param->reg_DQIDLY = 0x000000A0;
1498 param->reg_FREQ = 0x000054C0;
1499 param->madj_max = 79;
1500 param->dll2_finetune_step = 3;
1501 break;
1502 case 528:
1503 moutdwm(ast, 0x1E6E2020, 0x0120);
1504 param->wodt = 1;
1505 param->rodt = 1;
1506 param->reg_AC1 = 0x33302815;
1507 param->reg_AC2 = 0xEF44D024;
1508 param->reg_DQSIC = 0x00000125;
1509 param->reg_MRS = 0x00000E72;
1510 param->reg_EMRS = 0x00000004;
1511 param->reg_DRV = 0x000000F9;
1512 param->reg_IOZ = 0x00000045;
1513 param->reg_DQIDLY = 0x000000A7;
1514 param->reg_FREQ = 0x000055C0;
1515 param->madj_max = 76;
1516 param->dll2_finetune_step = 3;
1517 break;
1518 case 552:
1519 moutdwm(ast, 0x1E6E2020, 0x02A1);
1520 param->wodt = 1;
1521 param->rodt = 1;
1522 param->reg_AC1 = 0x43402915;
1523 param->reg_AC2 = 0xFF44E025;
1524 param->reg_DQSIC = 0x00000132;
1525 param->reg_MRS = 0x00000E72;
1526 param->reg_EMRS = 0x00000040;
1527 param->reg_DRV = 0x0000000A;
1528 param->reg_IOZ = 0x00000045;
1529 param->reg_DQIDLY = 0x000000AD;
1530 param->reg_FREQ = 0x000056C0;
1531 param->madj_max = 76;
1532 param->dll2_finetune_step = 3;
1533 break;
1534 case 576:
1535 moutdwm(ast, 0x1E6E2020, 0x0140);
1536 param->wodt = 1;
1537 param->rodt = 1;
1538 param->reg_AC1 = 0x43402915;
1539 param->reg_AC2 = 0xFF44E027;
1540 param->reg_DQSIC = 0x0000013F;
1541 param->reg_MRS = 0x00000E72;
1542 param->reg_EMRS = 0x00000004;
1543 param->reg_DRV = 0x000000F5;
1544 param->reg_IOZ = 0x00000045;
1545 param->reg_DQIDLY = 0x000000B3;
1546 param->reg_FREQ = 0x000057C0;
1547 param->madj_max = 76;
1548 param->dll2_finetune_step = 3;
1549 break;
1550 }
1551
1552 switch (param->dram_chipid) {
1553 case AST_DRAM_512Mx16:
1554 param->dram_config = 0x100;
1555 break;
1556 default:
1557 case AST_DRAM_1Gx16:
1558 param->dram_config = 0x121;
1559 break;
1560 case AST_DRAM_2Gx16:
1561 param->dram_config = 0x122;
1562 break;
1563 case AST_DRAM_4Gx16:
1564 param->dram_config = 0x123;
1565 break;
1566 }; /* switch size */
1567
1568 switch (param->vram_size) {
1569 default:
1570 case AST_VIDMEM_SIZE_8M:
1571 param->dram_config |= 0x00;
1572 break;
1573 case AST_VIDMEM_SIZE_16M:
1574 param->dram_config |= 0x04;
1575 break;
1576 case AST_VIDMEM_SIZE_32M:
1577 param->dram_config |= 0x08;
1578 break;
1579 case AST_VIDMEM_SIZE_64M:
1580 param->dram_config |= 0x0c;
1581 break;
1582 }
1583}
1584
1585static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1586{
1587 u32 data, data2;
1588
1589 moutdwm(ast, 0x1E6E0000, 0xFC600309);
1590 moutdwm(ast, 0x1E6E0018, 0x00000100);
1591 moutdwm(ast, 0x1E6E0024, 0x00000000);
1592 moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1593 moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1594 udelay(10);
1595 moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1596 udelay(10);
1597
1598 moutdwm(ast, 0x1E6E0004, param->dram_config);
1599 moutdwm(ast, 0x1E6E0008, 0x90040f);
1600 moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1601 moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1602 moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1603 moutdwm(ast, 0x1E6E0080, 0x00000000);
1604 moutdwm(ast, 0x1E6E0084, 0x00000000);
1605 moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1606 moutdwm(ast, 0x1E6E0018, 0x4040A130);
1607 moutdwm(ast, 0x1E6E0018, 0x20402330);
1608 moutdwm(ast, 0x1E6E0038, 0x00000000);
1609 moutdwm(ast, 0x1E6E0040, 0xFF808000);
1610 moutdwm(ast, 0x1E6E0044, 0x88848466);
1611 moutdwm(ast, 0x1E6E0048, 0x44440008);
1612 moutdwm(ast, 0x1E6E004C, 0x00000000);
1613 moutdwm(ast, 0x1E6E0050, 0x80000000);
1614 moutdwm(ast, 0x1E6E0050, 0x00000000);
1615 moutdwm(ast, 0x1E6E0054, 0);
1616 moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1617 moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1618 moutdwm(ast, 0x1E6E0070, 0x00000000);
1619 moutdwm(ast, 0x1E6E0074, 0x00000000);
1620 moutdwm(ast, 0x1E6E0078, 0x00000000);
1621 moutdwm(ast, 0x1E6E007C, 0x00000000);
1622
1623 /* Wait MCLK2X lock to MCLK */
1624 do {
1625 data = mindwm(ast, 0x1E6E001C);
1626 } while (!(data & 0x08000000));
1627 moutdwm(ast, 0x1E6E0034, 0x00000001);
1628 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1629 udelay(10);
1630 moutdwm(ast, 0x1E6E000C, 0x00000000);
1631 moutdwm(ast, 0x1E6E0034, 0x00000000);
1632 data = mindwm(ast, 0x1E6E001C);
1633 data = (data >> 8) & 0xff;
1634 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1635 data2 = (mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1636 if ((data2 & 0xff) > param->madj_max) {
1637 break;
1638 }
1639 moutdwm(ast, 0x1E6E0064, data2);
1640 if (data2 & 0x00100000) {
1641 data2 = ((data2 & 0xff) >> 3) + 3;
1642 } else {
1643 data2 = ((data2 & 0xff) >> 2) + 5;
1644 }
1645 data = mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1646 data2 += data & 0xff;
1647 data = data | (data2 << 8);
1648 moutdwm(ast, 0x1E6E0068, data);
1649 udelay(10);
1650 moutdwm(ast, 0x1E6E0064, mindwm(ast, 0x1E6E0064) | 0xC0000);
1651 udelay(10);
1652 data = mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1653 moutdwm(ast, 0x1E6E0018, data);
1654 data = data | 0x200;
1655 moutdwm(ast, 0x1E6E0018, data);
1656 do {
1657 data = mindwm(ast, 0x1E6E001C);
1658 } while (!(data & 0x08000000));
1659
1660 moutdwm(ast, 0x1E6E0034, 0x00000001);
1661 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1662 udelay(10);
1663 moutdwm(ast, 0x1E6E000C, 0x00000000);
1664 moutdwm(ast, 0x1E6E0034, 0x00000000);
1665 data = mindwm(ast, 0x1E6E001C);
1666 data = (data >> 8) & 0xff;
1667 }
1668 data = mindwm(ast, 0x1E6E0018) | 0xC00;
1669 moutdwm(ast, 0x1E6E0018, data);
1670
1671 moutdwm(ast, 0x1E6E0034, 0x00000001);
1672 moutdwm(ast, 0x1E6E000C, 0x00000000);
1673 udelay(50);
1674 /* Mode Register Setting */
1675 moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1676 moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1677 moutdwm(ast, 0x1E6E0028, 0x00000005);
1678 moutdwm(ast, 0x1E6E0028, 0x00000007);
1679 moutdwm(ast, 0x1E6E0028, 0x00000003);
1680 moutdwm(ast, 0x1E6E0028, 0x00000001);
1681
1682 moutdwm(ast, 0x1E6E000C, 0x00005C08);
1683 moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1684 moutdwm(ast, 0x1E6E0028, 0x00000001);
1685 moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1686 moutdwm(ast, 0x1E6E0028, 0x00000003);
1687 moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1688 moutdwm(ast, 0x1E6E0028, 0x00000003);
1689
1690 moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1691 data = 0;
1692 if (param->wodt) {
1693 data = 0x500;
1694 }
1695 if (param->rodt) {
1696 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1697 }
1698 moutdwm(ast, 0x1E6E0034, data | 0x3);
1699 moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1700
1701 /* Wait DQI delay lock */
1702 do {
1703 data = mindwm(ast, 0x1E6E0080);
1704 } while (!(data & 0x40000000));
1705 /* Wait DQSI delay lock */
1706 do {
1707 data = mindwm(ast, 0x1E6E0020);
1708 } while (!(data & 0x00000800));
1709 /* Calibrate the DQSI delay */
1710 cbr_dll2(ast, param);
1711
1712 /* ECC Memory Initialization */
1713#ifdef ECC
1714 moutdwm(ast, 0x1E6E007C, 0x00000000);
1715 moutdwm(ast, 0x1E6E0070, 0x221);
1716 do {
1717 data = mindwm(ast, 0x1E6E0070);
1718 } while (!(data & 0x00001000));
1719 moutdwm(ast, 0x1E6E0070, 0x00000000);
1720 moutdwm(ast, 0x1E6E0050, 0x80000000);
1721 moutdwm(ast, 0x1E6E0050, 0x00000000);
1722#endif
1723
1724}
1725
1726static void ast_init_dram_2300(struct drm_device *dev)
1727{
1728 struct ast_private *ast = dev->dev_private;
1729 struct ast2300_dram_param param;
1730 u32 temp;
1731 u8 reg;
1732
1733 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1734 if ((reg & 0x80) == 0) {/* vga only */
1735 ast_write32(ast, 0xf004, 0x1e6e0000);
1736 ast_write32(ast, 0xf000, 0x1);
1737 ast_write32(ast, 0x12000, 0x1688a8a8);
1738 do {
1739 ;
1740 } while (ast_read32(ast, 0x12000) != 0x1);
1741
1742 ast_write32(ast, 0x10000, 0xfc600309);
1743 do {
1744 ;
1745 } while (ast_read32(ast, 0x10000) != 0x1);
1746
1747 /* Slow down CPU/AHB CLK in VGA only mode */
1748 temp = ast_read32(ast, 0x12008);
1749 temp |= 0x73;
1750 ast_write32(ast, 0x12008, temp);
1751
1752 param.dram_type = AST_DDR3;
1753 if (temp & 0x01000000)
1754 param.dram_type = AST_DDR2;
1755 param.dram_chipid = ast->dram_type;
1756 param.dram_freq = ast->mclk;
1757 param.vram_size = ast->vram_size;
1758
1759 if (param.dram_type == AST_DDR3) {
1760 get_ddr3_info(ast, &param);
1761 ddr3_init(ast, &param);
1762 } else {
1763 get_ddr2_info(ast, &param);
1764 ddr2_init(ast, &param);
1765 }
1766
1767 temp = mindwm(ast, 0x1e6e2040);
1768 moutdwm(ast, 0x1e6e2040, temp | 0x40);
1769 }
1770
1771 /* wait ready */
1772 do {
1773 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1774 } while ((reg & 0x40) == 0);
1775}
1776
kernel source for telekom puls (alcatel/mediatek)