| 1 | /* |
| 2 | * Spin Table SMP initialisation |
| 3 | * |
| 4 | * Copyright (C) 2013 ARM Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/smp.h> |
| 23 | |
| 24 | #include <asm/cacheflush.h> |
| 25 | #include <asm/cpu_ops.h> |
| 26 | #include <asm/cputype.h> |
| 27 | #include <asm/smp_plat.h> |
| 28 | |
| 29 | extern void secondary_holding_pen(void); |
| 30 | volatile unsigned long secondary_holding_pen_release = INVALID_HWID; |
| 31 | |
| 32 | #include <linux/io.h> |
| 33 | #include <linux/of_address.h> |
| 34 | |
| 35 | |
| 36 | static phys_addr_t cpu_release_addr[NR_CPUS]; |
| 37 | static DEFINE_RAW_SPINLOCK(boot_lock); |
| 38 | |
| 39 | /* |
| 40 | * Write secondary_holding_pen_release in a way that is guaranteed to be |
| 41 | * visible to all observers, irrespective of whether they're taking part |
| 42 | * in coherency or not. This is necessary for the hotplug code to work |
| 43 | * reliably. |
| 44 | */ |
| 45 | static void write_pen_release(u64 val) |
| 46 | { |
| 47 | void *start = (void *)&secondary_holding_pen_release; |
| 48 | unsigned long size = sizeof(secondary_holding_pen_release); |
| 49 | |
| 50 | secondary_holding_pen_release = val; |
| 51 | __flush_dcache_area(start, size); |
| 52 | } |
| 53 | |
| 54 | |
| 55 | static int smp_spin_table_cpu_init(struct device_node *dn, unsigned int cpu) |
| 56 | { |
| 57 | /* |
| 58 | * Determine the address from which the CPU is polling. |
| 59 | */ |
| 60 | if (of_property_read_u64(dn, "cpu-release-addr", |
| 61 | &cpu_release_addr[cpu])) { |
| 62 | pr_err("CPU %d: missing or invalid cpu-release-addr property\n", |
| 63 | cpu); |
| 64 | |
| 65 | return -1; |
| 66 | } |
| 67 | |
| 68 | return 0; |
| 69 | } |
| 70 | |
| 71 | /*MTK only*/ |
| 72 | #define CCI400_SI4_BASE 0x5000 |
| 73 | #define CCI400_SI4_SNOOP_CONTROL CCI400_SI4_BASE |
| 74 | #define DVM_MSG_REQ (1U << 1) |
| 75 | #define SNOOP_REQ (1U << 0) |
| 76 | #define CCI400_STATUS 0x000C |
| 77 | #define CHANGE_PENDING (1U << 0) |
| 78 | |
| 79 | static int smp_spin_table_cpu_prepare(unsigned int cpu) |
| 80 | { |
| 81 | void **release_addr; |
| 82 | |
| 83 | struct device_node *node; |
| 84 | void __iomem *cci400_base; |
| 85 | |
| 86 | if (!cpu_release_addr[cpu]) |
| 87 | return -ENODEV; |
| 88 | |
| 89 | /*MTK only. Setup coherence interface*/ |
| 90 | node = of_find_compatible_node(NULL, NULL, "mediatek,CCI400"); |
| 91 | if(node) |
| 92 | { |
| 93 | cci400_base = of_iomap(node, 0); |
| 94 | |
| 95 | printk(KERN_EMERG "1.CCI400_SI4_SNOOP_CONTROL:0x%p, 0x%08x\n", cci400_base + CCI400_SI4_SNOOP_CONTROL, readl(cci400_base + CCI400_SI4_SNOOP_CONTROL)); |
| 96 | /* Enable snoop requests and DVM message requests*/ |
| 97 | writel(readl(cci400_base + CCI400_SI4_SNOOP_CONTROL) | (SNOOP_REQ | DVM_MSG_REQ), cci400_base + CCI400_SI4_SNOOP_CONTROL); |
| 98 | while (readl(cci400_base + CCI400_STATUS) & CHANGE_PENDING); |
| 99 | printk(KERN_EMERG "2.CCI400_SI4_SNOOP_CONTROL:0x%p, 0x%08x\n", cci400_base + CCI400_SI4_SNOOP_CONTROL,readl(cci400_base + CCI400_SI4_SNOOP_CONTROL)); |
| 100 | } |
| 101 | |
| 102 | release_addr = __va(cpu_release_addr[cpu]); |
| 103 | release_addr[0] = (void *)__pa(secondary_holding_pen); |
| 104 | __flush_dcache_area(release_addr, sizeof(release_addr[0])); |
| 105 | |
| 106 | /* |
| 107 | * Send an event to wake up the secondary CPU. |
| 108 | */ |
| 109 | sev(); |
| 110 | |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | static int smp_spin_table_cpu_boot(unsigned int cpu) |
| 115 | { |
| 116 | unsigned long timeout; |
| 117 | |
| 118 | /* |
| 119 | * Set synchronisation state between this boot processor |
| 120 | * and the secondary one |
| 121 | */ |
| 122 | raw_spin_lock(&boot_lock); |
| 123 | |
| 124 | /* |
| 125 | * Update the pen release flag. |
| 126 | */ |
| 127 | write_pen_release(cpu_logical_map(cpu)); |
| 128 | |
| 129 | /* |
| 130 | * Send an event, causing the secondaries to read pen_release. |
| 131 | */ |
| 132 | sev(); |
| 133 | |
| 134 | timeout = jiffies + (1 * HZ); |
| 135 | while (time_before(jiffies, timeout)) { |
| 136 | if (secondary_holding_pen_release == INVALID_HWID) |
| 137 | break; |
| 138 | udelay(10); |
| 139 | } |
| 140 | |
| 141 | /* |
| 142 | * Now the secondary core is starting up let it run its |
| 143 | * calibrations, then wait for it to finish |
| 144 | */ |
| 145 | raw_spin_unlock(&boot_lock); |
| 146 | |
| 147 | return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0; |
| 148 | } |
| 149 | |
| 150 | void smp_spin_table_cpu_postboot(void) |
| 151 | { |
| 152 | /* |
| 153 | * Let the primary processor know we're out of the pen. |
| 154 | */ |
| 155 | write_pen_release(INVALID_HWID); |
| 156 | |
| 157 | /* |
| 158 | * Synchronise with the boot thread. |
| 159 | */ |
| 160 | raw_spin_lock(&boot_lock); |
| 161 | raw_spin_unlock(&boot_lock); |
| 162 | } |
| 163 | |
| 164 | const struct cpu_operations smp_spin_table_ops = { |
| 165 | .name = "spin-table", |
| 166 | .cpu_init = smp_spin_table_cpu_init, |
| 167 | .cpu_prepare = smp_spin_table_cpu_prepare, |
| 168 | .cpu_boot = smp_spin_table_cpu_boot, |
| 169 | .cpu_postboot = smp_spin_table_cpu_postboot, |
| 170 | }; |