| 1 | /* |
| 2 | * linux/arch/arm/kernel/entry-armv.S |
| 3 | * |
| 4 | * Copyright (C) 1996,1997,1998 Russell King. |
| 5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) |
| 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * Low-level vector interface routines |
| 13 | * |
| 14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
| 15 | * that causes it to save wrong values... Be aware! |
| 16 | */ |
| 17 | |
| 18 | #include <asm/assembler.h> |
| 19 | #include <asm/memory.h> |
| 20 | #include <asm/glue-df.h> |
| 21 | #include <asm/glue-pf.h> |
| 22 | #include <asm/vfpmacros.h> |
| 23 | #ifndef CONFIG_MULTI_IRQ_HANDLER |
| 24 | #include <mach/entry-macro.S> |
| 25 | #endif |
| 26 | #include <asm/thread_notify.h> |
| 27 | #include <asm/unwind.h> |
| 28 | #include <asm/unistd.h> |
| 29 | #include <asm/tls.h> |
| 30 | #include <asm/system_info.h> |
| 31 | |
| 32 | #include "entry-header.S" |
| 33 | #include <asm/entry-macro-multi.S> |
| 34 | |
| 35 | /* |
| 36 | * Interrupt handling. |
| 37 | */ |
| 38 | .macro irq_handler |
| 39 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
| 40 | ldr r1, =handle_arch_irq |
| 41 | mov r0, sp |
| 42 | adr lr, BSYM(9997f) |
| 43 | ldr pc, [r1] |
| 44 | #else |
| 45 | arch_irq_handler_default |
| 46 | #endif |
| 47 | 9997: |
| 48 | .endm |
| 49 | |
| 50 | .macro pabt_helper |
| 51 | @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 |
| 52 | #ifdef MULTI_PABORT |
| 53 | ldr ip, .LCprocfns |
| 54 | mov lr, pc |
| 55 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
| 56 | #else |
| 57 | bl CPU_PABORT_HANDLER |
| 58 | #endif |
| 59 | .endm |
| 60 | |
| 61 | .macro dabt_helper |
| 62 | |
| 63 | @ |
| 64 | @ Call the processor-specific abort handler: |
| 65 | @ |
| 66 | @ r2 - pt_regs |
| 67 | @ r4 - aborted context pc |
| 68 | @ r5 - aborted context psr |
| 69 | @ |
| 70 | @ The abort handler must return the aborted address in r0, and |
| 71 | @ the fault status register in r1. r9 must be preserved. |
| 72 | @ |
| 73 | #ifdef MULTI_DABORT |
| 74 | ldr ip, .LCprocfns |
| 75 | mov lr, pc |
| 76 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
| 77 | #else |
| 78 | bl CPU_DABORT_HANDLER |
| 79 | #endif |
| 80 | .endm |
| 81 | |
| 82 | #ifdef CONFIG_KPROBES |
| 83 | .section .kprobes.text,"ax",%progbits |
| 84 | #else |
| 85 | .text |
| 86 | #endif |
| 87 | |
| 88 | /* |
| 89 | * Invalid mode handlers |
| 90 | */ |
| 91 | .macro inv_entry, reason |
| 92 | sub sp, sp, #S_FRAME_SIZE |
| 93 | ARM( stmib sp, {r1 - lr} ) |
| 94 | THUMB( stmia sp, {r0 - r12} ) |
| 95 | THUMB( str sp, [sp, #S_SP] ) |
| 96 | THUMB( str lr, [sp, #S_LR] ) |
| 97 | mov r1, #\reason |
| 98 | .endm |
| 99 | |
| 100 | __pabt_invalid: |
| 101 | inv_entry BAD_PREFETCH |
| 102 | b common_invalid |
| 103 | ENDPROC(__pabt_invalid) |
| 104 | |
| 105 | __dabt_invalid: |
| 106 | inv_entry BAD_DATA |
| 107 | b common_invalid |
| 108 | ENDPROC(__dabt_invalid) |
| 109 | |
| 110 | __irq_invalid: |
| 111 | inv_entry BAD_IRQ |
| 112 | b common_invalid |
| 113 | ENDPROC(__irq_invalid) |
| 114 | |
| 115 | __und_invalid: |
| 116 | inv_entry BAD_UNDEFINSTR |
| 117 | |
| 118 | @ |
| 119 | @ XXX fall through to common_invalid |
| 120 | @ |
| 121 | |
| 122 | @ |
| 123 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) |
| 124 | @ |
| 125 | common_invalid: |
| 126 | zero_fp |
| 127 | |
| 128 | ldmia r0, {r4 - r6} |
| 129 | add r0, sp, #S_PC @ here for interlock avoidance |
| 130 | mov r7, #-1 @ "" "" "" "" |
| 131 | str r4, [sp] @ save preserved r0 |
| 132 | stmia r0, {r5 - r7} @ lr_<exception>, |
| 133 | @ cpsr_<exception>, "old_r0" |
| 134 | |
| 135 | mov r0, sp |
| 136 | b bad_mode |
| 137 | ENDPROC(__und_invalid) |
| 138 | |
| 139 | /* |
| 140 | * SVC mode handlers |
| 141 | */ |
| 142 | |
| 143 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) |
| 144 | #define SPFIX(code...) code |
| 145 | #else |
| 146 | #define SPFIX(code...) |
| 147 | #endif |
| 148 | |
| 149 | .macro svc_entry, stack_hole=0 |
| 150 | UNWIND(.fnstart ) |
| 151 | UNWIND(.save {r0 - pc} ) |
| 152 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
| 153 | #ifdef CONFIG_THUMB2_KERNEL |
| 154 | SPFIX( str r0, [sp] ) @ temporarily saved |
| 155 | SPFIX( mov r0, sp ) |
| 156 | SPFIX( tst r0, #4 ) @ test original stack alignment |
| 157 | SPFIX( ldr r0, [sp] ) @ restored |
| 158 | #else |
| 159 | SPFIX( tst sp, #4 ) |
| 160 | #endif |
| 161 | SPFIX( subeq sp, sp, #4 ) |
| 162 | stmia sp, {r1 - r12} |
| 163 | |
| 164 | ldmia r0, {r3 - r5} |
| 165 | add r7, sp, #S_SP - 4 @ here for interlock avoidance |
| 166 | mov r6, #-1 @ "" "" "" "" |
| 167 | add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
| 168 | SPFIX( addeq r2, r2, #4 ) |
| 169 | str r3, [sp, #-4]! @ save the "real" r0 copied |
| 170 | @ from the exception stack |
| 171 | |
| 172 | mov r3, lr |
| 173 | |
| 174 | @ |
| 175 | @ We are now ready to fill in the remaining blanks on the stack: |
| 176 | @ |
| 177 | @ r2 - sp_svc |
| 178 | @ r3 - lr_svc |
| 179 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
| 180 | @ r5 - spsr_<exception> |
| 181 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) |
| 182 | @ |
| 183 | stmia r7, {r2 - r6} |
| 184 | |
| 185 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 186 | bl trace_hardirqs_off |
| 187 | #endif |
| 188 | .endm |
| 189 | |
| 190 | .align 5 |
| 191 | __dabt_svc: |
| 192 | svc_entry |
| 193 | mov r2, sp |
| 194 | dabt_helper |
| 195 | THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR |
| 196 | svc_exit r5 @ return from exception |
| 197 | UNWIND(.fnend ) |
| 198 | ENDPROC(__dabt_svc) |
| 199 | |
| 200 | .align 5 |
| 201 | __irq_svc: |
| 202 | svc_entry |
| 203 | irq_handler |
| 204 | |
| 205 | #ifdef CONFIG_PREEMPT |
| 206 | get_thread_info tsk |
| 207 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
| 208 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
| 209 | teq r8, #0 @ if preempt count != 0 |
| 210 | movne r0, #0 @ force flags to 0 |
| 211 | tst r0, #_TIF_NEED_RESCHED |
| 212 | blne svc_preempt |
| 213 | #endif |
| 214 | |
| 215 | svc_exit r5, irq = 1 @ return from exception |
| 216 | UNWIND(.fnend ) |
| 217 | ENDPROC(__irq_svc) |
| 218 | |
| 219 | .ltorg |
| 220 | |
| 221 | #ifdef CONFIG_PREEMPT |
| 222 | svc_preempt: |
| 223 | mov r8, lr |
| 224 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
| 225 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
| 226 | tst r0, #_TIF_NEED_RESCHED |
| 227 | moveq pc, r8 @ go again |
| 228 | b 1b |
| 229 | #endif |
| 230 | |
| 231 | __und_fault: |
| 232 | @ Correct the PC such that it is pointing at the instruction |
| 233 | @ which caused the fault. If the faulting instruction was ARM |
| 234 | @ the PC will be pointing at the next instruction, and have to |
| 235 | @ subtract 4. Otherwise, it is Thumb, and the PC will be |
| 236 | @ pointing at the second half of the Thumb instruction. We |
| 237 | @ have to subtract 2. |
| 238 | ldr r2, [r0, #S_PC] |
| 239 | sub r2, r2, r1 |
| 240 | str r2, [r0, #S_PC] |
| 241 | b do_undefinstr |
| 242 | ENDPROC(__und_fault) |
| 243 | |
| 244 | .align 5 |
| 245 | __und_svc: |
| 246 | #ifdef CONFIG_KPROBES |
| 247 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, |
| 248 | @ it obviously needs free stack space which then will belong to |
| 249 | @ the saved context. |
| 250 | svc_entry 64 |
| 251 | #else |
| 252 | svc_entry |
| 253 | #endif |
| 254 | @ |
| 255 | @ call emulation code, which returns using r9 if it has emulated |
| 256 | @ the instruction, or the more conventional lr if we are to treat |
| 257 | @ this as a real undefined instruction |
| 258 | @ |
| 259 | @ r0 - instruction |
| 260 | @ |
| 261 | #ifndef CONFIG_THUMB2_KERNEL |
| 262 | ldr r0, [r4, #-4] |
| 263 | #else |
| 264 | mov r1, #2 |
| 265 | ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 |
| 266 | cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 |
| 267 | blo __und_svc_fault |
| 268 | ldrh r9, [r4] @ bottom 16 bits |
| 269 | add r4, r4, #2 |
| 270 | str r4, [sp, #S_PC] |
| 271 | orr r0, r9, r0, lsl #16 |
| 272 | #endif |
| 273 | adr r9, BSYM(__und_svc_finish) |
| 274 | mov r2, r4 |
| 275 | bl call_fpe |
| 276 | |
| 277 | mov r1, #4 @ PC correction to apply |
| 278 | __und_svc_fault: |
| 279 | mov r0, sp @ struct pt_regs *regs |
| 280 | bl __und_fault |
| 281 | |
| 282 | __und_svc_finish: |
| 283 | ldr r5, [sp, #S_PSR] @ Get SVC cpsr |
| 284 | svc_exit r5 @ return from exception |
| 285 | UNWIND(.fnend ) |
| 286 | ENDPROC(__und_svc) |
| 287 | |
| 288 | .align 5 |
| 289 | __pabt_svc: |
| 290 | svc_entry |
| 291 | mov r2, sp @ regs |
| 292 | pabt_helper |
| 293 | svc_exit r5 @ return from exception |
| 294 | UNWIND(.fnend ) |
| 295 | ENDPROC(__pabt_svc) |
| 296 | |
| 297 | .align 5 |
| 298 | .LCcralign: |
| 299 | .word cr_alignment |
| 300 | #ifdef MULTI_DABORT |
| 301 | .LCprocfns: |
| 302 | .word processor |
| 303 | #endif |
| 304 | .LCfp: |
| 305 | .word fp_enter |
| 306 | |
| 307 | /* |
| 308 | * User mode handlers |
| 309 | * |
| 310 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE |
| 311 | */ |
| 312 | |
| 313 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) |
| 314 | #error "sizeof(struct pt_regs) must be a multiple of 8" |
| 315 | #endif |
| 316 | |
| 317 | .macro usr_entry |
| 318 | UNWIND(.fnstart ) |
| 319 | UNWIND(.cantunwind ) @ don't unwind the user space |
| 320 | sub sp, sp, #S_FRAME_SIZE |
| 321 | ARM( stmib sp, {r1 - r12} ) |
| 322 | THUMB( stmia sp, {r0 - r12} ) |
| 323 | |
| 324 | ldmia r0, {r3 - r5} |
| 325 | add r0, sp, #S_PC @ here for interlock avoidance |
| 326 | mov r6, #-1 @ "" "" "" "" |
| 327 | |
| 328 | str r3, [sp] @ save the "real" r0 copied |
| 329 | @ from the exception stack |
| 330 | |
| 331 | @ |
| 332 | @ We are now ready to fill in the remaining blanks on the stack: |
| 333 | @ |
| 334 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
| 335 | @ r5 - spsr_<exception> |
| 336 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) |
| 337 | @ |
| 338 | @ Also, separately save sp_usr and lr_usr |
| 339 | @ |
| 340 | stmia r0, {r4 - r6} |
| 341 | ARM( stmdb r0, {sp, lr}^ ) |
| 342 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) |
| 343 | |
| 344 | @ |
| 345 | @ Enable the alignment trap while in kernel mode |
| 346 | @ |
| 347 | alignment_trap r0 |
| 348 | |
| 349 | @ |
| 350 | @ Clear FP to mark the first stack frame |
| 351 | @ |
| 352 | zero_fp |
| 353 | |
| 354 | #ifdef CONFIG_IRQSOFF_TRACER |
| 355 | bl trace_hardirqs_off |
| 356 | #endif |
| 357 | ct_user_exit save = 0 |
| 358 | .endm |
| 359 | |
| 360 | .macro kuser_cmpxchg_check |
| 361 | #if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
| 362 | #ifndef CONFIG_MMU |
| 363 | #warning "NPTL on non MMU needs fixing" |
| 364 | #else |
| 365 | @ Make sure our user space atomic helper is restarted |
| 366 | @ if it was interrupted in a critical region. Here we |
| 367 | @ perform a quick test inline since it should be false |
| 368 | @ 99.9999% of the time. The rest is done out of line. |
| 369 | cmp r4, #TASK_SIZE |
| 370 | blhs kuser_cmpxchg64_fixup |
| 371 | #endif |
| 372 | #endif |
| 373 | .endm |
| 374 | |
| 375 | .align 5 |
| 376 | __dabt_usr: |
| 377 | usr_entry |
| 378 | kuser_cmpxchg_check |
| 379 | mov r2, sp |
| 380 | dabt_helper |
| 381 | b ret_from_exception |
| 382 | UNWIND(.fnend ) |
| 383 | ENDPROC(__dabt_usr) |
| 384 | |
| 385 | .align 5 |
| 386 | __irq_usr: |
| 387 | usr_entry |
| 388 | kuser_cmpxchg_check |
| 389 | irq_handler |
| 390 | get_thread_info tsk |
| 391 | mov why, #0 |
| 392 | b ret_to_user_from_irq |
| 393 | UNWIND(.fnend ) |
| 394 | ENDPROC(__irq_usr) |
| 395 | |
| 396 | .ltorg |
| 397 | |
| 398 | .align 5 |
| 399 | __und_usr: |
| 400 | usr_entry |
| 401 | |
| 402 | mov r2, r4 |
| 403 | mov r3, r5 |
| 404 | |
| 405 | @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the |
| 406 | @ faulting instruction depending on Thumb mode. |
| 407 | @ r3 = regs->ARM_cpsr |
| 408 | @ |
| 409 | @ The emulation code returns using r9 if it has emulated the |
| 410 | @ instruction, or the more conventional lr if we are to treat |
| 411 | @ this as a real undefined instruction |
| 412 | @ |
| 413 | adr r9, BSYM(ret_from_exception) |
| 414 | |
| 415 | tst r3, #PSR_T_BIT @ Thumb mode? |
| 416 | bne __und_usr_thumb |
| 417 | sub r4, r2, #4 @ ARM instr at LR - 4 |
| 418 | 1: ldrt r0, [r4] |
| 419 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
| 420 | rev r0, r0 @ little endian instruction |
| 421 | #endif |
| 422 | @ r0 = 32-bit ARM instruction which caused the exception |
| 423 | @ r2 = PC value for the following instruction (:= regs->ARM_pc) |
| 424 | @ r4 = PC value for the faulting instruction |
| 425 | @ lr = 32-bit undefined instruction function |
| 426 | adr lr, BSYM(__und_usr_fault_32) |
| 427 | b call_fpe |
| 428 | |
| 429 | __und_usr_thumb: |
| 430 | @ Thumb instruction |
| 431 | sub r4, r2, #2 @ First half of thumb instr at LR - 2 |
| 432 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
| 433 | /* |
| 434 | * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms |
| 435 | * can never be supported in a single kernel, this code is not applicable at |
| 436 | * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be |
| 437 | * made about .arch directives. |
| 438 | */ |
| 439 | #if __LINUX_ARM_ARCH__ < 7 |
| 440 | /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ |
| 441 | #define NEED_CPU_ARCHITECTURE |
| 442 | ldr r5, .LCcpu_architecture |
| 443 | ldr r5, [r5] |
| 444 | cmp r5, #CPU_ARCH_ARMv7 |
| 445 | blo __und_usr_fault_16 @ 16bit undefined instruction |
| 446 | /* |
| 447 | * The following code won't get run unless the running CPU really is v7, so |
| 448 | * coding round the lack of ldrht on older arches is pointless. Temporarily |
| 449 | * override the assembler target arch with the minimum required instead: |
| 450 | */ |
| 451 | .arch armv6t2 |
| 452 | #endif |
| 453 | 2: ldrht r5, [r4] |
| 454 | cmp r5, #0xe800 @ 32bit instruction if xx != 0 |
| 455 | blo __und_usr_fault_16 @ 16bit undefined instruction |
| 456 | 3: ldrht r0, [r2] |
| 457 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 |
| 458 | str r2, [sp, #S_PC] @ it's a 2x16bit instr, update |
| 459 | orr r0, r0, r5, lsl #16 |
| 460 | adr lr, BSYM(__und_usr_fault_32) |
| 461 | @ r0 = the two 16-bit Thumb instructions which caused the exception |
| 462 | @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) |
| 463 | @ r4 = PC value for the first 16-bit Thumb instruction |
| 464 | @ lr = 32bit undefined instruction function |
| 465 | |
| 466 | #if __LINUX_ARM_ARCH__ < 7 |
| 467 | /* If the target arch was overridden, change it back: */ |
| 468 | #ifdef CONFIG_CPU_32v6K |
| 469 | .arch armv6k |
| 470 | #else |
| 471 | .arch armv6 |
| 472 | #endif |
| 473 | #endif /* __LINUX_ARM_ARCH__ < 7 */ |
| 474 | #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ |
| 475 | b __und_usr_fault_16 |
| 476 | #endif |
| 477 | UNWIND(.fnend) |
| 478 | ENDPROC(__und_usr) |
| 479 | |
| 480 | /* |
| 481 | * The out of line fixup for the ldrt instructions above. |
| 482 | */ |
| 483 | .pushsection .fixup, "ax" |
| 484 | .align 2 |
| 485 | 4: mov pc, r9 |
| 486 | .popsection |
| 487 | .pushsection __ex_table,"a" |
| 488 | .long 1b, 4b |
| 489 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
| 490 | .long 2b, 4b |
| 491 | .long 3b, 4b |
| 492 | #endif |
| 493 | .popsection |
| 494 | |
| 495 | /* |
| 496 | * Check whether the instruction is a co-processor instruction. |
| 497 | * If yes, we need to call the relevant co-processor handler. |
| 498 | * |
| 499 | * Note that we don't do a full check here for the co-processor |
| 500 | * instructions; all instructions with bit 27 set are well |
| 501 | * defined. The only instructions that should fault are the |
| 502 | * co-processor instructions. However, we have to watch out |
| 503 | * for the ARM6/ARM7 SWI bug. |
| 504 | * |
| 505 | * NEON is a special case that has to be handled here. Not all |
| 506 | * NEON instructions are co-processor instructions, so we have |
| 507 | * to make a special case of checking for them. Plus, there's |
| 508 | * five groups of them, so we have a table of mask/opcode pairs |
| 509 | * to check against, and if any match then we branch off into the |
| 510 | * NEON handler code. |
| 511 | * |
| 512 | * Emulators may wish to make use of the following registers: |
| 513 | * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) |
| 514 | * r2 = PC value to resume execution after successful emulation |
| 515 | * r9 = normal "successful" return address |
| 516 | * r10 = this threads thread_info structure |
| 517 | * lr = unrecognised instruction return address |
| 518 | * IRQs disabled, FIQs enabled. |
| 519 | */ |
| 520 | @ |
| 521 | @ Fall-through from Thumb-2 __und_usr |
| 522 | @ |
| 523 | #ifdef CONFIG_NEON |
| 524 | get_thread_info r10 @ get current thread |
| 525 | adr r6, .LCneon_thumb_opcodes |
| 526 | b 2f |
| 527 | #endif |
| 528 | call_fpe: |
| 529 | get_thread_info r10 @ get current thread |
| 530 | #ifdef CONFIG_NEON |
| 531 | adr r6, .LCneon_arm_opcodes |
| 532 | 2: ldr r5, [r6], #4 @ mask value |
| 533 | ldr r7, [r6], #4 @ opcode bits matching in mask |
| 534 | cmp r5, #0 @ end mask? |
| 535 | beq 1f |
| 536 | and r8, r0, r5 |
| 537 | cmp r8, r7 @ NEON instruction? |
| 538 | bne 2b |
| 539 | mov r7, #1 |
| 540 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used |
| 541 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used |
| 542 | b do_vfp @ let VFP handler handle this |
| 543 | 1: |
| 544 | #endif |
| 545 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
| 546 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
| 547 | moveq pc, lr |
| 548 | and r8, r0, #0x00000f00 @ mask out CP number |
| 549 | THUMB( lsr r8, r8, #8 ) |
| 550 | mov r7, #1 |
| 551 | add r6, r10, #TI_USED_CP |
| 552 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
| 553 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] |
| 554 | #ifdef CONFIG_IWMMXT |
| 555 | @ Test if we need to give access to iWMMXt coprocessors |
| 556 | ldr r5, [r10, #TI_FLAGS] |
| 557 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only |
| 558 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) |
| 559 | bcs iwmmxt_task_enable |
| 560 | #endif |
| 561 | ARM( add pc, pc, r8, lsr #6 ) |
| 562 | THUMB( lsl r8, r8, #2 ) |
| 563 | THUMB( add pc, r8 ) |
| 564 | nop |
| 565 | |
| 566 | movw_pc lr @ CP#0 |
| 567 | W(b) do_fpe @ CP#1 (FPE) |
| 568 | W(b) do_fpe @ CP#2 (FPE) |
| 569 | movw_pc lr @ CP#3 |
| 570 | #ifdef CONFIG_CRUNCH |
| 571 | b crunch_task_enable @ CP#4 (MaverickCrunch) |
| 572 | b crunch_task_enable @ CP#5 (MaverickCrunch) |
| 573 | b crunch_task_enable @ CP#6 (MaverickCrunch) |
| 574 | #else |
| 575 | movw_pc lr @ CP#4 |
| 576 | movw_pc lr @ CP#5 |
| 577 | movw_pc lr @ CP#6 |
| 578 | #endif |
| 579 | movw_pc lr @ CP#7 |
| 580 | movw_pc lr @ CP#8 |
| 581 | movw_pc lr @ CP#9 |
| 582 | #ifdef CONFIG_VFP |
| 583 | W(b) do_vfp @ CP#10 (VFP) |
| 584 | W(b) do_vfp @ CP#11 (VFP) |
| 585 | #else |
| 586 | movw_pc lr @ CP#10 (VFP) |
| 587 | movw_pc lr @ CP#11 (VFP) |
| 588 | #endif |
| 589 | movw_pc lr @ CP#12 |
| 590 | movw_pc lr @ CP#13 |
| 591 | movw_pc lr @ CP#14 (Debug) |
| 592 | movw_pc lr @ CP#15 (Control) |
| 593 | |
| 594 | #ifdef NEED_CPU_ARCHITECTURE |
| 595 | .align 2 |
| 596 | .LCcpu_architecture: |
| 597 | .word __cpu_architecture |
| 598 | #endif |
| 599 | |
| 600 | #ifdef CONFIG_NEON |
| 601 | .align 6 |
| 602 | |
| 603 | .LCneon_arm_opcodes: |
| 604 | .word 0xfe000000 @ mask |
| 605 | .word 0xf2000000 @ opcode |
| 606 | |
| 607 | .word 0xff100000 @ mask |
| 608 | .word 0xf4000000 @ opcode |
| 609 | |
| 610 | .word 0x00000000 @ mask |
| 611 | .word 0x00000000 @ opcode |
| 612 | |
| 613 | .LCneon_thumb_opcodes: |
| 614 | .word 0xef000000 @ mask |
| 615 | .word 0xef000000 @ opcode |
| 616 | |
| 617 | .word 0xff100000 @ mask |
| 618 | .word 0xf9000000 @ opcode |
| 619 | |
| 620 | .word 0x00000000 @ mask |
| 621 | .word 0x00000000 @ opcode |
| 622 | #endif |
| 623 | |
| 624 | do_fpe: |
| 625 | enable_irq |
| 626 | ldr r4, .LCfp |
| 627 | add r10, r10, #TI_FPSTATE @ r10 = workspace |
| 628 | ldr pc, [r4] @ Call FP module USR entry point |
| 629 | |
| 630 | /* |
| 631 | * The FP module is called with these registers set: |
| 632 | * r0 = instruction |
| 633 | * r2 = PC+4 |
| 634 | * r9 = normal "successful" return address |
| 635 | * r10 = FP workspace |
| 636 | * lr = unrecognised FP instruction return address |
| 637 | */ |
| 638 | |
| 639 | .pushsection .data |
| 640 | ENTRY(fp_enter) |
| 641 | .word no_fp |
| 642 | .popsection |
| 643 | |
| 644 | ENTRY(no_fp) |
| 645 | mov pc, lr |
| 646 | ENDPROC(no_fp) |
| 647 | |
| 648 | __und_usr_fault_32: |
| 649 | mov r1, #4 |
| 650 | b 1f |
| 651 | __und_usr_fault_16: |
| 652 | mov r1, #2 |
| 653 | 1: enable_irq |
| 654 | mov r0, sp |
| 655 | adr lr, BSYM(ret_from_exception) |
| 656 | b __und_fault |
| 657 | ENDPROC(__und_usr_fault_32) |
| 658 | ENDPROC(__und_usr_fault_16) |
| 659 | |
| 660 | .align 5 |
| 661 | __pabt_usr: |
| 662 | usr_entry |
| 663 | mov r2, sp @ regs |
| 664 | pabt_helper |
| 665 | UNWIND(.fnend ) |
| 666 | /* fall through */ |
| 667 | /* |
| 668 | * This is the return code to user mode for abort handlers |
| 669 | */ |
| 670 | ENTRY(ret_from_exception) |
| 671 | UNWIND(.fnstart ) |
| 672 | UNWIND(.cantunwind ) |
| 673 | get_thread_info tsk |
| 674 | mov why, #0 |
| 675 | b ret_to_user |
| 676 | UNWIND(.fnend ) |
| 677 | ENDPROC(__pabt_usr) |
| 678 | ENDPROC(ret_from_exception) |
| 679 | |
| 680 | /* |
| 681 | * Register switch for ARMv3 and ARMv4 processors |
| 682 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info |
| 683 | * previous and next are guaranteed not to be the same. |
| 684 | */ |
| 685 | ENTRY(__switch_to) |
| 686 | UNWIND(.fnstart ) |
| 687 | UNWIND(.cantunwind ) |
| 688 | #ifdef CONFIG_VFP_OPT |
| 689 | add ip, r1, #TI_CPU_SAVE |
| 690 | stmfa ip!, {r0, r1, r2, r5, r6, r8, lr} |
| 691 | |
| 692 | @1. save vfp state for previous thread_info |
| 693 | mov r0, r1 |
| 694 | add r0, r0, #TI_VFPSTATE @ r0 = workspace |
| 695 | VFPFMRX r1, FPEXC |
| 696 | mov r5, ip @ save ip to r5, because vfp_save_state may change ip |
| 697 | mov r6, r2 @ save r2 to r6, because vfp_save_state may change r2 |
| 698 | bl vfp_save_state |
| 699 | mov ip, r5 |
| 700 | mov r2, r6 |
| 701 | |
| 702 | @ 2. restore vfp state from next thread_info |
| 703 | add r2, r2, #TI_VFPSTATE @ r2 = workspace |
| 704 | VFPFLDMIA r2, r0 @ reload the working registers while |
| 705 | @ FPEXC is in a safe state |
| 706 | ldmia r2, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 |
| 707 | VFPFMXR FPSCR, r5 @ restore status |
| 708 | ldmfa ip!, {r0, r1, r2, r5, r6, r8, lr} |
| 709 | #endif |
| 710 | add ip, r1, #TI_CPU_SAVE |
| 711 | ldr r3, [r2, #TI_TP_VALUE] |
| 712 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
| 713 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack |
| 714 | THUMB( str sp, [ip], #4 ) |
| 715 | THUMB( str lr, [ip], #4 ) |
| 716 | #ifdef CONFIG_CPU_USE_DOMAINS |
| 717 | ldr r6, [r2, #TI_CPU_DOMAIN] |
| 718 | #endif |
| 719 | set_tls r3, r4, r5 |
| 720 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
| 721 | ldr r7, [r2, #TI_TASK] |
| 722 | ldr r8, =__stack_chk_guard |
| 723 | ldr r7, [r7, #TSK_STACK_CANARY] |
| 724 | #endif |
| 725 | #ifdef CONFIG_CPU_USE_DOMAINS |
| 726 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
| 727 | #endif |
| 728 | mov r5, r0 |
| 729 | add r4, r2, #TI_CPU_SAVE |
| 730 | ldr r0, =thread_notify_head |
| 731 | mov r1, #THREAD_NOTIFY_SWITCH |
| 732 | bl atomic_notifier_call_chain |
| 733 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
| 734 | str r7, [r8] |
| 735 | #endif |
| 736 | THUMB( mov ip, r4 ) |
| 737 | mov r0, r5 |
| 738 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
| 739 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously |
| 740 | THUMB( ldr sp, [ip], #4 ) |
| 741 | THUMB( ldr pc, [ip] ) |
| 742 | UNWIND(.fnend ) |
| 743 | ENDPROC(__switch_to) |
| 744 | |
| 745 | __INIT |
| 746 | |
| 747 | /* |
| 748 | * User helpers. |
| 749 | * |
| 750 | * Each segment is 32-byte aligned and will be moved to the top of the high |
| 751 | * vector page. New segments (if ever needed) must be added in front of |
| 752 | * existing ones. This mechanism should be used only for things that are |
| 753 | * really small and justified, and not be abused freely. |
| 754 | * |
| 755 | * See Documentation/arm/kernel_user_helpers.txt for formal definitions. |
| 756 | */ |
| 757 | THUMB( .arm ) |
| 758 | |
| 759 | .macro usr_ret, reg |
| 760 | #ifdef CONFIG_ARM_THUMB |
| 761 | bx \reg |
| 762 | #else |
| 763 | mov pc, \reg |
| 764 | #endif |
| 765 | .endm |
| 766 | |
| 767 | .macro kuser_pad, sym, size |
| 768 | .if (. - \sym) & 3 |
| 769 | .rept 4 - (. - \sym) & 3 |
| 770 | .byte 0 |
| 771 | .endr |
| 772 | .endif |
| 773 | .rept (\size - (. - \sym)) / 4 |
| 774 | .word 0xe7fddef1 |
| 775 | .endr |
| 776 | .endm |
| 777 | |
| 778 | #ifdef CONFIG_KUSER_HELPERS |
| 779 | .align 5 |
| 780 | .globl __kuser_helper_start |
| 781 | __kuser_helper_start: |
| 782 | |
| 783 | /* |
| 784 | * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular |
| 785 | * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. |
| 786 | */ |
| 787 | |
| 788 | __kuser_cmpxchg64: @ 0xffff0f60 |
| 789 | |
| 790 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
| 791 | |
| 792 | /* |
| 793 | * Poor you. No fast solution possible... |
| 794 | * The kernel itself must perform the operation. |
| 795 | * A special ghost syscall is used for that (see traps.c). |
| 796 | */ |
| 797 | stmfd sp!, {r7, lr} |
| 798 | ldr r7, 1f @ it's 20 bits |
| 799 | swi __ARM_NR_cmpxchg64 |
| 800 | ldmfd sp!, {r7, pc} |
| 801 | 1: .word __ARM_NR_cmpxchg64 |
| 802 | |
| 803 | #elif defined(CONFIG_CPU_32v6K) |
| 804 | |
| 805 | stmfd sp!, {r4, r5, r6, r7} |
| 806 | ldrd r4, r5, [r0] @ load old val |
| 807 | ldrd r6, r7, [r1] @ load new val |
| 808 | smp_dmb arm |
| 809 | 1: ldrexd r0, r1, [r2] @ load current val |
| 810 | eors r3, r0, r4 @ compare with oldval (1) |
| 811 | eoreqs r3, r1, r5 @ compare with oldval (2) |
| 812 | strexdeq r3, r6, r7, [r2] @ store newval if eq |
| 813 | teqeq r3, #1 @ success? |
| 814 | beq 1b @ if no then retry |
| 815 | smp_dmb arm |
| 816 | rsbs r0, r3, #0 @ set returned val and C flag |
| 817 | ldmfd sp!, {r4, r5, r6, r7} |
| 818 | usr_ret lr |
| 819 | |
| 820 | #elif !defined(CONFIG_SMP) |
| 821 | |
| 822 | #ifdef CONFIG_MMU |
| 823 | |
| 824 | /* |
| 825 | * The only thing that can break atomicity in this cmpxchg64 |
| 826 | * implementation is either an IRQ or a data abort exception |
| 827 | * causing another process/thread to be scheduled in the middle of |
| 828 | * the critical sequence. The same strategy as for cmpxchg is used. |
| 829 | */ |
| 830 | stmfd sp!, {r4, r5, r6, lr} |
| 831 | ldmia r0, {r4, r5} @ load old val |
| 832 | ldmia r1, {r6, lr} @ load new val |
| 833 | 1: ldmia r2, {r0, r1} @ load current val |
| 834 | eors r3, r0, r4 @ compare with oldval (1) |
| 835 | eoreqs r3, r1, r5 @ compare with oldval (2) |
| 836 | 2: stmeqia r2, {r6, lr} @ store newval if eq |
| 837 | rsbs r0, r3, #0 @ set return val and C flag |
| 838 | ldmfd sp!, {r4, r5, r6, pc} |
| 839 | |
| 840 | .text |
| 841 | kuser_cmpxchg64_fixup: |
| 842 | @ Called from kuser_cmpxchg_fixup. |
| 843 | @ r4 = address of interrupted insn (must be preserved). |
| 844 | @ sp = saved regs. r7 and r8 are clobbered. |
| 845 | @ 1b = first critical insn, 2b = last critical insn. |
| 846 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
| 847 | mov r7, #0xffff0fff |
| 848 | sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) |
| 849 | subs r8, r4, r7 |
| 850 | rsbcss r8, r8, #(2b - 1b) |
| 851 | strcs r7, [sp, #S_PC] |
| 852 | #if __LINUX_ARM_ARCH__ < 6 |
| 853 | bcc kuser_cmpxchg32_fixup |
| 854 | #endif |
| 855 | mov pc, lr |
| 856 | .previous |
| 857 | |
| 858 | #else |
| 859 | #warning "NPTL on non MMU needs fixing" |
| 860 | mov r0, #-1 |
| 861 | adds r0, r0, #0 |
| 862 | usr_ret lr |
| 863 | #endif |
| 864 | |
| 865 | #else |
| 866 | #error "incoherent kernel configuration" |
| 867 | #endif |
| 868 | |
| 869 | kuser_pad __kuser_cmpxchg64, 64 |
| 870 | |
| 871 | __kuser_memory_barrier: @ 0xffff0fa0 |
| 872 | smp_dmb arm |
| 873 | usr_ret lr |
| 874 | |
| 875 | kuser_pad __kuser_memory_barrier, 32 |
| 876 | |
| 877 | __kuser_cmpxchg: @ 0xffff0fc0 |
| 878 | |
| 879 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
| 880 | |
| 881 | /* |
| 882 | * Poor you. No fast solution possible... |
| 883 | * The kernel itself must perform the operation. |
| 884 | * A special ghost syscall is used for that (see traps.c). |
| 885 | */ |
| 886 | stmfd sp!, {r7, lr} |
| 887 | ldr r7, 1f @ it's 20 bits |
| 888 | swi __ARM_NR_cmpxchg |
| 889 | ldmfd sp!, {r7, pc} |
| 890 | 1: .word __ARM_NR_cmpxchg |
| 891 | |
| 892 | #elif __LINUX_ARM_ARCH__ < 6 |
| 893 | |
| 894 | #ifdef CONFIG_MMU |
| 895 | |
| 896 | /* |
| 897 | * The only thing that can break atomicity in this cmpxchg |
| 898 | * implementation is either an IRQ or a data abort exception |
| 899 | * causing another process/thread to be scheduled in the middle |
| 900 | * of the critical sequence. To prevent this, code is added to |
| 901 | * the IRQ and data abort exception handlers to set the pc back |
| 902 | * to the beginning of the critical section if it is found to be |
| 903 | * within that critical section (see kuser_cmpxchg_fixup). |
| 904 | */ |
| 905 | 1: ldr r3, [r2] @ load current val |
| 906 | subs r3, r3, r0 @ compare with oldval |
| 907 | 2: streq r1, [r2] @ store newval if eq |
| 908 | rsbs r0, r3, #0 @ set return val and C flag |
| 909 | usr_ret lr |
| 910 | |
| 911 | .text |
| 912 | kuser_cmpxchg32_fixup: |
| 913 | @ Called from kuser_cmpxchg_check macro. |
| 914 | @ r4 = address of interrupted insn (must be preserved). |
| 915 | @ sp = saved regs. r7 and r8 are clobbered. |
| 916 | @ 1b = first critical insn, 2b = last critical insn. |
| 917 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
| 918 | mov r7, #0xffff0fff |
| 919 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) |
| 920 | subs r8, r4, r7 |
| 921 | rsbcss r8, r8, #(2b - 1b) |
| 922 | strcs r7, [sp, #S_PC] |
| 923 | mov pc, lr |
| 924 | .previous |
| 925 | |
| 926 | #else |
| 927 | #warning "NPTL on non MMU needs fixing" |
| 928 | mov r0, #-1 |
| 929 | adds r0, r0, #0 |
| 930 | usr_ret lr |
| 931 | #endif |
| 932 | |
| 933 | #else |
| 934 | |
| 935 | smp_dmb arm |
| 936 | 1: ldrex r3, [r2] |
| 937 | subs r3, r3, r0 |
| 938 | strexeq r3, r1, [r2] |
| 939 | teqeq r3, #1 |
| 940 | beq 1b |
| 941 | rsbs r0, r3, #0 |
| 942 | /* beware -- each __kuser slot must be 8 instructions max */ |
| 943 | ALT_SMP(b __kuser_memory_barrier) |
| 944 | ALT_UP(usr_ret lr) |
| 945 | |
| 946 | #endif |
| 947 | |
| 948 | kuser_pad __kuser_cmpxchg, 32 |
| 949 | |
| 950 | __kuser_get_tls: @ 0xffff0fe0 |
| 951 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
| 952 | usr_ret lr |
| 953 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
| 954 | kuser_pad __kuser_get_tls, 16 |
| 955 | .rep 3 |
| 956 | .word 0 @ 0xffff0ff0 software TLS value, then |
| 957 | .endr @ pad up to __kuser_helper_version |
| 958 | |
| 959 | __kuser_helper_version: @ 0xffff0ffc |
| 960 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) |
| 961 | |
| 962 | .globl __kuser_helper_end |
| 963 | __kuser_helper_end: |
| 964 | |
| 965 | #endif |
| 966 | |
| 967 | THUMB( .thumb ) |
| 968 | |
| 969 | /* |
| 970 | * Vector stubs. |
| 971 | * |
| 972 | * This code is copied to 0xffff1000 so we can use branches in the |
| 973 | * vectors, rather than ldr's. Note that this code must not exceed |
| 974 | * a page size. |
| 975 | * |
| 976 | * Common stub entry macro: |
| 977 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC |
| 978 | * |
| 979 | * SP points to a minimal amount of processor-private memory, the address |
| 980 | * of which is copied into r0 for the mode specific abort handler. |
| 981 | */ |
| 982 | .macro vector_stub, name, mode, correction=0 |
| 983 | .align 5 |
| 984 | |
| 985 | vector_\name: |
| 986 | .if \correction |
| 987 | sub lr, lr, #\correction |
| 988 | .endif |
| 989 | |
| 990 | @ |
| 991 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> |
| 992 | @ (parent CPSR) |
| 993 | @ |
| 994 | stmia sp, {r0, lr} @ save r0, lr |
| 995 | mrs lr, spsr |
| 996 | str lr, [sp, #8] @ save spsr |
| 997 | |
| 998 | @ |
| 999 | @ Prepare for SVC32 mode. IRQs remain disabled. |
| 1000 | @ |
| 1001 | mrs r0, cpsr |
| 1002 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
| 1003 | msr spsr_cxsf, r0 |
| 1004 | |
| 1005 | @ |
| 1006 | @ the branch table must immediately follow this code |
| 1007 | @ |
| 1008 | and lr, lr, #0x0f |
| 1009 | THUMB( adr r0, 1f ) |
| 1010 | THUMB( ldr lr, [r0, lr, lsl #2] ) |
| 1011 | mov r0, sp |
| 1012 | ARM( ldr lr, [pc, lr, lsl #2] ) |
| 1013 | movs pc, lr @ branch to handler in SVC mode |
| 1014 | ENDPROC(vector_\name) |
| 1015 | |
| 1016 | .align 2 |
| 1017 | @ handler addresses follow this label |
| 1018 | 1: |
| 1019 | .endm |
| 1020 | |
| 1021 | .section .stubs, "ax", %progbits |
| 1022 | __stubs_start: |
| 1023 | @ This must be the first word |
| 1024 | .word vector_swi |
| 1025 | |
| 1026 | vector_rst: |
| 1027 | ARM( swi SYS_ERROR0 ) |
| 1028 | THUMB( svc #0 ) |
| 1029 | THUMB( nop ) |
| 1030 | b vector_und |
| 1031 | |
| 1032 | /* |
| 1033 | * Interrupt dispatcher |
| 1034 | */ |
| 1035 | vector_stub irq, IRQ_MODE, 4 |
| 1036 | |
| 1037 | .long __irq_usr @ 0 (USR_26 / USR_32) |
| 1038 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) |
| 1039 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) |
| 1040 | .long __irq_svc @ 3 (SVC_26 / SVC_32) |
| 1041 | .long __irq_invalid @ 4 |
| 1042 | .long __irq_invalid @ 5 |
| 1043 | .long __irq_invalid @ 6 |
| 1044 | .long __irq_invalid @ 7 |
| 1045 | .long __irq_invalid @ 8 |
| 1046 | .long __irq_invalid @ 9 |
| 1047 | .long __irq_invalid @ a |
| 1048 | .long __irq_invalid @ b |
| 1049 | .long __irq_invalid @ c |
| 1050 | .long __irq_invalid @ d |
| 1051 | .long __irq_invalid @ e |
| 1052 | .long __irq_invalid @ f |
| 1053 | |
| 1054 | /* |
| 1055 | * Data abort dispatcher |
| 1056 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC |
| 1057 | */ |
| 1058 | vector_stub dabt, ABT_MODE, 8 |
| 1059 | |
| 1060 | .long __dabt_usr @ 0 (USR_26 / USR_32) |
| 1061 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) |
| 1062 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) |
| 1063 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) |
| 1064 | .long __dabt_invalid @ 4 |
| 1065 | .long __dabt_invalid @ 5 |
| 1066 | .long __dabt_invalid @ 6 |
| 1067 | .long __dabt_invalid @ 7 |
| 1068 | .long __dabt_invalid @ 8 |
| 1069 | .long __dabt_invalid @ 9 |
| 1070 | .long __dabt_invalid @ a |
| 1071 | .long __dabt_invalid @ b |
| 1072 | .long __dabt_invalid @ c |
| 1073 | .long __dabt_invalid @ d |
| 1074 | .long __dabt_invalid @ e |
| 1075 | .long __dabt_invalid @ f |
| 1076 | |
| 1077 | /* |
| 1078 | * Prefetch abort dispatcher |
| 1079 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC |
| 1080 | */ |
| 1081 | vector_stub pabt, ABT_MODE, 4 |
| 1082 | |
| 1083 | .long __pabt_usr @ 0 (USR_26 / USR_32) |
| 1084 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) |
| 1085 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) |
| 1086 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) |
| 1087 | .long __pabt_invalid @ 4 |
| 1088 | .long __pabt_invalid @ 5 |
| 1089 | .long __pabt_invalid @ 6 |
| 1090 | .long __pabt_invalid @ 7 |
| 1091 | .long __pabt_invalid @ 8 |
| 1092 | .long __pabt_invalid @ 9 |
| 1093 | .long __pabt_invalid @ a |
| 1094 | .long __pabt_invalid @ b |
| 1095 | .long __pabt_invalid @ c |
| 1096 | .long __pabt_invalid @ d |
| 1097 | .long __pabt_invalid @ e |
| 1098 | .long __pabt_invalid @ f |
| 1099 | |
| 1100 | /* |
| 1101 | * Undef instr entry dispatcher |
| 1102 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC |
| 1103 | */ |
| 1104 | vector_stub und, UND_MODE |
| 1105 | |
| 1106 | .long __und_usr @ 0 (USR_26 / USR_32) |
| 1107 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) |
| 1108 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) |
| 1109 | .long __und_svc @ 3 (SVC_26 / SVC_32) |
| 1110 | .long __und_invalid @ 4 |
| 1111 | .long __und_invalid @ 5 |
| 1112 | .long __und_invalid @ 6 |
| 1113 | .long __und_invalid @ 7 |
| 1114 | .long __und_invalid @ 8 |
| 1115 | .long __und_invalid @ 9 |
| 1116 | .long __und_invalid @ a |
| 1117 | .long __und_invalid @ b |
| 1118 | .long __und_invalid @ c |
| 1119 | .long __und_invalid @ d |
| 1120 | .long __und_invalid @ e |
| 1121 | .long __und_invalid @ f |
| 1122 | |
| 1123 | .align 5 |
| 1124 | |
| 1125 | /*============================================================================= |
| 1126 | * Address exception handler |
| 1127 | *----------------------------------------------------------------------------- |
| 1128 | * These aren't too critical. |
| 1129 | * (they're not supposed to happen, and won't happen in 32-bit data mode). |
| 1130 | */ |
| 1131 | |
| 1132 | vector_addrexcptn: |
| 1133 | b vector_addrexcptn |
| 1134 | |
| 1135 | /*============================================================================= |
| 1136 | * Undefined FIQs |
| 1137 | *----------------------------------------------------------------------------- |
| 1138 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC |
| 1139 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. |
| 1140 | * Basically to switch modes, we *HAVE* to clobber one register... brain |
| 1141 | * damage alert! I don't think that we can execute any code in here in any |
| 1142 | * other mode than FIQ... Ok you can switch to another mode, but you can't |
| 1143 | * get out of that mode without clobbering one register. |
| 1144 | */ |
| 1145 | vector_fiq: |
| 1146 | subs pc, lr, #4 |
| 1147 | |
| 1148 | .globl vector_fiq_offset |
| 1149 | .equ vector_fiq_offset, vector_fiq |
| 1150 | |
| 1151 | .section .vectors, "ax", %progbits |
| 1152 | __vectors_start: |
| 1153 | W(b) vector_rst |
| 1154 | W(b) vector_und |
| 1155 | W(ldr) pc, __vectors_start + 0x1000 |
| 1156 | W(b) vector_pabt |
| 1157 | W(b) vector_dabt |
| 1158 | W(b) vector_addrexcptn |
| 1159 | W(b) vector_irq |
| 1160 | W(b) vector_fiq |
| 1161 | |
| 1162 | .data |
| 1163 | |
| 1164 | .globl cr_alignment |
| 1165 | .globl cr_no_alignment |
| 1166 | cr_alignment: |
| 1167 | .space 4 |
| 1168 | cr_no_alignment: |
| 1169 | .space 4 |
| 1170 | |
| 1171 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
| 1172 | .globl handle_arch_irq |
| 1173 | handle_arch_irq: |
| 1174 | .space 4 |
| 1175 | #endif |