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Merge tag 'v3.10.96' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / sparc / cs4231.c
CommitLineData
1da177e4
LT		 1/*
2 * Driver for CS4231 sound chips found on Sparcs.
ae251031 3 * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
1da177e4
LT		 4 *
5 * Based entirely upon drivers/sbus/audio/cs4231.c which is:
9e9abb4f 6 * Copyright (C) 1996, 1997, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
1da177e4 7 * and also sound/isa/cs423x/cs4231_lib.c which is:
c1017a4c 8 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 9 */
10
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/kernel.h>
1da177e4
LT		 13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/moduleparam.h>
9e9abb4f
KH		 17#include <linux/irq.h>
18#include <linux/io.h>
ae251031
DM		 19#include <linux/of.h>
20#include <linux/of_device.h>
1da177e4 21
1da177e4
LT		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/info.h>
25#include <sound/control.h>
26#include <sound/timer.h>
27#include <sound/initval.h>
28#include <sound/pcm_params.h>
29
1da177e4
LT		 30#ifdef CONFIG_SBUS
31#define SBUS_SUPPORT
1da177e4
LT		 32#endif
33
34#if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
35#define EBUS_SUPPORT
1da177e4 36#include <linux/pci.h>
aae7fb87 37#include <asm/ebus_dma.h>
1da177e4
LT		 38#endif
39
40static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
41static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
9e9abb4f 42/* Enable this card */
a67ff6a5 43static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
1da177e4
LT		 44
45module_param_array(index, int, NULL, 0444);
46MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
47module_param_array(id, charp, NULL, 0444);
48MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
49module_param_array(enable, bool, NULL, 0444);
50MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
51MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
52MODULE_DESCRIPTION("Sun CS4231");
53MODULE_LICENSE("GPL");
54MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
55
5a820fa7 56#ifdef SBUS_SUPPORT
be9b7e8c 57struct sbus_dma_info {
9e9abb4f
KH		 58 spinlock_t lock; /* DMA access lock */
59 int dir;
60 void __iomem *regs;
be9b7e8c 61};
5a820fa7
GC		 62#endif
63
4f3f2f6f 64struct snd_cs4231;
be9b7e8c 65struct cs4231_dma_control {
9e9abb4f
KH		 66 void (*prepare)(struct cs4231_dma_control *dma_cont,
67 int dir);
68 void (*enable)(struct cs4231_dma_control *dma_cont, int on);
69 int (*request)(struct cs4231_dma_control *dma_cont,
70 dma_addr_t bus_addr, size_t len);
71 unsigned int (*address)(struct cs4231_dma_control *dma_cont);
1da177e4 72#ifdef EBUS_SUPPORT
b128254f 73 struct ebus_dma_info ebus_info;
1da177e4 74#endif
5a820fa7 75#ifdef SBUS_SUPPORT
b128254f 76 struct sbus_dma_info sbus_info;
5a820fa7 77#endif
be9b7e8c 78};
b128254f
GC		 79
80struct snd_cs4231 {
9e9abb4f 81 spinlock_t lock; /* registers access lock */
b128254f
GC		 82 void __iomem *port;
83
be9b7e8c
TI		 84 struct cs4231_dma_control p_dma;
85 struct cs4231_dma_control c_dma;
5a820fa7 86
1da177e4
LT		 87 u32 flags;
88#define CS4231_FLAG_EBUS 0x00000001
89#define CS4231_FLAG_PLAYBACK 0x00000002
90#define CS4231_FLAG_CAPTURE 0x00000004
91
be9b7e8c
TI		 92 struct snd_card *card;
93 struct snd_pcm *pcm;
94 struct snd_pcm_substream *playback_substream;
1da177e4 95 unsigned int p_periods_sent;
be9b7e8c 96 struct snd_pcm_substream *capture_substream;
1da177e4 97 unsigned int c_periods_sent;
be9b7e8c 98 struct snd_timer *timer;
1da177e4
LT		 99
100 unsigned short mode;
101#define CS4231_MODE_NONE 0x0000
102#define CS4231_MODE_PLAY 0x0001
103#define CS4231_MODE_RECORD 0x0002
104#define CS4231_MODE_TIMER 0x0004
9e9abb4f
KH		 105#define CS4231_MODE_OPEN (CS4231_MODE_PLAY | CS4231_MODE_RECORD | \
106 CS4231_MODE_TIMER)
1da177e4
LT		 107
108 unsigned char image[32]; /* registers image */
109 int mce_bit;
110 int calibrate_mute;
9e9abb4f
KH		 111 struct mutex mce_mutex; /* mutex for mce register */
112 struct mutex open_mutex; /* mutex for ALSA open/close */
1da177e4 113
2dc11581 114 struct platform_device *op;
1da177e4
LT		 115 unsigned int irq[2];
116 unsigned int regs_size;
117 struct snd_cs4231 *next;
b128254f 118};
1da177e4 119
1da177e4
LT		 120/* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
121 * now.... -DaveM
122 */
123
124/* IO ports */
7e52f3da 125#include <sound/cs4231-regs.h>
1da177e4
LT		 126
127/* XXX offsets are different than PC ISA chips... */
7e52f3da 128#define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2))
1da177e4
LT		 129
130/* SBUS DMA register defines. */
131
132#define APCCSR 0x10UL /* APC DMA CSR */
133#define APCCVA 0x20UL /* APC Capture DMA Address */
134#define APCCC 0x24UL /* APC Capture Count */
135#define APCCNVA 0x28UL /* APC Capture DMA Next Address */
136#define APCCNC 0x2cUL /* APC Capture Next Count */
137#define APCPVA 0x30UL /* APC Play DMA Address */
138#define APCPC 0x34UL /* APC Play Count */
139#define APCPNVA 0x38UL /* APC Play DMA Next Address */
140#define APCPNC 0x3cUL /* APC Play Next Count */
141
5a820fa7
GC		 142/* Defines for SBUS DMA-routines */
143
144#define APCVA 0x0UL /* APC DMA Address */
145#define APCC 0x4UL /* APC Count */
146#define APCNVA 0x8UL /* APC DMA Next Address */
147#define APCNC 0xcUL /* APC Next Count */
148#define APC_PLAY 0x30UL /* Play registers start at 0x30 */
149#define APC_RECORD 0x20UL /* Record registers start at 0x20 */
150
1da177e4
LT		 151/* APCCSR bits */
152
153#define APC_INT_PENDING 0x800000 /* Interrupt Pending */
154#define APC_PLAY_INT 0x400000 /* Playback interrupt */
155#define APC_CAPT_INT 0x200000 /* Capture interrupt */
156#define APC_GENL_INT 0x100000 /* General interrupt */
157#define APC_XINT_ENA 0x80000 /* General ext int. enable */
158#define APC_XINT_PLAY 0x40000 /* Playback ext intr */
159#define APC_XINT_CAPT 0x20000 /* Capture ext intr */
160#define APC_XINT_GENL 0x10000 /* Error ext intr */
161#define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
162#define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
163#define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
164#define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
165#define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
166#define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
167#define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
168#define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
169#define APC_PPAUSE 0x80 /* Pause the play DMA */
170#define APC_CPAUSE 0x40 /* Pause the capture DMA */
171#define APC_CDC_RESET 0x20 /* CODEC RESET */
172#define APC_PDMA_READY 0x08 /* Play DMA Go */
173#define APC_CDMA_READY 0x04 /* Capture DMA Go */
174#define APC_CHIP_RESET 0x01 /* Reset the chip */
175
176/* EBUS DMA register offsets */
177
178#define EBDMA_CSR 0x00UL /* Control/Status */
179#define EBDMA_ADDR 0x04UL /* DMA Address */
180#define EBDMA_COUNT 0x08UL /* DMA Count */
181
182/*
183 * Some variables
184 */
185
186static unsigned char freq_bits[14] = {
187 /* 5510 */ 0x00 | CS4231_XTAL2,
188 /* 6620 */ 0x0E | CS4231_XTAL2,
189 /* 8000 */ 0x00 | CS4231_XTAL1,
190 /* 9600 */ 0x0E | CS4231_XTAL1,
191 /* 11025 */ 0x02 | CS4231_XTAL2,
192 /* 16000 */ 0x02 | CS4231_XTAL1,
193 /* 18900 */ 0x04 | CS4231_XTAL2,
194 /* 22050 */ 0x06 | CS4231_XTAL2,
195 /* 27042 */ 0x04 | CS4231_XTAL1,
196 /* 32000 */ 0x06 | CS4231_XTAL1,
197 /* 33075 */ 0x0C | CS4231_XTAL2,
198 /* 37800 */ 0x08 | CS4231_XTAL2,
199 /* 44100 */ 0x0A | CS4231_XTAL2,
200 /* 48000 */ 0x0C | CS4231_XTAL1
201};
202
203static unsigned int rates[14] = {
204 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
205 27042, 32000, 33075, 37800, 44100, 48000
206};
207
be9b7e8c 208static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
c6c2d57b 209 .count = ARRAY_SIZE(rates),
1da177e4
LT		 210 .list = rates,
211};
212
be9b7e8c 213static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
1da177e4
LT		 214{
215 return snd_pcm_hw_constraint_list(runtime, 0,
216 SNDRV_PCM_HW_PARAM_RATE,
217 &hw_constraints_rates);
218}
219
220static unsigned char snd_cs4231_original_image[32] =
221{
222 0x00, /* 00/00 - lic */
223 0x00, /* 01/01 - ric */
224 0x9f, /* 02/02 - la1ic */
225 0x9f, /* 03/03 - ra1ic */
226 0x9f, /* 04/04 - la2ic */
227 0x9f, /* 05/05 - ra2ic */
228 0xbf, /* 06/06 - loc */
229 0xbf, /* 07/07 - roc */
230 0x20, /* 08/08 - pdfr */
231 CS4231_AUTOCALIB, /* 09/09 - ic */
232 0x00, /* 0a/10 - pc */
233 0x00, /* 0b/11 - ti */
234 CS4231_MODE2, /* 0c/12 - mi */
235 0x00, /* 0d/13 - lbc */
236 0x00, /* 0e/14 - pbru */
237 0x00, /* 0f/15 - pbrl */
238 0x80, /* 10/16 - afei */
239 0x01, /* 11/17 - afeii */
240 0x9f, /* 12/18 - llic */
241 0x9f, /* 13/19 - rlic */
242 0x00, /* 14/20 - tlb */
243 0x00, /* 15/21 - thb */
244 0x00, /* 16/22 - la3mic/reserved */
245 0x00, /* 17/23 - ra3mic/reserved */
246 0x00, /* 18/24 - afs */
247 0x00, /* 19/25 - lamoc/version */
248 0x00, /* 1a/26 - mioc */
249 0x00, /* 1b/27 - ramoc/reserved */
250 0x20, /* 1c/28 - cdfr */
251 0x00, /* 1d/29 - res4 */
252 0x00, /* 1e/30 - cbru */
253 0x00, /* 1f/31 - cbrl */
254};
255
be9b7e8c 256static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
1da177e4 257{
c6c2d57b 258 if (cp->flags & CS4231_FLAG_EBUS)
1da177e4 259 return readb(reg_addr);
c6c2d57b 260 else
1da177e4 261 return sbus_readb(reg_addr);
1da177e4
LT		 262}
263
9e9abb4f
KH		 264static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val,
265 void __iomem *reg_addr)
1da177e4 266{
c6c2d57b 267 if (cp->flags & CS4231_FLAG_EBUS)
1da177e4 268 return writeb(val, reg_addr);
c6c2d57b 269 else
1da177e4 270 return sbus_writeb(val, reg_addr);
1da177e4
LT		 271}
272
273/*
274 * Basic I/O functions
275 */
276
c6c2d57b 277static void snd_cs4231_ready(struct snd_cs4231 *chip)
1da177e4
LT		 278{
279 int timeout;
1da177e4 280
7e52f3da
KH		 281 for (timeout = 250; timeout > 0; timeout--) {
282 int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
283 if ((val & CS4231_INIT) == 0)
284 break;
285 udelay(100);
286 }
1da177e4
LT		 287}
288
9e9abb4f
KH		 289static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
290 unsigned char value)
1da177e4 291{
c6c2d57b 292 snd_cs4231_ready(chip);
a131430c 293#ifdef CONFIG_SND_DEBUG
7e52f3da 294 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
c6c2d57b
KH		 295 snd_printdd("out: auto calibration time out - reg = 0x%x, "
296 "value = 0x%x\n",
297 reg, value);
a131430c 298#endif
7e52f3da 299 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
c6c2d57b 300 wmb();
7e52f3da 301 __cs4231_writeb(chip, value, CS4231U(chip, REG));
1da177e4
LT		 302 mb();
303}
304
c6c2d57b
KH		 305static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
306 unsigned char mask, unsigned char value)
1da177e4 307{
c6c2d57b 308 unsigned char tmp = (chip->image[reg] & mask) | value;
1da177e4 309
c6c2d57b
KH		 310 chip->image[reg] = tmp;
311 if (!chip->calibrate_mute)
312 snd_cs4231_dout(chip, reg, tmp);
313}
314
315static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg,
316 unsigned char value)
317{
318 snd_cs4231_dout(chip, reg, value);
1da177e4
LT		 319 chip->image[reg] = value;
320 mb();
1da177e4
LT		 321}
322
be9b7e8c 323static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
1da177e4 324{
c6c2d57b 325 snd_cs4231_ready(chip);
1da177e4 326#ifdef CONFIG_SND_DEBUG
7e52f3da 327 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
c6c2d57b
KH		 328 snd_printdd("in: auto calibration time out - reg = 0x%x\n",
329 reg);
1da177e4 330#endif
7e52f3da 331 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
1da177e4 332 mb();
7e52f3da 333 return __cs4231_readb(chip, CS4231U(chip, REG));
1da177e4
LT		 334}
335
1da177e4
LT		 336/*
337 * CS4231 detection / MCE routines
338 */
339
be9b7e8c 340static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
1da177e4
LT		 341{
342 int timeout;
343
9e9abb4f 344 /* looks like this sequence is proper for CS4231A chip (GUS MAX) */
1da177e4 345 for (timeout = 5; timeout > 0; timeout--)
7e52f3da 346 __cs4231_readb(chip, CS4231U(chip, REGSEL));
a131430c 347
1da177e4 348 /* end of cleanup sequence */
7e52f3da
KH		 349 for (timeout = 500; timeout > 0; timeout--) {
350 int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
351 if ((val & CS4231_INIT) == 0)
352 break;
c6c2d57b 353 msleep(1);
7e52f3da 354 }
1da177e4
LT		 355}
356
be9b7e8c 357static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
1da177e4
LT		 358{
359 unsigned long flags;
360 int timeout;
361
362 spin_lock_irqsave(&chip->lock, flags);
c6c2d57b 363 snd_cs4231_ready(chip);
1da177e4 364#ifdef CONFIG_SND_DEBUG
7e52f3da 365 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
a131430c 366 snd_printdd("mce_up - auto calibration time out (0)\n");
1da177e4
LT		 367#endif
368 chip->mce_bit |= CS4231_MCE;
7e52f3da 369 timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL));
1da177e4 370 if (timeout == 0x80)
9e9abb4f
KH		 371 snd_printdd("mce_up [%p]: serious init problem - "
372 "codec still busy\n",
373 chip->port);
1da177e4 374 if (!(timeout & CS4231_MCE))
7e52f3da
KH		 375 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f),
376 CS4231U(chip, REGSEL));
1da177e4
LT		 377 spin_unlock_irqrestore(&chip->lock, flags);
378}
379
be9b7e8c 380static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
1da177e4 381{
9823adf6
KH		 382 unsigned long flags, timeout;
383 int reg;
1da177e4 384
1da177e4 385 snd_cs4231_busy_wait(chip);
9823adf6 386 spin_lock_irqsave(&chip->lock, flags);
1da177e4 387#ifdef CONFIG_SND_DEBUG
7e52f3da
KH		 388 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
389 snd_printdd("mce_down [%p] - auto calibration time out (0)\n",
390 CS4231U(chip, REGSEL));
1da177e4
LT		 391#endif
392 chip->mce_bit &= ~CS4231_MCE;
9823adf6
KH		 393 reg = __cs4231_readb(chip, CS4231U(chip, REGSEL));
394 __cs4231_writeb(chip, chip->mce_bit | (reg & 0x1f),
7e52f3da 395 CS4231U(chip, REGSEL));
9823adf6
KH		 396 if (reg == 0x80)
397 snd_printdd("mce_down [%p]: serious init problem "
398 "- codec still busy\n", chip->port);
399 if ((reg & CS4231_MCE) == 0) {
1da177e4
LT		 400 spin_unlock_irqrestore(&chip->lock, flags);
401 return;
402 }
1da177e4 403
56f91585 404 /*
9823adf6 405 * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
56f91585 406 */
9823adf6
KH		 407 timeout = jiffies + msecs_to_jiffies(250);
408 do {
1da177e4 409 spin_unlock_irqrestore(&chip->lock, flags);
b875d650 410 msleep(1);
1da177e4 411 spin_lock_irqsave(&chip->lock, flags);
9823adf6
KH		 412 reg = snd_cs4231_in(chip, CS4231_TEST_INIT);
413 reg &= CS4231_CALIB_IN_PROGRESS;
414 } while (reg && time_before(jiffies, timeout));
1da177e4 415 spin_unlock_irqrestore(&chip->lock, flags);
9823adf6
KH		 416
417 if (reg)
418 snd_printk(KERN_ERR
419 "mce_down - auto calibration time out (2)\n");
1da177e4
LT		 420}
421
be9b7e8c
TI		 422static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
423 struct snd_pcm_substream *substream,
424 unsigned int *periods_sent)
1da177e4 425{
be9b7e8c 426 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 427
428 while (1) {
a131430c
CZ		 429 unsigned int period_size = snd_pcm_lib_period_bytes(substream);
430 unsigned int offset = period_size * (*periods_sent);
1da177e4 431
817dd6ee 432 BUG_ON(period_size >= (1 << 24));
1da177e4 433
9e9abb4f
KH		 434 if (dma_cont->request(dma_cont,
435 runtime->dma_addr + offset, period_size))
1da177e4 436 return;
1da177e4
LT		 437 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
438 }
439}
a131430c 440
be9b7e8c
TI		 441static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
442 unsigned int what, int on)
1da177e4 443{
be9b7e8c
TI		 444 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
445 struct cs4231_dma_control *dma_cont;
a131430c 446
5a820fa7 447 if (what & CS4231_PLAYBACK_ENABLE) {
b128254f 448 dma_cont = &chip->p_dma;
a131430c 449 if (on) {
b128254f
GC		 450 dma_cont->prepare(dma_cont, 0);
451 dma_cont->enable(dma_cont, 1);
452 snd_cs4231_advance_dma(dma_cont,
5a820fa7
GC		 453 chip->playback_substream,
454 &chip->p_periods_sent);
a131430c 455 } else {
b128254f 456 dma_cont->enable(dma_cont, 0);
a131430c 457 }
5a820fa7
GC		 458 }
459 if (what & CS4231_RECORD_ENABLE) {
b128254f 460 dma_cont = &chip->c_dma;
a131430c 461 if (on) {
b128254f
GC		 462 dma_cont->prepare(dma_cont, 1);
463 dma_cont->enable(dma_cont, 1);
464 snd_cs4231_advance_dma(dma_cont,
5a820fa7
GC		 465 chip->capture_substream,
466 &chip->c_periods_sent);
a131430c 467 } else {
b128254f 468 dma_cont->enable(dma_cont, 0);
a131430c 469 }
a131430c 470 }
1da177e4
LT		 471}
472
be9b7e8c 473static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 474{
be9b7e8c 475 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 476 int result = 0;
477
478 switch (cmd) {
479 case SNDRV_PCM_TRIGGER_START:
480 case SNDRV_PCM_TRIGGER_STOP:
481 {
482 unsigned int what = 0;
be9b7e8c 483 struct snd_pcm_substream *s;
1da177e4
LT		 484 unsigned long flags;
485
ef991b95 486 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT		 487 if (s == chip->playback_substream) {
488 what |= CS4231_PLAYBACK_ENABLE;
489 snd_pcm_trigger_done(s, substream);
490 } else if (s == chip->capture_substream) {
491 what |= CS4231_RECORD_ENABLE;
492 snd_pcm_trigger_done(s, substream);
493 }
494 }
495
1da177e4
LT		 496 spin_lock_irqsave(&chip->lock, flags);
497 if (cmd == SNDRV_PCM_TRIGGER_START) {
a131430c 498 cs4231_dma_trigger(substream, what, 1);
1da177e4 499 chip->image[CS4231_IFACE_CTRL] |= what;
1da177e4 500 } else {
a131430c 501 cs4231_dma_trigger(substream, what, 0);
1da177e4
LT		 502 chip->image[CS4231_IFACE_CTRL] &= ~what;
503 }
504 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
505 chip->image[CS4231_IFACE_CTRL]);
506 spin_unlock_irqrestore(&chip->lock, flags);
507 break;
508 }
509 default:
510 result = -EINVAL;
511 break;
512 }
a131430c 513
1da177e4
LT		 514 return result;
515}
516
517/*
518 * CODEC I/O
519 */
520
521static unsigned char snd_cs4231_get_rate(unsigned int rate)
522{
523 int i;
524
525 for (i = 0; i < 14; i++)
526 if (rate == rates[i])
527 return freq_bits[i];
9e9abb4f 528
1da177e4
LT		 529 return freq_bits[13];
530}
531
9e9abb4f
KH		 532static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format,
533 int channels)
1da177e4
LT		 534{
535 unsigned char rformat;
536
537 rformat = CS4231_LINEAR_8;
538 switch (format) {
9e9abb4f
KH		 539 case SNDRV_PCM_FORMAT_MU_LAW:
540 rformat = CS4231_ULAW_8;
541 break;
542 case SNDRV_PCM_FORMAT_A_LAW:
543 rformat = CS4231_ALAW_8;
544 break;
545 case SNDRV_PCM_FORMAT_S16_LE:
546 rformat = CS4231_LINEAR_16;
547 break;
548 case SNDRV_PCM_FORMAT_S16_BE:
549 rformat = CS4231_LINEAR_16_BIG;
550 break;
551 case SNDRV_PCM_FORMAT_IMA_ADPCM:
552 rformat = CS4231_ADPCM_16;
553 break;
1da177e4
LT		 554 }
555 if (channels > 1)
556 rformat |= CS4231_STEREO;
1da177e4
LT		 557 return rformat;
558}
559
be9b7e8c 560static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
1da177e4
LT		 561{
562 unsigned long flags;
563
564 mute = mute ? 1 : 0;
565 spin_lock_irqsave(&chip->lock, flags);
566 if (chip->calibrate_mute == mute) {
567 spin_unlock_irqrestore(&chip->lock, flags);
568 return;
569 }
570 if (!mute) {
571 snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
572 chip->image[CS4231_LEFT_INPUT]);
573 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
574 chip->image[CS4231_RIGHT_INPUT]);
575 snd_cs4231_dout(chip, CS4231_LOOPBACK,
576 chip->image[CS4231_LOOPBACK]);
577 }
578 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
579 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
580 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
581 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
582 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
583 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
584 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
585 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
586 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
587 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
588 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
589 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
590 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
591 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
592 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
593 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
594 snd_cs4231_dout(chip, CS4231_MONO_CTRL,
595 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
596 chip->calibrate_mute = mute;
597 spin_unlock_irqrestore(&chip->lock, flags);
598}
599
9e9abb4f
KH		 600static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
601 struct snd_pcm_hw_params *params,
1da177e4
LT		 602 unsigned char pdfr)
603{
604 unsigned long flags;
605
12aa7579 606 mutex_lock(&chip->mce_mutex);
1da177e4
LT		 607 snd_cs4231_calibrate_mute(chip, 1);
608
609 snd_cs4231_mce_up(chip);
610
611 spin_lock_irqsave(&chip->lock, flags);
612 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
613 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
614 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
615 pdfr);
616 spin_unlock_irqrestore(&chip->lock, flags);
617
618 snd_cs4231_mce_down(chip);
619
620 snd_cs4231_calibrate_mute(chip, 0);
12aa7579 621 mutex_unlock(&chip->mce_mutex);
1da177e4
LT		 622}
623
9e9abb4f
KH		 624static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
625 struct snd_pcm_hw_params *params,
626 unsigned char cdfr)
1da177e4
LT		 627{
628 unsigned long flags;
629
12aa7579 630 mutex_lock(&chip->mce_mutex);
1da177e4
LT		 631 snd_cs4231_calibrate_mute(chip, 1);
632
633 snd_cs4231_mce_up(chip);
634
635 spin_lock_irqsave(&chip->lock, flags);
636 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
637 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
638 ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
639 (cdfr & 0x0f));
640 spin_unlock_irqrestore(&chip->lock, flags);
641 snd_cs4231_mce_down(chip);
642 snd_cs4231_mce_up(chip);
643 spin_lock_irqsave(&chip->lock, flags);
644 }
645 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
646 spin_unlock_irqrestore(&chip->lock, flags);
647
648 snd_cs4231_mce_down(chip);
649
650 snd_cs4231_calibrate_mute(chip, 0);
12aa7579 651 mutex_unlock(&chip->mce_mutex);
1da177e4
LT		 652}
653
654/*
655 * Timer interface
656 */
657
be9b7e8c 658static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
1da177e4 659{
be9b7e8c 660 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 661
662 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
663}
664
be9b7e8c 665static int snd_cs4231_timer_start(struct snd_timer *timer)
1da177e4
LT		 666{
667 unsigned long flags;
668 unsigned int ticks;
be9b7e8c 669 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 670
671 spin_lock_irqsave(&chip->lock, flags);
672 ticks = timer->sticks;
673 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
674 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
675 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
676 snd_cs4231_out(chip, CS4231_TIMER_HIGH,
677 chip->image[CS4231_TIMER_HIGH] =
678 (unsigned char) (ticks >> 8));
679 snd_cs4231_out(chip, CS4231_TIMER_LOW,
680 chip->image[CS4231_TIMER_LOW] =
681 (unsigned char) ticks);
682 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
9e9abb4f
KH		 683 chip->image[CS4231_ALT_FEATURE_1] |
684 CS4231_TIMER_ENABLE);
1da177e4
LT		 685 }
686 spin_unlock_irqrestore(&chip->lock, flags);
687
688 return 0;
689}
690
be9b7e8c 691static int snd_cs4231_timer_stop(struct snd_timer *timer)
1da177e4
LT		 692{
693 unsigned long flags;
be9b7e8c 694 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 695
696 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f 697 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
1da177e4 698 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
9e9abb4f 699 chip->image[CS4231_ALT_FEATURE_1]);
1da177e4
LT		 700 spin_unlock_irqrestore(&chip->lock, flags);
701
702 return 0;
703}
704
32e02a7b 705static void snd_cs4231_init(struct snd_cs4231 *chip)
1da177e4
LT		 706{
707 unsigned long flags;
708
709 snd_cs4231_mce_down(chip);
710
711#ifdef SNDRV_DEBUG_MCE
a131430c 712 snd_printdd("init: (1)\n");
1da177e4
LT		 713#endif
714 snd_cs4231_mce_up(chip);
715 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 716 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
717 CS4231_PLAYBACK_PIO |
718 CS4231_RECORD_ENABLE |
719 CS4231_RECORD_PIO |
1da177e4
LT		 720 CS4231_CALIB_MODE);
721 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
722 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
723 spin_unlock_irqrestore(&chip->lock, flags);
724 snd_cs4231_mce_down(chip);
725
726#ifdef SNDRV_DEBUG_MCE
a131430c 727 snd_printdd("init: (2)\n");
1da177e4
LT		 728#endif
729
730 snd_cs4231_mce_up(chip);
731 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 732 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
733 chip->image[CS4231_ALT_FEATURE_1]);
1da177e4
LT		 734 spin_unlock_irqrestore(&chip->lock, flags);
735 snd_cs4231_mce_down(chip);
736
737#ifdef SNDRV_DEBUG_MCE
9e9abb4f
KH		 738 snd_printdd("init: (3) - afei = 0x%x\n",
739 chip->image[CS4231_ALT_FEATURE_1]);
1da177e4
LT		 740#endif
741
742 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 743 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2,
744 chip->image[CS4231_ALT_FEATURE_2]);
1da177e4
LT		 745 spin_unlock_irqrestore(&chip->lock, flags);
746
747 snd_cs4231_mce_up(chip);
748 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 749 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
750 chip->image[CS4231_PLAYBK_FORMAT]);
1da177e4
LT		 751 spin_unlock_irqrestore(&chip->lock, flags);
752 snd_cs4231_mce_down(chip);
753
754#ifdef SNDRV_DEBUG_MCE
a131430c 755 snd_printdd("init: (4)\n");
1da177e4
LT		 756#endif
757
758 snd_cs4231_mce_up(chip);
759 spin_lock_irqsave(&chip->lock, flags);
760 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
761 spin_unlock_irqrestore(&chip->lock, flags);
762 snd_cs4231_mce_down(chip);
763
764#ifdef SNDRV_DEBUG_MCE
a131430c 765 snd_printdd("init: (5)\n");
1da177e4
LT		 766#endif
767}
768
be9b7e8c 769static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
1da177e4
LT		 770{
771 unsigned long flags;
772
12aa7579 773 mutex_lock(&chip->open_mutex);
1da177e4 774 if ((chip->mode & mode)) {
12aa7579 775 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 776 return -EAGAIN;
777 }
778 if (chip->mode & CS4231_MODE_OPEN) {
779 chip->mode |= mode;
12aa7579 780 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 781 return 0;
782 }
783 /* ok. now enable and ack CODEC IRQ */
784 spin_lock_irqsave(&chip->lock, flags);
785 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
786 CS4231_RECORD_IRQ |
787 CS4231_TIMER_IRQ);
788 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
7e52f3da
KH		 789 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
790 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
1da177e4
LT		 791
792 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
793 CS4231_RECORD_IRQ |
794 CS4231_TIMER_IRQ);
795 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
a131430c 796
1da177e4
LT		 797 spin_unlock_irqrestore(&chip->lock, flags);
798
799 chip->mode = mode;
12aa7579 800 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 801 return 0;
802}
803
be9b7e8c 804static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
1da177e4
LT		 805{
806 unsigned long flags;
807
12aa7579 808 mutex_lock(&chip->open_mutex);
1da177e4
LT		 809 chip->mode &= ~mode;
810 if (chip->mode & CS4231_MODE_OPEN) {
12aa7579 811 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 812 return;
813 }
814 snd_cs4231_calibrate_mute(chip, 1);
815
816 /* disable IRQ */
817 spin_lock_irqsave(&chip->lock, flags);
818 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
7e52f3da
KH		 819 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
820 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
1da177e4
LT		 821
822 /* now disable record & playback */
823
824 if (chip->image[CS4231_IFACE_CTRL] &
825 (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
826 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
827 spin_unlock_irqrestore(&chip->lock, flags);
828 snd_cs4231_mce_up(chip);
829 spin_lock_irqsave(&chip->lock, flags);
830 chip->image[CS4231_IFACE_CTRL] &=
831 ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
832 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
9e9abb4f
KH		 833 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
834 chip->image[CS4231_IFACE_CTRL]);
1da177e4
LT		 835 spin_unlock_irqrestore(&chip->lock, flags);
836 snd_cs4231_mce_down(chip);
837 spin_lock_irqsave(&chip->lock, flags);
838 }
839
840 /* clear IRQ again */
841 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
7e52f3da
KH		 842 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
843 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
1da177e4
LT		 844 spin_unlock_irqrestore(&chip->lock, flags);
845
846 snd_cs4231_calibrate_mute(chip, 0);
847
848 chip->mode = 0;
12aa7579 849 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 850}
851
852/*
853 * timer open/close
854 */
855
be9b7e8c 856static int snd_cs4231_timer_open(struct snd_timer *timer)
1da177e4 857{
be9b7e8c 858 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 859 snd_cs4231_open(chip, CS4231_MODE_TIMER);
860 return 0;
861}
862
9e9abb4f 863static int snd_cs4231_timer_close(struct snd_timer *timer)
1da177e4 864{
be9b7e8c 865 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 866 snd_cs4231_close(chip, CS4231_MODE_TIMER);
867 return 0;
868}
869
9e9abb4f 870static struct snd_timer_hardware snd_cs4231_timer_table = {
1da177e4
LT		 871 .flags = SNDRV_TIMER_HW_AUTO,
872 .resolution = 9945,
873 .ticks = 65535,
874 .open = snd_cs4231_timer_open,
875 .close = snd_cs4231_timer_close,
876 .c_resolution = snd_cs4231_timer_resolution,
877 .start = snd_cs4231_timer_start,
878 .stop = snd_cs4231_timer_stop,
879};
880
881/*
882 * ok.. exported functions..
883 */
884
be9b7e8c
TI		 885static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
886 struct snd_pcm_hw_params *hw_params)
1da177e4 887{
be9b7e8c 888 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 889 unsigned char new_pdfr;
890 int err;
891
9e9abb4f
KH		 892 err = snd_pcm_lib_malloc_pages(substream,
893 params_buffer_bytes(hw_params));
894 if (err < 0)
1da177e4
LT		 895 return err;
896 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
897 params_channels(hw_params)) |
898 snd_cs4231_get_rate(params_rate(hw_params));
899 snd_cs4231_playback_format(chip, hw_params, new_pdfr);
900
901 return 0;
902}
903
be9b7e8c 904static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 905{
be9b7e8c
TI		 906 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
907 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 908 unsigned long flags;
909
910 spin_lock_irqsave(&chip->lock, flags);
a131430c 911
1da177e4
LT		 912 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
913 CS4231_PLAYBACK_PIO);
a131430c 914
817dd6ee 915 BUG_ON(runtime->period_size > 0xffff + 1);
a131430c 916
a131430c 917 chip->p_periods_sent = 0;
1da177e4
LT		 918 spin_unlock_irqrestore(&chip->lock, flags);
919
920 return 0;
921}
922
be9b7e8c
TI		 923static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
924 struct snd_pcm_hw_params *hw_params)
1da177e4 925{
be9b7e8c 926 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 927 unsigned char new_cdfr;
928 int err;
929
9e9abb4f
KH		 930 err = snd_pcm_lib_malloc_pages(substream,
931 params_buffer_bytes(hw_params));
932 if (err < 0)
1da177e4
LT		 933 return err;
934 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
935 params_channels(hw_params)) |
936 snd_cs4231_get_rate(params_rate(hw_params));
937 snd_cs4231_capture_format(chip, hw_params, new_cdfr);
938
939 return 0;
940}
941
be9b7e8c 942static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 943{
be9b7e8c 944 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 945 unsigned long flags;
946
947 spin_lock_irqsave(&chip->lock, flags);
948 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
949 CS4231_RECORD_PIO);
950
a131430c 951
5a820fa7 952 chip->c_periods_sent = 0;
1da177e4
LT		 953 spin_unlock_irqrestore(&chip->lock, flags);
954
955 return 0;
956}
957
be9b7e8c 958static void snd_cs4231_overrange(struct snd_cs4231 *chip)
1da177e4
LT		 959{
960 unsigned long flags;
961 unsigned char res;
962
963 spin_lock_irqsave(&chip->lock, flags);
964 res = snd_cs4231_in(chip, CS4231_TEST_INIT);
965 spin_unlock_irqrestore(&chip->lock, flags);
966
9e9abb4f
KH		 967 /* detect overrange only above 0dB; may be user selectable? */
968 if (res & (0x08 | 0x02))
1da177e4
LT		 969 chip->capture_substream->runtime->overrange++;
970}
971
be9b7e8c 972static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
1da177e4 973{
1da177e4
LT		 974 if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
975 snd_pcm_period_elapsed(chip->playback_substream);
b128254f 976 snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
1da177e4
LT		 977 &chip->p_periods_sent);
978 }
979}
980
be9b7e8c 981static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
1da177e4 982{
1da177e4
LT		 983 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
984 snd_pcm_period_elapsed(chip->capture_substream);
b128254f 985 snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
1da177e4
LT		 986 &chip->c_periods_sent);
987 }
988}
1da177e4 989
9e9abb4f
KH		 990static snd_pcm_uframes_t snd_cs4231_playback_pointer(
991 struct snd_pcm_substream *substream)
1da177e4 992{
be9b7e8c
TI		 993 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
994 struct cs4231_dma_control *dma_cont = &chip->p_dma;
5a820fa7 995 size_t ptr;
9e9abb4f 996
1da177e4
LT		 997 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
998 return 0;
b128254f
GC		 999 ptr = dma_cont->address(dma_cont);
1000 if (ptr != 0)
1001 ptr -= substream->runtime->dma_addr;
9e9abb4f 1002
1da177e4
LT		 1003 return bytes_to_frames(substream->runtime, ptr);
1004}
1005
9e9abb4f
KH		 1006static snd_pcm_uframes_t snd_cs4231_capture_pointer(
1007 struct snd_pcm_substream *substream)
1da177e4 1008{
be9b7e8c
TI		 1009 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1010 struct cs4231_dma_control *dma_cont = &chip->c_dma;
5a820fa7 1011 size_t ptr;
9e9abb4f 1012
1da177e4
LT		 1013 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1014 return 0;
b128254f
GC		 1015 ptr = dma_cont->address(dma_cont);
1016 if (ptr != 0)
1017 ptr -= substream->runtime->dma_addr;
9e9abb4f 1018
1da177e4
LT		 1019 return bytes_to_frames(substream->runtime, ptr);
1020}
1021
32e02a7b 1022static int snd_cs4231_probe(struct snd_cs4231 *chip)
1da177e4
LT		 1023{
1024 unsigned long flags;
9e9abb4f
KH		 1025 int i;
1026 int id = 0;
1027 int vers = 0;
1da177e4
LT		 1028 unsigned char *ptr;
1029
1da177e4
LT		 1030 for (i = 0; i < 50; i++) {
1031 mb();
7e52f3da 1032 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
9e9abb4f 1033 msleep(2);
1da177e4
LT		 1034 else {
1035 spin_lock_irqsave(&chip->lock, flags);
1036 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
1037 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
1038 vers = snd_cs4231_in(chip, CS4231_VERSION);
1039 spin_unlock_irqrestore(&chip->lock, flags);
1040 if (id == 0x0a)
1041 break; /* this is valid value */
1042 }
1043 }
1044 snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
1045 if (id != 0x0a)
1046 return -ENODEV; /* no valid device found */
1047
1048 spin_lock_irqsave(&chip->lock, flags);
1049
7e52f3da
KH		 1050 /* clear any pendings IRQ */
1051 __cs4231_readb(chip, CS4231U(chip, STATUS));
1052 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS));
1da177e4
LT		 1053 mb();
1054
1055 spin_unlock_irqrestore(&chip->lock, flags);
1056
1057 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1058 chip->image[CS4231_IFACE_CTRL] =
1059 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
1060 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1061 chip->image[CS4231_ALT_FEATURE_2] = 0x01;
1062 if (vers & 0x20)
1063 chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
1064
1065 ptr = (unsigned char *) &chip->image;
1066
1067 snd_cs4231_mce_down(chip);
1068
1069 spin_lock_irqsave(&chip->lock, flags);
1070
1071 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
1072 snd_cs4231_out(chip, i, *ptr++);
1073
1074 spin_unlock_irqrestore(&chip->lock, flags);
1075
1076 snd_cs4231_mce_up(chip);
1077
1078 snd_cs4231_mce_down(chip);
1079
1080 mdelay(2);
1081
1082 return 0; /* all things are ok.. */
1083}
1084
9e9abb4f
KH		 1085static struct snd_pcm_hardware snd_cs4231_playback = {
1086 .info = SNDRV_PCM_INFO_MMAP |
1087 SNDRV_PCM_INFO_INTERLEAVED |
1088 SNDRV_PCM_INFO_MMAP_VALID |
1089 SNDRV_PCM_INFO_SYNC_START,
1090 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1091 SNDRV_PCM_FMTBIT_A_LAW |
1092 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1093 SNDRV_PCM_FMTBIT_U8 |
1094 SNDRV_PCM_FMTBIT_S16_LE |
1095 SNDRV_PCM_FMTBIT_S16_BE,
1096 .rates = SNDRV_PCM_RATE_KNOT |
1097 SNDRV_PCM_RATE_8000_48000,
1da177e4
LT		 1098 .rate_min = 5510,
1099 .rate_max = 48000,
1100 .channels_min = 1,
1101 .channels_max = 2,
9e9abb4f 1102 .buffer_bytes_max = 32 * 1024,
f9af1d9d 1103 .period_bytes_min = 64,
9e9abb4f 1104 .period_bytes_max = 32 * 1024,
1da177e4
LT		 1105 .periods_min = 1,
1106 .periods_max = 1024,
1107};
1108
9e9abb4f
KH		 1109static struct snd_pcm_hardware snd_cs4231_capture = {
1110 .info = SNDRV_PCM_INFO_MMAP |
1111 SNDRV_PCM_INFO_INTERLEAVED |
1112 SNDRV_PCM_INFO_MMAP_VALID |
1113 SNDRV_PCM_INFO_SYNC_START,
1114 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1115 SNDRV_PCM_FMTBIT_A_LAW |
1116 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1117 SNDRV_PCM_FMTBIT_U8 |
1118 SNDRV_PCM_FMTBIT_S16_LE |
1119 SNDRV_PCM_FMTBIT_S16_BE,
1120 .rates = SNDRV_PCM_RATE_KNOT |
1121 SNDRV_PCM_RATE_8000_48000,
1da177e4
LT		 1122 .rate_min = 5510,
1123 .rate_max = 48000,
1124 .channels_min = 1,
1125 .channels_max = 2,
9e9abb4f 1126 .buffer_bytes_max = 32 * 1024,
f9af1d9d 1127 .period_bytes_min = 64,
9e9abb4f 1128 .period_bytes_max = 32 * 1024,
1da177e4
LT		 1129 .periods_min = 1,
1130 .periods_max = 1024,
1131};
1132
be9b7e8c 1133static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
1da177e4 1134{
be9b7e8c
TI		 1135 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1136 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1137 int err;
1138
1139 runtime->hw = snd_cs4231_playback;
1140
9e9abb4f
KH		 1141 err = snd_cs4231_open(chip, CS4231_MODE_PLAY);
1142 if (err < 0) {
1da177e4
LT		 1143 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1144 return err;
1145 }
1146 chip->playback_substream = substream;
1147 chip->p_periods_sent = 0;
1148 snd_pcm_set_sync(substream);
1149 snd_cs4231_xrate(runtime);
1150
1151 return 0;
1152}
1153
be9b7e8c 1154static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
1da177e4 1155{
be9b7e8c
TI		 1156 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1157 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1158 int err;
1159
1160 runtime->hw = snd_cs4231_capture;
1161
9e9abb4f
KH		 1162 err = snd_cs4231_open(chip, CS4231_MODE_RECORD);
1163 if (err < 0) {
1da177e4
LT		 1164 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1165 return err;
1166 }
1167 chip->capture_substream = substream;
1168 chip->c_periods_sent = 0;
1169 snd_pcm_set_sync(substream);
1170 snd_cs4231_xrate(runtime);
1171
1172 return 0;
1173}
1174
be9b7e8c 1175static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
1da177e4 1176{
be9b7e8c 1177 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4 1178
1da177e4 1179 snd_cs4231_close(chip, CS4231_MODE_PLAY);
b128254f 1180 chip->playback_substream = NULL;
1da177e4
LT		 1181
1182 return 0;
1183}
1184
be9b7e8c 1185static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
1da177e4 1186{
be9b7e8c 1187 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4 1188
1da177e4 1189 snd_cs4231_close(chip, CS4231_MODE_RECORD);
b128254f 1190 chip->capture_substream = NULL;
1da177e4
LT		 1191
1192 return 0;
1193}
1194
1195/* XXX We can do some power-management, in particular on EBUS using
1196 * XXX the audio AUXIO register...
1197 */
1198
be9b7e8c 1199static struct snd_pcm_ops snd_cs4231_playback_ops = {
1da177e4
LT		 1200 .open = snd_cs4231_playback_open,
1201 .close = snd_cs4231_playback_close,
1202 .ioctl = snd_pcm_lib_ioctl,
1203 .hw_params = snd_cs4231_playback_hw_params,
c6c2d57b 1204 .hw_free = snd_pcm_lib_free_pages,
1da177e4
LT		 1205 .prepare = snd_cs4231_playback_prepare,
1206 .trigger = snd_cs4231_trigger,
1207 .pointer = snd_cs4231_playback_pointer,
1208};
1209
be9b7e8c 1210static struct snd_pcm_ops snd_cs4231_capture_ops = {
1da177e4
LT		 1211 .open = snd_cs4231_capture_open,
1212 .close = snd_cs4231_capture_close,
1213 .ioctl = snd_pcm_lib_ioctl,
1214 .hw_params = snd_cs4231_capture_hw_params,
c6c2d57b 1215 .hw_free = snd_pcm_lib_free_pages,
1da177e4
LT		 1216 .prepare = snd_cs4231_capture_prepare,
1217 .trigger = snd_cs4231_trigger,
1218 .pointer = snd_cs4231_capture_pointer,
1219};
1220
32e02a7b 1221static int snd_cs4231_pcm(struct snd_card *card)
1da177e4 1222{
c6c2d57b 1223 struct snd_cs4231 *chip = card->private_data;
be9b7e8c 1224 struct snd_pcm *pcm;
1da177e4
LT		 1225 int err;
1226
c6c2d57b
KH		 1227 err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm);
1228 if (err < 0)
1da177e4
LT		 1229 return err;
1230
9e9abb4f
KH		 1231 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1232 &snd_cs4231_playback_ops);
1233 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1234 &snd_cs4231_capture_ops);
1235
1da177e4
LT		 1236 /* global setup */
1237 pcm->private_data = chip;
1da177e4
LT		 1238 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1239 strcpy(pcm->name, "CS4231");
1240
afc88ad6
DM		 1241 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1242 &chip->op->dev,
1243 64 * 1024, 128 * 1024);
1da177e4
LT		 1244
1245 chip->pcm = pcm;
1246
1247 return 0;
1248}
1249
32e02a7b 1250static int snd_cs4231_timer(struct snd_card *card)
1da177e4 1251{
c6c2d57b 1252 struct snd_cs4231 *chip = card->private_data;
be9b7e8c
TI		 1253 struct snd_timer *timer;
1254 struct snd_timer_id tid;
1da177e4
LT		 1255 int err;
1256
1257 /* Timer initialization */
1258 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1259 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
c6c2d57b 1260 tid.card = card->number;
1da177e4
LT		 1261 tid.device = 0;
1262 tid.subdevice = 0;
c6c2d57b
KH		 1263 err = snd_timer_new(card, "CS4231", &tid, &timer);
1264 if (err < 0)
1da177e4
LT		 1265 return err;
1266 strcpy(timer->name, "CS4231");
1267 timer->private_data = chip;
1da177e4
LT		 1268 timer->hw = snd_cs4231_timer_table;
1269 chip->timer = timer;
1270
1271 return 0;
1272}
9e9abb4f 1273
1da177e4
LT		 1274/*
1275 * MIXER part
1276 */
1277
be9b7e8c
TI		 1278static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
1279 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1280{
1281 static char *texts[4] = {
1282 "Line", "CD", "Mic", "Mix"
1283 };
1da177e4 1284
1da177e4
LT		 1285 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1286 uinfo->count = 2;
1287 uinfo->value.enumerated.items = 4;
1288 if (uinfo->value.enumerated.item > 3)
1289 uinfo->value.enumerated.item = 3;
9e9abb4f
KH		 1290 strcpy(uinfo->value.enumerated.name,
1291 texts[uinfo->value.enumerated.item]);
1da177e4
LT		 1292
1293 return 0;
1294}
1295
be9b7e8c
TI		 1296static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
1297 struct snd_ctl_elem_value *ucontrol)
1da177e4 1298{
be9b7e8c 1299 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4 1300 unsigned long flags;
9e9abb4f 1301
1da177e4
LT		 1302 spin_lock_irqsave(&chip->lock, flags);
1303 ucontrol->value.enumerated.item[0] =
1304 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1305 ucontrol->value.enumerated.item[1] =
1306 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1307 spin_unlock_irqrestore(&chip->lock, flags);
1308
1309 return 0;
1310}
1311
be9b7e8c
TI		 1312static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
1313 struct snd_ctl_elem_value *ucontrol)
1da177e4 1314{
be9b7e8c 1315 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1316 unsigned long flags;
1317 unsigned short left, right;
1318 int change;
9e9abb4f 1319
1da177e4
LT		 1320 if (ucontrol->value.enumerated.item[0] > 3 ||
1321 ucontrol->value.enumerated.item[1] > 3)
1322 return -EINVAL;
1323 left = ucontrol->value.enumerated.item[0] << 6;
1324 right = ucontrol->value.enumerated.item[1] << 6;
1325
1326 spin_lock_irqsave(&chip->lock, flags);
1327
1328 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1329 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1330 change = left != chip->image[CS4231_LEFT_INPUT] ||
9e9abb4f 1331 right != chip->image[CS4231_RIGHT_INPUT];
1da177e4
LT		 1332 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
1333 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
1334
1335 spin_unlock_irqrestore(&chip->lock, flags);
1336
1337 return change;
1338}
1339
be9b7e8c
TI		 1340static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
1341 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1342{
1343 int mask = (kcontrol->private_value >> 16) & 0xff;
1344
1345 uinfo->type = (mask == 1) ?
1346 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1347 uinfo->count = 1;
1348 uinfo->value.integer.min = 0;
1349 uinfo->value.integer.max = mask;
1350
1351 return 0;
1352}
1353
be9b7e8c
TI		 1354static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
1355 struct snd_ctl_elem_value *ucontrol)
1da177e4 1356{
be9b7e8c 1357 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1358 unsigned long flags;
1359 int reg = kcontrol->private_value & 0xff;
1360 int shift = (kcontrol->private_value >> 8) & 0xff;
1361 int mask = (kcontrol->private_value >> 16) & 0xff;
1362 int invert = (kcontrol->private_value >> 24) & 0xff;
9e9abb4f 1363
1da177e4
LT		 1364 spin_lock_irqsave(&chip->lock, flags);
1365
1366 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
1367
1368 spin_unlock_irqrestore(&chip->lock, flags);
1369
1370 if (invert)
1371 ucontrol->value.integer.value[0] =
1372 (mask - ucontrol->value.integer.value[0]);
1373
1374 return 0;
1375}
1376
be9b7e8c
TI		 1377static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
1378 struct snd_ctl_elem_value *ucontrol)
1da177e4 1379{
be9b7e8c 1380 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1381 unsigned long flags;
1382 int reg = kcontrol->private_value & 0xff;
1383 int shift = (kcontrol->private_value >> 8) & 0xff;
1384 int mask = (kcontrol->private_value >> 16) & 0xff;
1385 int invert = (kcontrol->private_value >> 24) & 0xff;
1386 int change;
1387 unsigned short val;
9e9abb4f 1388
1da177e4
LT		 1389 val = (ucontrol->value.integer.value[0] & mask);
1390 if (invert)
1391 val = mask - val;
1392 val <<= shift;
1393
1394 spin_lock_irqsave(&chip->lock, flags);
1395
1396 val = (chip->image[reg] & ~(mask << shift)) | val;
1397 change = val != chip->image[reg];
1398 snd_cs4231_out(chip, reg, val);
1399
1400 spin_unlock_irqrestore(&chip->lock, flags);
1401
1402 return change;
1403}
1404
be9b7e8c
TI		 1405static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
1406 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1407{
1408 int mask = (kcontrol->private_value >> 24) & 0xff;
1409
1410 uinfo->type = mask == 1 ?
1411 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1412 uinfo->count = 2;
1413 uinfo->value.integer.min = 0;
1414 uinfo->value.integer.max = mask;
1415
1416 return 0;
1417}
1418
be9b7e8c
TI		 1419static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
1420 struct snd_ctl_elem_value *ucontrol)
1da177e4 1421{
be9b7e8c 1422 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1423 unsigned long flags;
1424 int left_reg = kcontrol->private_value & 0xff;
1425 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1426 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1427 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1428 int mask = (kcontrol->private_value >> 24) & 0xff;
1429 int invert = (kcontrol->private_value >> 22) & 1;
9e9abb4f 1430
1da177e4
LT		 1431 spin_lock_irqsave(&chip->lock, flags);
1432
9e9abb4f
KH		 1433 ucontrol->value.integer.value[0] =
1434 (chip->image[left_reg] >> shift_left) & mask;
1435 ucontrol->value.integer.value[1] =
1436 (chip->image[right_reg] >> shift_right) & mask;
1da177e4
LT		 1437
1438 spin_unlock_irqrestore(&chip->lock, flags);
1439
1440 if (invert) {
1441 ucontrol->value.integer.value[0] =
1442 (mask - ucontrol->value.integer.value[0]);
1443 ucontrol->value.integer.value[1] =
1444 (mask - ucontrol->value.integer.value[1]);
1445 }
1446
1447 return 0;
1448}
1449
be9b7e8c
TI		 1450static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
1451 struct snd_ctl_elem_value *ucontrol)
1da177e4 1452{
be9b7e8c 1453 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1454 unsigned long flags;
1455 int left_reg = kcontrol->private_value & 0xff;
1456 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1457 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1458 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1459 int mask = (kcontrol->private_value >> 24) & 0xff;
1460 int invert = (kcontrol->private_value >> 22) & 1;
1461 int change;
1462 unsigned short val1, val2;
9e9abb4f 1463
1da177e4
LT		 1464 val1 = ucontrol->value.integer.value[0] & mask;
1465 val2 = ucontrol->value.integer.value[1] & mask;
1466 if (invert) {
1467 val1 = mask - val1;
1468 val2 = mask - val2;
1469 }
1470 val1 <<= shift_left;
1471 val2 <<= shift_right;
1472
1473 spin_lock_irqsave(&chip->lock, flags);
1474
1475 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
1476 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
9e9abb4f
KH		 1477 change = val1 != chip->image[left_reg];
1478 change |= val2 != chip->image[right_reg];
1da177e4
LT		 1479 snd_cs4231_out(chip, left_reg, val1);
1480 snd_cs4231_out(chip, right_reg, val2);
1481
1482 spin_unlock_irqrestore(&chip->lock, flags);
1483
1484 return change;
1485}
1486
1487#define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
9e9abb4f
KH		 1488{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
1489 .info = snd_cs4231_info_single, \
1490 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
1491 .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) }
1492
1493#define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, \
1494 shift_right, mask, invert) \
1495{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
1496 .info = snd_cs4231_info_double, \
1497 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
1498 .private_value = (left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | \
1499 ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) }
1da177e4 1500
32e02a7b 1501static struct snd_kcontrol_new snd_cs4231_controls[] = {
9e9abb4f
KH		 1502CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT,
1503 CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1504CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT,
1505 CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
1506CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN,
1507 CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1508CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN,
1509 CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
1510CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT,
1511 CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1512CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT,
1513 CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
1514CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT,
1515 CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1516CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT,
1517 CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
1da177e4
LT		 1518CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
1519CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
1520CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
1521CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
9e9abb4f
KH		 1522CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0,
1523 15, 0),
1da177e4
LT		 1524{
1525 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1526 .name = "Capture Source",
1527 .info = snd_cs4231_info_mux,
1528 .get = snd_cs4231_get_mux,
1529 .put = snd_cs4231_put_mux,
1530},
9e9abb4f
KH		 1531CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5,
1532 1, 0),
1da177e4
LT		 1533CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
1534CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
1535/* SPARC specific uses of XCTL{0,1} general purpose outputs. */
1536CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
1537CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
1538};
9e9abb4f 1539
32e02a7b 1540static int snd_cs4231_mixer(struct snd_card *card)
1da177e4 1541{
c6c2d57b 1542 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1543 int err, idx;
1544
5e246b85
TI		 1545 if (snd_BUG_ON(!chip || !chip->pcm))
1546 return -EINVAL;
1da177e4 1547
1da177e4
LT		 1548 strcpy(card->mixername, chip->pcm->name);
1549
1550 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
c6c2d57b
KH		 1551 err = snd_ctl_add(card,
1552 snd_ctl_new1(&snd_cs4231_controls[idx], chip));
1553 if (err < 0)
1da177e4
LT		 1554 return err;
1555 }
1556 return 0;
1557}
1558
1559static int dev;
1560
32e02a7b 1561static int cs4231_attach_begin(struct snd_card **rcard)
1da177e4 1562{
be9b7e8c 1563 struct snd_card *card;
c6c2d57b 1564 struct snd_cs4231 *chip;
bd7dd77c 1565 int err;
1da177e4
LT		 1566
1567 *rcard = NULL;
1568
1569 if (dev >= SNDRV_CARDS)
1570 return -ENODEV;
1571
1572 if (!enable[dev]) {
1573 dev++;
1574 return -ENOENT;
1575 }
1576
bd7dd77c
TI		 1577 err = snd_card_create(index[dev], id[dev], THIS_MODULE,
1578 sizeof(struct snd_cs4231), &card);
1579 if (err < 0)
1580 return err;
1da177e4
LT		 1581
1582 strcpy(card->driver, "CS4231");
1583 strcpy(card->shortname, "Sun CS4231");
1584
c6c2d57b
KH		 1585 chip = card->private_data;
1586 chip->card = card;
1587
1da177e4
LT		 1588 *rcard = card;
1589 return 0;
1590}
1591
32e02a7b 1592static int cs4231_attach_finish(struct snd_card *card)
1da177e4 1593{
c6c2d57b 1594 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1595 int err;
1596
c6c2d57b
KH		 1597 err = snd_cs4231_pcm(card);
1598 if (err < 0)
1da177e4
LT		 1599 goto out_err;
1600
c6c2d57b
KH		 1601 err = snd_cs4231_mixer(card);
1602 if (err < 0)
1da177e4
LT		 1603 goto out_err;
1604
c6c2d57b
KH		 1605 err = snd_cs4231_timer(card);
1606 if (err < 0)
1da177e4
LT		 1607 goto out_err;
1608
c6c2d57b
KH		 1609 err = snd_card_register(card);
1610 if (err < 0)
1da177e4
LT		 1611 goto out_err;
1612
afc88ad6 1613 dev_set_drvdata(&chip->op->dev, chip);
1da177e4
LT		 1614
1615 dev++;
1616 return 0;
1617
1618out_err:
1619 snd_card_free(card);
1620 return err;
1621}
1622
1623#ifdef SBUS_SUPPORT
b128254f 1624
7d12e780 1625static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
b128254f
GC		 1626{
1627 unsigned long flags;
1628 unsigned char status;
1629 u32 csr;
be9b7e8c 1630 struct snd_cs4231 *chip = dev_id;
b128254f
GC		 1631
1632 /*This is IRQ is not raised by the cs4231*/
7e52f3da 1633 if (!(__cs4231_readb(chip, CS4231U(chip, STATUS)) & CS4231_GLOBALIRQ))
b128254f
GC		 1634 return IRQ_NONE;
1635
1636 /* ACK the APC interrupt. */
1637 csr = sbus_readl(chip->port + APCCSR);
1638
1639 sbus_writel(csr, chip->port + APCCSR);
1640
9e9abb4f
KH		 1641 if ((csr & APC_PDMA_READY) &&
1642 (csr & APC_PLAY_INT) &&
b128254f
GC		 1643 (csr & APC_XINT_PNVA) &&
1644 !(csr & APC_XINT_EMPT))
1645 snd_cs4231_play_callback(chip);
1646
9e9abb4f
KH		 1647 if ((csr & APC_CDMA_READY) &&
1648 (csr & APC_CAPT_INT) &&
b128254f
GC		 1649 (csr & APC_XINT_CNVA) &&
1650 !(csr & APC_XINT_EMPT))
1651 snd_cs4231_capture_callback(chip);
9e9abb4f 1652
b128254f
GC		 1653 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
1654
1655 if (status & CS4231_TIMER_IRQ) {
1656 if (chip->timer)
1657 snd_timer_interrupt(chip->timer, chip->timer->sticks);
9e9abb4f 1658 }
b128254f
GC		 1659
1660 if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
1661 snd_cs4231_overrange(chip);
1662
1663 /* ACK the CS4231 interrupt. */
1664 spin_lock_irqsave(&chip->lock, flags);
1665 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
1666 spin_unlock_irqrestore(&chip->lock, flags);
1667
d35a1b9e 1668 return IRQ_HANDLED;
b128254f
GC		 1669}
1670
1671/*
1672 * SBUS DMA routines
1673 */
1674
9e9abb4f
KH		 1675static int sbus_dma_request(struct cs4231_dma_control *dma_cont,
1676 dma_addr_t bus_addr, size_t len)
b128254f
GC		 1677{
1678 unsigned long flags;
1679 u32 test, csr;
1680 int err;
be9b7e8c 1681 struct sbus_dma_info *base = &dma_cont->sbus_info;
9e9abb4f 1682
b128254f
GC		 1683 if (len >= (1 << 24))
1684 return -EINVAL;
1685 spin_lock_irqsave(&base->lock, flags);
1686 csr = sbus_readl(base->regs + APCCSR);
1687 err = -EINVAL;
1688 test = APC_CDMA_READY;
9e9abb4f 1689 if (base->dir == APC_PLAY)
b128254f
GC		 1690 test = APC_PDMA_READY;
1691 if (!(csr & test))
1692 goto out;
1693 err = -EBUSY;
b128254f 1694 test = APC_XINT_CNVA;
9e9abb4f 1695 if (base->dir == APC_PLAY)
b128254f
GC		 1696 test = APC_XINT_PNVA;
1697 if (!(csr & test))
1698 goto out;
1699 err = 0;
1700 sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
1701 sbus_writel(len, base->regs + base->dir + APCNC);
1702out:
1703 spin_unlock_irqrestore(&base->lock, flags);
1704 return err;
1705}
1706
be9b7e8c 1707static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
b128254f
GC		 1708{
1709 unsigned long flags;
1710 u32 csr, test;
be9b7e8c 1711 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f
GC		 1712
1713 spin_lock_irqsave(&base->lock, flags);
1714 csr = sbus_readl(base->regs + APCCSR);
1715 test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
1716 APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
1717 APC_XINT_PENA;
9e9abb4f 1718 if (base->dir == APC_RECORD)
b128254f
GC		 1719 test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
1720 APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
1721 csr |= test;
1722 sbus_writel(csr, base->regs + APCCSR);
1723 spin_unlock_irqrestore(&base->lock, flags);
1724}
1725
be9b7e8c 1726static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
b128254f
GC		 1727{
1728 unsigned long flags;
1729 u32 csr, shift;
be9b7e8c 1730 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f
GC		 1731
1732 spin_lock_irqsave(&base->lock, flags);
1733 if (!on) {
d35a1b9e
GC		 1734 sbus_writel(0, base->regs + base->dir + APCNC);
1735 sbus_writel(0, base->regs + base->dir + APCNVA);
9e9abb4f 1736 if (base->dir == APC_PLAY) {
3daadf33
GC		 1737 sbus_writel(0, base->regs + base->dir + APCC);
1738 sbus_writel(0, base->regs + base->dir + APCVA);
1739 }
d35a1b9e 1740
3daadf33 1741 udelay(1200);
9e9abb4f 1742 }
b128254f
GC		 1743 csr = sbus_readl(base->regs + APCCSR);
1744 shift = 0;
9e9abb4f 1745 if (base->dir == APC_PLAY)
b128254f
GC		 1746 shift = 1;
1747 if (on)
1748 csr &= ~(APC_CPAUSE << shift);
1749 else
9e9abb4f 1750 csr |= (APC_CPAUSE << shift);
b128254f
GC		 1751 sbus_writel(csr, base->regs + APCCSR);
1752 if (on)
1753 csr |= (APC_CDMA_READY << shift);
1754 else
1755 csr &= ~(APC_CDMA_READY << shift);
1756 sbus_writel(csr, base->regs + APCCSR);
9e9abb4f 1757
b128254f
GC		 1758 spin_unlock_irqrestore(&base->lock, flags);
1759}
1760
be9b7e8c 1761static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
b128254f 1762{
be9b7e8c 1763 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f 1764
9e9abb4f 1765 return sbus_readl(base->regs + base->dir + APCVA);
b128254f
GC		 1766}
1767
b128254f
GC		 1768/*
1769 * Init and exit routines
1770 */
1771
be9b7e8c 1772static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
1da177e4 1773{
2dc11581 1774 struct platform_device *op = chip->op;
ae251031 1775
1da177e4
LT		 1776 if (chip->irq[0])
1777 free_irq(chip->irq[0], chip);
1778
1779 if (chip->port)
ae251031 1780 of_iounmap(&op->resource[0], chip->port, chip->regs_size);
1da177e4 1781
1da177e4
LT		 1782 return 0;
1783}
1784
be9b7e8c 1785static int snd_cs4231_sbus_dev_free(struct snd_device *device)
1da177e4 1786{
be9b7e8c 1787 struct snd_cs4231 *cp = device->device_data;
1da177e4
LT		 1788
1789 return snd_cs4231_sbus_free(cp);
1790}
1791
be9b7e8c 1792static struct snd_device_ops snd_cs4231_sbus_dev_ops = {
1da177e4
LT		 1793 .dev_free = snd_cs4231_sbus_dev_free,
1794};
1795
32e02a7b
BP		 1796static int snd_cs4231_sbus_create(struct snd_card *card,
1797 struct platform_device *op,
1798 int dev)
1da177e4 1799{
c6c2d57b 1800 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1801 int err;
1802
1da177e4 1803 spin_lock_init(&chip->lock);
b128254f
GC		 1804 spin_lock_init(&chip->c_dma.sbus_info.lock);
1805 spin_lock_init(&chip->p_dma.sbus_info.lock);
12aa7579
IM		 1806 mutex_init(&chip->mce_mutex);
1807 mutex_init(&chip->open_mutex);
afc88ad6 1808 chip->op = op;
ae251031 1809 chip->regs_size = resource_size(&op->resource[0]);
1da177e4
LT		 1810 memcpy(&chip->image, &snd_cs4231_original_image,
1811 sizeof(snd_cs4231_original_image));
1812
ae251031
DM		 1813 chip->port = of_ioremap(&op->resource[0], 0,
1814 chip->regs_size, "cs4231");
1da177e4 1815 if (!chip->port) {
a131430c 1816 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
1da177e4
LT		 1817 return -EIO;
1818 }
1819
b128254f
GC		 1820 chip->c_dma.sbus_info.regs = chip->port;
1821 chip->p_dma.sbus_info.regs = chip->port;
1822 chip->c_dma.sbus_info.dir = APC_RECORD;
1823 chip->p_dma.sbus_info.dir = APC_PLAY;
1824
1825 chip->p_dma.prepare = sbus_dma_prepare;
1826 chip->p_dma.enable = sbus_dma_enable;
1827 chip->p_dma.request = sbus_dma_request;
1828 chip->p_dma.address = sbus_dma_addr;
b128254f
GC		 1829
1830 chip->c_dma.prepare = sbus_dma_prepare;
1831 chip->c_dma.enable = sbus_dma_enable;
1832 chip->c_dma.request = sbus_dma_request;
1833 chip->c_dma.address = sbus_dma_addr;
5a820fa7 1834
1636f8ac 1835 if (request_irq(op->archdata.irqs[0], snd_cs4231_sbus_interrupt,
65ca68b3 1836 IRQF_SHARED, "cs4231", chip)) {
c6387a48 1837 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
1636f8ac 1838 dev, op->archdata.irqs[0]);
1da177e4
LT		 1839 snd_cs4231_sbus_free(chip);
1840 return -EBUSY;
1841 }
1636f8ac 1842 chip->irq[0] = op->archdata.irqs[0];
1da177e4
LT		 1843
1844 if (snd_cs4231_probe(chip) < 0) {
1845 snd_cs4231_sbus_free(chip);
1846 return -ENODEV;
1847 }
1848 snd_cs4231_init(chip);
1849
1850 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
1851 chip, &snd_cs4231_sbus_dev_ops)) < 0) {
1852 snd_cs4231_sbus_free(chip);
1853 return err;
1854 }
1855
1da177e4
LT		 1856 return 0;
1857}
1858
32e02a7b 1859static int cs4231_sbus_probe(struct platform_device *op)
1da177e4 1860{
ae251031 1861 struct resource *rp = &op->resource[0];
be9b7e8c 1862 struct snd_card *card;
1da177e4
LT		 1863 int err;
1864
1865 err = cs4231_attach_begin(&card);
1866 if (err)
1867 return err;
1868
5863aa65 1869 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
1da177e4
LT		 1870 card->shortname,
1871 rp->flags & 0xffL,
aa0a2ddc 1872 (unsigned long long)rp->start,
1636f8ac 1873 op->archdata.irqs[0]);
1da177e4 1874
ae251031 1875 err = snd_cs4231_sbus_create(card, op, dev);
c6c2d57b 1876 if (err < 0) {
1da177e4
LT		 1877 snd_card_free(card);
1878 return err;
1879 }
1880
c6c2d57b 1881 return cs4231_attach_finish(card);
1da177e4
LT		 1882}
1883#endif
1884
1885#ifdef EBUS_SUPPORT
b128254f 1886
9e9abb4f
KH		 1887static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event,
1888 void *cookie)
b128254f 1889{
be9b7e8c 1890 struct snd_cs4231 *chip = cookie;
9e9abb4f 1891
b128254f
GC		 1892 snd_cs4231_play_callback(chip);
1893}
1894
9e9abb4f
KH		 1895static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p,
1896 int event, void *cookie)
b128254f 1897{
be9b7e8c 1898 struct snd_cs4231 *chip = cookie;
b128254f
GC		 1899
1900 snd_cs4231_capture_callback(chip);
1901}
1902
1903/*
1904 * EBUS DMA wrappers
1905 */
1906
9e9abb4f
KH		 1907static int _ebus_dma_request(struct cs4231_dma_control *dma_cont,
1908 dma_addr_t bus_addr, size_t len)
b128254f
GC		 1909{
1910 return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
1911}
1912
be9b7e8c 1913static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
b128254f
GC		 1914{
1915 ebus_dma_enable(&dma_cont->ebus_info, on);
1916}
1917
be9b7e8c 1918static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
b128254f
GC		 1919{
1920 ebus_dma_prepare(&dma_cont->ebus_info, dir);
1921}
1922
be9b7e8c 1923static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
b128254f
GC		 1924{
1925 return ebus_dma_addr(&dma_cont->ebus_info);
1926}
1927
b128254f
GC		 1928/*
1929 * Init and exit routines
1930 */
1931
be9b7e8c 1932static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
1da177e4 1933{
2dc11581 1934 struct platform_device *op = chip->op;
afc88ad6 1935
b128254f
GC		 1936 if (chip->c_dma.ebus_info.regs) {
1937 ebus_dma_unregister(&chip->c_dma.ebus_info);
afc88ad6 1938 of_iounmap(&op->resource[2], chip->c_dma.ebus_info.regs, 0x10);
1da177e4 1939 }
b128254f
GC		 1940 if (chip->p_dma.ebus_info.regs) {
1941 ebus_dma_unregister(&chip->p_dma.ebus_info);
afc88ad6 1942 of_iounmap(&op->resource[1], chip->p_dma.ebus_info.regs, 0x10);
1da177e4
LT		 1943 }
1944
1945 if (chip->port)
afc88ad6 1946 of_iounmap(&op->resource[0], chip->port, 0x10);
1da177e4 1947
1da177e4
LT		 1948 return 0;
1949}
1950
be9b7e8c 1951static int snd_cs4231_ebus_dev_free(struct snd_device *device)
1da177e4 1952{
be9b7e8c 1953 struct snd_cs4231 *cp = device->device_data;
1da177e4
LT		 1954
1955 return snd_cs4231_ebus_free(cp);
1956}
1957
be9b7e8c 1958static struct snd_device_ops snd_cs4231_ebus_dev_ops = {
1da177e4
LT		 1959 .dev_free = snd_cs4231_ebus_dev_free,
1960};
1961
32e02a7b
BP		 1962static int snd_cs4231_ebus_create(struct snd_card *card,
1963 struct platform_device *op,
1964 int dev)
1da177e4 1965{
c6c2d57b 1966 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1967 int err;
1968
1da177e4 1969 spin_lock_init(&chip->lock);
b128254f
GC		 1970 spin_lock_init(&chip->c_dma.ebus_info.lock);
1971 spin_lock_init(&chip->p_dma.ebus_info.lock);
12aa7579
IM		 1972 mutex_init(&chip->mce_mutex);
1973 mutex_init(&chip->open_mutex);
1da177e4 1974 chip->flags |= CS4231_FLAG_EBUS;
afc88ad6 1975 chip->op = op;
1da177e4
LT		 1976 memcpy(&chip->image, &snd_cs4231_original_image,
1977 sizeof(snd_cs4231_original_image));
b128254f
GC		 1978 strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
1979 chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
1980 chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
1981 chip->c_dma.ebus_info.client_cookie = chip;
1636f8ac 1982 chip->c_dma.ebus_info.irq = op->archdata.irqs[0];
b128254f
GC		 1983 strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
1984 chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
1985 chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
1986 chip->p_dma.ebus_info.client_cookie = chip;
1636f8ac 1987 chip->p_dma.ebus_info.irq = op->archdata.irqs[1];
b128254f
GC		 1988
1989 chip->p_dma.prepare = _ebus_dma_prepare;
1990 chip->p_dma.enable = _ebus_dma_enable;
1991 chip->p_dma.request = _ebus_dma_request;
1992 chip->p_dma.address = _ebus_dma_addr;
b128254f
GC		 1993
1994 chip->c_dma.prepare = _ebus_dma_prepare;
1995 chip->c_dma.enable = _ebus_dma_enable;
1996 chip->c_dma.request = _ebus_dma_request;
1997 chip->c_dma.address = _ebus_dma_addr;
1da177e4 1998
afc88ad6
DM		 1999 chip->port = of_ioremap(&op->resource[0], 0, 0x10, "cs4231");
2000 chip->p_dma.ebus_info.regs =
2001 of_ioremap(&op->resource[1], 0, 0x10, "cs4231_pdma");
2002 chip->c_dma.ebus_info.regs =
2003 of_ioremap(&op->resource[2], 0, 0x10, "cs4231_cdma");
9e9abb4f
KH		 2004 if (!chip->port || !chip->p_dma.ebus_info.regs ||
2005 !chip->c_dma.ebus_info.regs) {
1da177e4 2006 snd_cs4231_ebus_free(chip);
a131430c 2007 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
1da177e4
LT		 2008 return -EIO;
2009 }
2010
b128254f 2011 if (ebus_dma_register(&chip->c_dma.ebus_info)) {
1da177e4 2012 snd_cs4231_ebus_free(chip);
9e9abb4f
KH		 2013 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n",
2014 dev);
1da177e4
LT		 2015 return -EBUSY;
2016 }
b128254f 2017 if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
1da177e4 2018 snd_cs4231_ebus_free(chip);
9e9abb4f
KH		 2019 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n",
2020 dev);
1da177e4
LT		 2021 return -EBUSY;
2022 }
2023
b128254f 2024 if (ebus_dma_register(&chip->p_dma.ebus_info)) {
1da177e4 2025 snd_cs4231_ebus_free(chip);
9e9abb4f
KH		 2026 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n",
2027 dev);
1da177e4
LT		 2028 return -EBUSY;
2029 }
b128254f 2030 if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
1da177e4 2031 snd_cs4231_ebus_free(chip);
a131430c 2032 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
1da177e4
LT		 2033 return -EBUSY;
2034 }
2035
2036 if (snd_cs4231_probe(chip) < 0) {
2037 snd_cs4231_ebus_free(chip);
2038 return -ENODEV;
2039 }
2040 snd_cs4231_init(chip);
2041
2042 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2043 chip, &snd_cs4231_ebus_dev_ops)) < 0) {
2044 snd_cs4231_ebus_free(chip);
2045 return err;
2046 }
2047
1da177e4
LT		 2048 return 0;
2049}
2050
32e02a7b 2051static int cs4231_ebus_probe(struct platform_device *op)
1da177e4 2052{
be9b7e8c 2053 struct snd_card *card;
1da177e4
LT		 2054 int err;
2055
2056 err = cs4231_attach_begin(&card);
2057 if (err)
2058 return err;
2059
3f4528d6 2060 sprintf(card->longname, "%s at 0x%llx, irq %d",
1da177e4 2061 card->shortname,
afc88ad6 2062 op->resource[0].start,
1636f8ac 2063 op->archdata.irqs[0]);
1da177e4 2064
afc88ad6 2065 err = snd_cs4231_ebus_create(card, op, dev);
c6c2d57b 2066 if (err < 0) {
1da177e4
LT		 2067 snd_card_free(card);
2068 return err;
2069 }
2070
c6c2d57b 2071 return cs4231_attach_finish(card);
1da177e4
LT		 2072}
2073#endif
2074
32e02a7b 2075static int cs4231_probe(struct platform_device *op)
afc88ad6
DM		 2076{
2077#ifdef EBUS_SUPPORT
61c7a080 2078 if (!strcmp(op->dev.of_node->parent->name, "ebus"))
f07eb223 2079 return cs4231_ebus_probe(op);
afc88ad6 2080#endif
1da177e4 2081#ifdef SBUS_SUPPORT
61c7a080
GL		 2082 if (!strcmp(op->dev.of_node->parent->name, "sbus") ||
2083 !strcmp(op->dev.of_node->parent->name, "sbi"))
f07eb223 2084 return cs4231_sbus_probe(op);
afc88ad6
DM		 2085#endif
2086 return -ENODEV;
2087}
2088
32e02a7b 2089static int cs4231_remove(struct platform_device *op)
afc88ad6
DM		 2090{
2091 struct snd_cs4231 *chip = dev_get_drvdata(&op->dev);
2092
2093 snd_card_free(chip->card);
2094
2095 return 0;
2096}
2097
fd098316 2098static const struct of_device_id cs4231_match[] = {
ae251031
DM		 2099 {
2100 .name = "SUNW,CS4231",
2101 },
afc88ad6
DM		 2102 {
2103 .name = "audio",
2104 .compatible = "SUNW,CS4231",
2105 },
ae251031
DM		 2106 {},
2107};
2108
2109MODULE_DEVICE_TABLE(of, cs4231_match);
2110
f07eb223 2111static struct platform_driver cs4231_driver = {
4018294b
GL		 2112 .driver = {
2113 .name = "audio",
2114 .owner = THIS_MODULE,
2115 .of_match_table = cs4231_match,
2116 },
ae251031 2117 .probe = cs4231_probe,
32e02a7b 2118 .remove = cs4231_remove,
ae251031 2119};
ae251031 2120
a09452ee 2121module_platform_driver(cs4231_driver);
kernel source for telekom puls (alcatel/mediatek)