[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa2xx-i2s.c

/*
 * pxa2xx-i2s.c  --  ALSA Soc Audio Layer
 *
 * Copyright 2005 Wolfson Microelectronics PLC.
 * Author: Liam Girdwood
 *         lrg@slimlogic.co.uk
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/pxa2xx-lib.h>

#include <mach/hardware.h>
#include <mach/dma.h>
#include <mach/audio.h>

#include "pxa2xx-pcm.h"
#include "pxa2xx-i2s.h"

/*
 * I2S Controller Register and Bit Definitions
 */
#define SACR0		__REG(0x40400000)  /* Global Control Register */
#define SACR1		__REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
#define SASR0		__REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
#define SAIMR		__REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
#define SAICR		__REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
#define SADIV		__REG(0x40400060)  /* Audio Clock Divider Register. */
#define SADR		__REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */

#define SACR0_RFTH(x)	((x) << 12)	/* Rx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_TFTH(x)	((x) << 8)	/* Tx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_STRF	(1 << 5)	/* FIFO Select for EFWR Special Function */
#define SACR0_EFWR	(1 << 4)	/* Enable EFWR Function  */
#define SACR0_RST	(1 << 3)	/* FIFO, i2s Register Reset */
#define SACR0_BCKD	(1 << 2) 	/* Bit Clock Direction */
#define SACR0_ENB	(1 << 0)	/* Enable I2S Link */
#define SACR1_ENLBF	(1 << 5)	/* Enable Loopback */
#define SACR1_DRPL	(1 << 4) 	/* Disable Replaying Function */
#define SACR1_DREC	(1 << 3)	/* Disable Recording Function */
#define SACR1_AMSL	(1 << 0)	/* Specify Alternate Mode */

#define SASR0_I2SOFF	(1 << 7)	/* Controller Status */
#define SASR0_ROR	(1 << 6)	/* Rx FIFO Overrun */
#define SASR0_TUR	(1 << 5)	/* Tx FIFO Underrun */
#define SASR0_RFS	(1 << 4)	/* Rx FIFO Service Request */
#define SASR0_TFS	(1 << 3)	/* Tx FIFO Service Request */
#define SASR0_BSY	(1 << 2)	/* I2S Busy */
#define SASR0_RNE	(1 << 1)	/* Rx FIFO Not Empty */
#define SASR0_TNF	(1 << 0) 	/* Tx FIFO Not Empty */

#define SAICR_ROR	(1 << 6)	/* Clear Rx FIFO Overrun Interrupt */
#define SAICR_TUR	(1 << 5)	/* Clear Tx FIFO Underrun Interrupt */

#define SAIMR_ROR	(1 << 6)	/* Enable Rx FIFO Overrun Condition Interrupt */
#define SAIMR_TUR	(1 << 5)	/* Enable Tx FIFO Underrun Condition Interrupt */
#define SAIMR_RFS	(1 << 4)	/* Enable Rx FIFO Service Interrupt */
#define SAIMR_TFS	(1 << 3)	/* Enable Tx FIFO Service Interrupt */

struct pxa_i2s_port {
	u32 sadiv;
	u32 sacr0;
	u32 sacr1;
	u32 saimr;
	int master;
	u32 fmt;
};
static struct pxa_i2s_port pxa_i2s;
static struct clk *clk_i2s;

static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
	.name			= "I2S PCM Stereo out",
	.dev_addr		= __PREG(SADR),
	.drcmr			= &DRCMR(3),
	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
	.name			= "I2S PCM Stereo in",
	.dev_addr		= __PREG(SADR),
	.drcmr			= &DRCMR(2),
	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
			      struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;

	if (IS_ERR(clk_i2s))
		return PTR_ERR(clk_i2s);

	if (!cpu_dai->active)
		SACR0 = 0;

	return 0;
}

/* wait for I2S controller to be ready */
static int pxa_i2s_wait(void)
{
	int i;

	/* flush the Rx FIFO */
	for(i = 0; i < 16; i++)
		SADR;
	return 0;
}

static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
		unsigned int fmt)
{
	/* interface format */
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		pxa_i2s.fmt = 0;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		pxa_i2s.fmt = SACR1_AMSL;
		break;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		pxa_i2s.master = 1;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		pxa_i2s.master = 0;
		break;
	default:
		break;
	}
	return 0;
}

static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
		int clk_id, unsigned int freq, int dir)
{
	if (clk_id != PXA2XX_I2S_SYSCLK)
		return -ENODEV;

	return 0;
}

static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct pxa2xx_pcm_dma_params *dma_data;

	BUG_ON(IS_ERR(clk_i2s));
	clk_enable(clk_i2s);
	dai->private_data = dai;
	pxa_i2s_wait();

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dma_data = &pxa2xx_i2s_pcm_stereo_out;
	else
		dma_data = &pxa2xx_i2s_pcm_stereo_in;

	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);

	/* is port used by another stream */
	if (!(SACR0 & SACR0_ENB)) {
		SACR0 = 0;
		if (pxa_i2s.master)
			SACR0 |= SACR0_BCKD;

		SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
		SACR1 |= pxa_i2s.fmt;
	}
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		SAIMR |= SAIMR_TFS;
	else
		SAIMR |= SAIMR_RFS;

	switch (params_rate(params)) {
	case 8000:
		SADIV = 0x48;
		break;
	case 11025:
		SADIV = 0x34;
		break;
	case 16000:
		SADIV = 0x24;
		break;
	case 22050:
		SADIV = 0x1a;
		break;
	case 44100:
		SADIV = 0xd;
		break;
	case 48000:
		SADIV = 0xc;
		break;
	case 96000: /* not in manual and possibly slightly inaccurate */
		SADIV = 0x6;
		break;
	}

	return 0;
}

static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			      struct snd_soc_dai *dai)
{
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			SACR1 &= ~SACR1_DRPL;
		else
			SACR1 &= ~SACR1_DREC;
		SACR0 |= SACR0_ENB;
		break;
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
				struct snd_soc_dai *dai)
{
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		SACR1 |= SACR1_DRPL;
		SAIMR &= ~SAIMR_TFS;
	} else {
		SACR1 |= SACR1_DREC;
		SAIMR &= ~SAIMR_RFS;
	}

	if ((SACR1 & (SACR1_DREC | SACR1_DRPL)) == (SACR1_DREC | SACR1_DRPL)) {
		SACR0 &= ~SACR0_ENB;
		pxa_i2s_wait();
		if (dai->private_data != NULL) {
			clk_disable(clk_i2s);
			dai->private_data = NULL;
		}
	}
}

#ifdef CONFIG_PM
static int pxa2xx_i2s_suspend(struct snd_soc_dai *dai)
{
	/* store registers */
	pxa_i2s.sacr0 = SACR0;
	pxa_i2s.sacr1 = SACR1;
	pxa_i2s.saimr = SAIMR;
	pxa_i2s.sadiv = SADIV;

	/* deactivate link */
	SACR0 &= ~SACR0_ENB;
	pxa_i2s_wait();
	return 0;
}

static int pxa2xx_i2s_resume(struct snd_soc_dai *dai)
{
	pxa_i2s_wait();

	SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB;
	SACR1 = pxa_i2s.sacr1;
	SAIMR = pxa_i2s.saimr;
	SADIV = pxa_i2s.sadiv;

	SACR0 = pxa_i2s.sacr0;

	return 0;
}

#else
#define pxa2xx_i2s_suspend	NULL
#define pxa2xx_i2s_resume	NULL
#endif

#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
		SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
		SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)

static struct snd_soc_dai_ops pxa_i2s_dai_ops = {
	.startup	= pxa2xx_i2s_startup,
	.shutdown	= pxa2xx_i2s_shutdown,
	.trigger	= pxa2xx_i2s_trigger,
	.hw_params	= pxa2xx_i2s_hw_params,
	.set_fmt	= pxa2xx_i2s_set_dai_fmt,
	.set_sysclk	= pxa2xx_i2s_set_dai_sysclk,
};

struct snd_soc_dai pxa_i2s_dai = {
	.name = "pxa2xx-i2s",
	.id = 0,
	.suspend = pxa2xx_i2s_suspend,
	.resume = pxa2xx_i2s_resume,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = PXA2XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = PXA2XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = &pxa_i2s_dai_ops,
	.symmetric_rates = 1,
};

EXPORT_SYMBOL_GPL(pxa_i2s_dai);

static int pxa2xx_i2s_probe(struct platform_device *dev)
{
	int ret;

	clk_i2s = clk_get(&dev->dev, "I2SCLK");
	if (IS_ERR(clk_i2s))
		return PTR_ERR(clk_i2s);

	pxa_i2s_dai.dev = &dev->dev;
	pxa_i2s_dai.private_data = NULL;
	ret = snd_soc_register_dai(&pxa_i2s_dai);
	if (ret != 0)
		clk_put(clk_i2s);

	/*
	 * PXA Developer's Manual:
	 * If SACR0[ENB] is toggled in the middle of a normal operation,
	 * the SACR0[RST] bit must also be set and cleared to reset all
	 * I2S controller registers.
	 */
	SACR0 = SACR0_RST;
	SACR0 = 0;
	/* Make sure RPL and REC are disabled */
	SACR1 = SACR1_DRPL | SACR1_DREC;
	/* Along with FIFO servicing */
	SAIMR &= ~(SAIMR_RFS | SAIMR_TFS);

	return ret;
}

static int __devexit pxa2xx_i2s_remove(struct platform_device *dev)
{
	snd_soc_unregister_dai(&pxa_i2s_dai);
	clk_put(clk_i2s);
	clk_i2s = ERR_PTR(-ENOENT);
	return 0;
}

static struct platform_driver pxa2xx_i2s_driver = {
	.probe = pxa2xx_i2s_probe,
	.remove = __devexit_p(pxa2xx_i2s_remove),

	.driver = {
		.name = "pxa2xx-i2s",
		.owner = THIS_MODULE,
	},
};

static int __init pxa2xx_i2s_init(void)
{
	clk_i2s = ERR_PTR(-ENOENT);
	return platform_driver_register(&pxa2xx_i2s_driver);
}

static void __exit pxa2xx_i2s_exit(void)
{
	platform_driver_unregister(&pxa2xx_i2s_driver);
}

module_init(pxa2xx_i2s_init);
module_exit(pxa2xx_i2s_exit);

/* Module information */
MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
3e7cc3d3 LG	1	/*
	2	* pxa2xx-i2s.c -- ALSA Soc Audio Layer
	3	*
	4	* Copyright 2005 Wolfson Microelectronics PLC.
	5	* Author: Liam Girdwood
d331124d	6	* lrg@slimlogic.co.uk
3e7cc3d3 LG	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
3e7cc3d3 LG	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/module.h>
	16	#include <linux/device.h>
	17	#include <linux/delay.h>
5a2cc50f	18	#include <linux/clk.h>
6e5ea701	19	#include <linux/platform_device.h>
3e7cc3d3 LG	20	#include <sound/core.h>
	21	#include <sound/pcm.h>
	22	#include <sound/initval.h>
	23	#include <sound/soc.h>
a6d77317	24	#include <sound/pxa2xx-lib.h>
3e7cc3d3	25
a09e64fb	26	#include <mach/hardware.h>
7ebc8d56	27	#include <mach/dma.h>
a09e64fb	28	#include <mach/audio.h>
3e7cc3d3 LG	29
3e7cc3d3 LG	30	#include "pxa2xx-pcm.h"
eaff2ae7	31	#include "pxa2xx-i2s.h"
3e7cc3d3	32
52358ba3 EM	33	/*
	34	* I2S Controller Register and Bit Definitions
	35	*/
	36	#define SACR0 __REG(0x40400000) /* Global Control Register */
	37	#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
	38	#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
	39	#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
	40	#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
	41	#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
	42	#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
	43
	44	#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
	45	#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
	46	#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
	47	#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
	48	#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
	49	#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
	50	#define SACR0_ENB (1 << 0) /* Enable I2S Link */
	51	#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
	52	#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
	53	#define SACR1_DREC (1 << 3) /* Disable Recording Function */
	54	#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
	55
	56	#define SASR0_I2SOFF (1 << 7) /* Controller Status */
	57	#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
	58	#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
	59	#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
	60	#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
	61	#define SASR0_BSY (1 << 2) /* I2S Busy */
	62	#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
	63	#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
	64
	65	#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
	66	#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
	67
	68	#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
	69	#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
	70	#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
	71	#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
a6d77317	72
3e7cc3d3 LG	73	struct pxa_i2s_port {
	74	u32 sadiv;
	75	u32 sacr0;
	76	u32 sacr1;
	77	u32 saimr;
	78	int master;
eaff2ae7	79	u32 fmt;
3e7cc3d3 LG	80	};
3e7cc3d3 LG	81	static struct pxa_i2s_port pxa_i2s;
5a2cc50f	82	static struct clk *clk_i2s;
3e7cc3d3	83
3e7cc3d3 LG	84	static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
	85	.name = "I2S PCM Stereo out",
	86	.dev_addr = __PREG(SADR),
87f3dd77	87	.drcmr = &DRCMR(3),
3e7cc3d3 LG	88	.dcmd = DCMD_INCSRCADDR \| DCMD_FLOWTRG \|
	89	DCMD_BURST32 \| DCMD_WIDTH4,
	90	};
	91
	92	static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
	93	.name = "I2S PCM Stereo in",
	94	.dev_addr = __PREG(SADR),
87f3dd77	95	.drcmr = &DRCMR(2),
3e7cc3d3 LG	96	.dcmd = DCMD_INCTRGADDR \| DCMD_FLOWSRC \|
	97	DCMD_BURST32 \| DCMD_WIDTH4,
	98	};
	99
dee89c4d MB	100	static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
dee89c4d MB	101	struct snd_soc_dai *dai)
3e7cc3d3 LG	102	{
3e7cc3d3 LG	103	struct snd_soc_pcm_runtime *rtd = substream->private_data;
917f93ac	104	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
3e7cc3d3	105
5a2cc50f	106	if (IS_ERR(clk_i2s))
	107	return PTR_ERR(clk_i2s);
	108
b243b77c	109	if (!cpu_dai->active)
3e7cc3d3	110	SACR0 = 0;
3e7cc3d3 LG	111
	112	return 0;
	113	}
	114
	115	/* wait for I2S controller to be ready */
	116	static int pxa_i2s_wait(void)
	117	{
	118	int i;
	119
	120	/* flush the Rx FIFO */
	121	for(i = 0; i < 16; i++)
	122	SADR;
	123	return 0;
	124	}
	125
917f93ac	126	static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
eaff2ae7	127	unsigned int fmt)
3e7cc3d3	128	{
eaff2ae7 PZ	129	/* interface format */
	130	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	131	case SND_SOC_DAIFMT_I2S:
	132	pxa_i2s.fmt = 0;
	133	break;
	134	case SND_SOC_DAIFMT_LEFT_J:
	135	pxa_i2s.fmt = SACR1_AMSL;
	136	break;
	137	}
3e7cc3d3	138
eaff2ae7 PZ	139	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
eaff2ae7 PZ	140	case SND_SOC_DAIFMT_CBS_CFS:
3e7cc3d3	141	pxa_i2s.master = 1;
eaff2ae7 PZ	142	break;
	143	case SND_SOC_DAIFMT_CBM_CFS:
	144	pxa_i2s.master = 0;
	145	break;
	146	default:
	147	break;
	148	}
	149	return 0;
	150	}
3e7cc3d3	151
917f93ac	152	static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
eaff2ae7 PZ	153	int clk_id, unsigned int freq, int dir)
	154	{
	155	if (clk_id != PXA2XX_I2S_SYSCLK)
	156	return -ENODEV;
	157
eaff2ae7 PZ	158	return 0;
	159	}
	160
	161	static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	162	struct snd_pcm_hw_params *params,
dee89c4d MB	163	struct snd_soc_dai *dai)
eaff2ae7 PZ	164	{
eaff2ae7 PZ	165	struct snd_soc_pcm_runtime *rtd = substream->private_data;
917f93ac	166	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
5f712b2b	167	struct pxa2xx_pcm_dma_params *dma_data;
eaff2ae7	168
6e5ea701	169	BUG_ON(IS_ERR(clk_i2s));
5a2cc50f	170	clk_enable(clk_i2s);
da9ff1f7	171	dai->private_data = dai;
3e7cc3d3 LG	172	pxa_i2s_wait();
	173
	174	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5f712b2b	175	dma_data = &pxa2xx_i2s_pcm_stereo_out;
3e7cc3d3	176	else
5f712b2b DM	177	dma_data = &pxa2xx_i2s_pcm_stereo_in;
	178
	179	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
3e7cc3d3 LG	180
	181	/* is port used by another stream */
	182	if (!(SACR0 & SACR0_ENB)) {
3e7cc3d3	183	SACR0 = 0;
3e7cc3d3 LG	184	if (pxa_i2s.master)
	185	SACR0 \|= SACR0_BCKD;
	186
	187	SACR0 \|= SACR0_RFTH(14) \| SACR0_TFTH(1);
eaff2ae7	188	SACR1 \|= pxa_i2s.fmt;
3e7cc3d3 LG	189	}
	190	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	191	SAIMR \|= SAIMR_TFS;
	192	else
	193	SAIMR \|= SAIMR_RFS;
	194
eaff2ae7 PZ	195	switch (params_rate(params)) {
	196	case 8000:
	197	SADIV = 0x48;
	198	break;
	199	case 11025:
	200	SADIV = 0x34;
	201	break;
	202	case 16000:
	203	SADIV = 0x24;
	204	break;
	205	case 22050:
	206	SADIV = 0x1a;
	207	break;
	208	case 44100:
	209	SADIV = 0xd;
	210	break;
	211	case 48000:
	212	SADIV = 0xc;
	213	break;
	214	case 96000: /* not in manual and possibly slightly inaccurate */
	215	SADIV = 0x6;
	216	break;
	217	}
	218
3e7cc3d3 LG	219	return 0;
	220	}
	221
dee89c4d MB	222	static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	223	struct snd_soc_dai *dai)
3e7cc3d3 LG	224	{
	225	int ret = 0;
	226
	227	switch (cmd) {
	228	case SNDRV_PCM_TRIGGER_START:
34555c10 KB	229	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	230	SACR1 &= ~SACR1_DRPL;
	231	else
	232	SACR1 &= ~SACR1_DREC;
3e7cc3d3 LG	233	SACR0 \|= SACR0_ENB;
	234	break;
	235	case SNDRV_PCM_TRIGGER_RESUME:
	236	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	237	case SNDRV_PCM_TRIGGER_STOP:
	238	case SNDRV_PCM_TRIGGER_SUSPEND:
	239	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	240	break;
	241	default:
	242	ret = -EINVAL;
	243	}
	244
	245	return ret;
	246	}
	247
dee89c4d MB	248	static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	249	struct snd_soc_dai *dai)
3e7cc3d3 LG	250	{
	251	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	252	SACR1 \|= SACR1_DRPL;
	253	SAIMR &= ~SAIMR_TFS;
	254	} else {
	255	SACR1 \|= SACR1_DREC;
	256	SAIMR &= ~SAIMR_RFS;
	257	}
	258
34555c10	259	if ((SACR1 & (SACR1_DREC \| SACR1_DRPL)) == (SACR1_DREC \| SACR1_DRPL)) {
3e7cc3d3 LG	260	SACR0 &= ~SACR0_ENB;
3e7cc3d3 LG	261	pxa_i2s_wait();
da9ff1f7 MB	262	if (dai->private_data != NULL) {
	263	clk_disable(clk_i2s);
	264	dai->private_data = NULL;
	265	}
3e7cc3d3 LG	266	}
	267	}
	268
	269	#ifdef CONFIG_PM
dc7d7b83	270	static int pxa2xx_i2s_suspend(struct snd_soc_dai *dai)
3e7cc3d3	271	{
3e7cc3d3 LG	272	/* store registers */
	273	pxa_i2s.sacr0 = SACR0;
	274	pxa_i2s.sacr1 = SACR1;
	275	pxa_i2s.saimr = SAIMR;
	276	pxa_i2s.sadiv = SADIV;
	277
	278	/* deactivate link */
	279	SACR0 &= ~SACR0_ENB;
	280	pxa_i2s_wait();
	281	return 0;
	282	}
	283
dc7d7b83	284	static int pxa2xx_i2s_resume(struct snd_soc_dai *dai)
3e7cc3d3	285	{
3e7cc3d3 LG	286	pxa_i2s_wait();
3e7cc3d3 LG	287
916465a8	288	SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB;
3e7cc3d3 LG	289	SACR1 = pxa_i2s.sacr1;
	290	SAIMR = pxa_i2s.saimr;
	291	SADIV = pxa_i2s.sadiv;
916465a8 KB	292
916465a8 KB	293	SACR0 = pxa_i2s.sacr0;
3e7cc3d3 LG	294
	295	return 0;
	296	}
	297
	298	#else
	299	#define pxa2xx_i2s_suspend NULL
	300	#define pxa2xx_i2s_resume NULL
	301	#endif
	302
eaff2ae7 PZ	303	#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \|\
	304	SNDRV_PCM_RATE_16000 \| SNDRV_PCM_RATE_22050 \| SNDRV_PCM_RATE_44100 \| \
	305	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_96000)
3e7cc3d3	306
6335d055 EM	307	static struct snd_soc_dai_ops pxa_i2s_dai_ops = {
	308	.startup = pxa2xx_i2s_startup,
	309	.shutdown = pxa2xx_i2s_shutdown,
	310	.trigger = pxa2xx_i2s_trigger,
	311	.hw_params = pxa2xx_i2s_hw_params,
	312	.set_fmt = pxa2xx_i2s_set_dai_fmt,
	313	.set_sysclk = pxa2xx_i2s_set_dai_sysclk,
	314	};
	315
917f93ac	316	struct snd_soc_dai pxa_i2s_dai = {
3e7cc3d3 LG	317	.name = "pxa2xx-i2s",
3e7cc3d3 LG	318	.id = 0,
3e7cc3d3 LG	319	.suspend = pxa2xx_i2s_suspend,
3e7cc3d3 LG	320	.resume = pxa2xx_i2s_resume,
3e7cc3d3 LG	321	.playback = {
3e7cc3d3 LG	322	.channels_min = 2,
eaff2ae7 PZ	323	.channels_max = 2,
	324	.rates = PXA2XX_I2S_RATES,
	325	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
3e7cc3d3 LG	326	.capture = {
3e7cc3d3 LG	327	.channels_min = 2,
eaff2ae7 PZ	328	.channels_max = 2,
	329	.rates = PXA2XX_I2S_RATES,
	330	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
6335d055	331	.ops = &pxa_i2s_dai_ops,
7de0a0ae	332	.symmetric_rates = 1,
3e7cc3d3 LG	333	};
	334
	335	EXPORT_SYMBOL_GPL(pxa_i2s_dai);
	336
6e5ea701 DES	337	static int pxa2xx_i2s_probe(struct platform_device *dev)
6e5ea701 DES	338	{
3f4b783c MB	339	int ret;
3f4b783c MB	340
6e5ea701	341	clk_i2s = clk_get(&dev->dev, "I2SCLK");
3f4b783c MB	342	if (IS_ERR(clk_i2s))
	343	return PTR_ERR(clk_i2s);
	344
	345	pxa_i2s_dai.dev = &dev->dev;
da9ff1f7	346	pxa_i2s_dai.private_data = NULL;
3f4b783c MB	347	ret = snd_soc_register_dai(&pxa_i2s_dai);
	348	if (ret != 0)
	349	clk_put(clk_i2s);
	350
b243b77c KB	351	/*
	352	* PXA Developer's Manual:
	353	* If SACR0[ENB] is toggled in the middle of a normal operation,
	354	* the SACR0[RST] bit must also be set and cleared to reset all
	355	* I2S controller registers.
	356	*/
	357	SACR0 = SACR0_RST;
	358	SACR0 = 0;
	359	/* Make sure RPL and REC are disabled */
	360	SACR1 = SACR1_DRPL \| SACR1_DREC;
	361	/* Along with FIFO servicing */
	362	SAIMR &= ~(SAIMR_RFS \| SAIMR_TFS);
	363
3f4b783c	364	return ret;
6e5ea701 DES	365	}
	366
	367	static int __devexit pxa2xx_i2s_remove(struct platform_device *dev)
	368	{
3f4b783c	369	snd_soc_unregister_dai(&pxa_i2s_dai);
6e5ea701 DES	370	clk_put(clk_i2s);
	371	clk_i2s = ERR_PTR(-ENOENT);
	372	return 0;
	373	}
	374
	375	static struct platform_driver pxa2xx_i2s_driver = {
	376	.probe = pxa2xx_i2s_probe,
	377	.remove = __devexit_p(pxa2xx_i2s_remove),
	378
	379	.driver = {
	380	.name = "pxa2xx-i2s",
	381	.owner = THIS_MODULE,
	382	},
	383	};
	384
	385	static int __init pxa2xx_i2s_init(void)
	386	{
	387	clk_i2s = ERR_PTR(-ENOENT);
	388	return platform_driver_register(&pxa2xx_i2s_driver);
	389	}
	390
	391	static void __exit pxa2xx_i2s_exit(void)
	392	{
	393	platform_driver_unregister(&pxa2xx_i2s_driver);
	394	}
	395
	396	module_init(pxa2xx_i2s_init);
	397	module_exit(pxa2xx_i2s_exit);
	398
3e7cc3d3	399	/* Module information */
d331124d	400	MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
3e7cc3d3 LG	401	MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
3e7cc3d3 LG	402	MODULE_LICENSE("GPL");