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Merge tag 'async' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93
MB		 23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/jack.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
32#include <linux/mfd/arizona/registers.h>
33
34#include "wm_adsp.h"
35
36#define adsp_crit(_dsp, fmt, ...) \
37 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
38#define adsp_err(_dsp, fmt, ...) \
39 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
40#define adsp_warn(_dsp, fmt, ...) \
41 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42#define adsp_info(_dsp, fmt, ...) \
43 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44#define adsp_dbg(_dsp, fmt, ...) \
45 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46
47#define ADSP1_CONTROL_1 0x00
48#define ADSP1_CONTROL_2 0x02
49#define ADSP1_CONTROL_3 0x03
50#define ADSP1_CONTROL_4 0x04
51#define ADSP1_CONTROL_5 0x06
52#define ADSP1_CONTROL_6 0x07
53#define ADSP1_CONTROL_7 0x08
54#define ADSP1_CONTROL_8 0x09
55#define ADSP1_CONTROL_9 0x0A
56#define ADSP1_CONTROL_10 0x0B
57#define ADSP1_CONTROL_11 0x0C
58#define ADSP1_CONTROL_12 0x0D
59#define ADSP1_CONTROL_13 0x0F
60#define ADSP1_CONTROL_14 0x10
61#define ADSP1_CONTROL_15 0x11
62#define ADSP1_CONTROL_16 0x12
63#define ADSP1_CONTROL_17 0x13
64#define ADSP1_CONTROL_18 0x14
65#define ADSP1_CONTROL_19 0x16
66#define ADSP1_CONTROL_20 0x17
67#define ADSP1_CONTROL_21 0x18
68#define ADSP1_CONTROL_22 0x1A
69#define ADSP1_CONTROL_23 0x1B
70#define ADSP1_CONTROL_24 0x1C
71#define ADSP1_CONTROL_25 0x1E
72#define ADSP1_CONTROL_26 0x20
73#define ADSP1_CONTROL_27 0x21
74#define ADSP1_CONTROL_28 0x22
75#define ADSP1_CONTROL_29 0x23
76#define ADSP1_CONTROL_30 0x24
77#define ADSP1_CONTROL_31 0x26
78
79/*
80 * ADSP1 Control 19
81 */
82#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
83#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85
86
87/*
88 * ADSP1 Control 30
89 */
90#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
91#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
92#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
94#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
95#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
96#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
97#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
98#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
99#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
100#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
101#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
102#define ADSP1_START 0x0001 /* DSP1_START */
103#define ADSP1_START_MASK 0x0001 /* DSP1_START */
104#define ADSP1_START_SHIFT 0 /* DSP1_START */
105#define ADSP1_START_WIDTH 1 /* DSP1_START */
106
94e205bf
CR		 107/*
108 * ADSP1 Control 31
109 */
110#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
111#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
112#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
113
2d30b575
MB		 114#define ADSP2_CONTROL 0x0
115#define ADSP2_CLOCKING 0x1
116#define ADSP2_STATUS1 0x4
117#define ADSP2_WDMA_CONFIG_1 0x30
118#define ADSP2_WDMA_CONFIG_2 0x31
119#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93
MB		 120
121/*
122 * ADSP2 Control
123 */
124
125#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
126#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
127#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
128#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
129#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
130#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
131#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
132#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
133#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
134#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
135#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
136#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
137#define ADSP2_START 0x0001 /* DSP1_START */
138#define ADSP2_START_MASK 0x0001 /* DSP1_START */
139#define ADSP2_START_SHIFT 0 /* DSP1_START */
140#define ADSP2_START_WIDTH 1 /* DSP1_START */
141
973838a0
MB		 142/*
143 * ADSP2 clocking
144 */
145#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
146#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
147#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
148
2159ad93
MB		 149/*
150 * ADSP2 Status 1
151 */
152#define ADSP2_RAM_RDY 0x0001
153#define ADSP2_RAM_RDY_MASK 0x0001
154#define ADSP2_RAM_RDY_SHIFT 0
155#define ADSP2_RAM_RDY_WIDTH 1
156
cf17c83c
MB		 157struct wm_adsp_buf {
158 struct list_head list;
159 void *buf;
160};
161
162static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
163 struct list_head *list)
164{
165 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
166
167 if (buf == NULL)
168 return NULL;
169
170 buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA);
171 if (!buf->buf) {
172 kfree(buf);
173 return NULL;
174 }
175
176 if (list)
177 list_add_tail(&buf->list, list);
178
179 return buf;
180}
181
182static void wm_adsp_buf_free(struct list_head *list)
183{
184 while (!list_empty(list)) {
185 struct wm_adsp_buf *buf = list_first_entry(list,
186 struct wm_adsp_buf,
187 list);
188 list_del(&buf->list);
189 kfree(buf->buf);
190 kfree(buf);
191 }
192}
193
36e8fe99 194#define WM_ADSP_NUM_FW 4
1023dbd9
MB		 195
196static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
36e8fe99 197 "MBC/VSS", "Tx", "Tx Speaker", "Rx ANC"
1023dbd9
MB		 198};
199
200static struct {
201 const char *file;
202} wm_adsp_fw[WM_ADSP_NUM_FW] = {
203 { .file = "mbc-vss" },
204 { .file = "tx" },
36e8fe99 205 { .file = "tx-spk" },
1023dbd9
MB		 206 { .file = "rx-anc" },
207};
208
209static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
210 struct snd_ctl_elem_value *ucontrol)
211{
212 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
213 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
214 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
215
216 ucontrol->value.integer.value[0] = adsp[e->shift_l].fw;
217
218 return 0;
219}
220
221static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
222 struct snd_ctl_elem_value *ucontrol)
223{
224 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
225 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
226 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
227
228 if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw)
229 return 0;
230
231 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
232 return -EINVAL;
233
234 if (adsp[e->shift_l].running)
235 return -EBUSY;
236
31522764 237 adsp[e->shift_l].fw = ucontrol->value.integer.value[0];
1023dbd9
MB		 238
239 return 0;
240}
241
242static const struct soc_enum wm_adsp_fw_enum[] = {
243 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
244 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
245 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
246 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
247};
248
249const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
250 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
251 wm_adsp_fw_get, wm_adsp_fw_put),
252 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
253 wm_adsp_fw_get, wm_adsp_fw_put),
254 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
255 wm_adsp_fw_get, wm_adsp_fw_put),
256 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
257 wm_adsp_fw_get, wm_adsp_fw_put),
258};
259EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 260
261static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
262 int type)
263{
264 int i;
265
266 for (i = 0; i < dsp->num_mems; i++)
267 if (dsp->mem[i].type == type)
268 return &dsp->mem[i];
269
270 return NULL;
271}
272
45b9ee72
MB		 273static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
274 unsigned int offset)
275{
276 switch (region->type) {
277 case WMFW_ADSP1_PM:
278 return region->base + (offset * 3);
279 case WMFW_ADSP1_DM:
280 return region->base + (offset * 2);
281 case WMFW_ADSP2_XM:
282 return region->base + (offset * 2);
283 case WMFW_ADSP2_YM:
284 return region->base + (offset * 2);
285 case WMFW_ADSP1_ZM:
286 return region->base + (offset * 2);
287 default:
288 WARN_ON(NULL != "Unknown memory region type");
289 return offset;
290 }
291}
292
2159ad93
MB		 293static int wm_adsp_load(struct wm_adsp *dsp)
294{
cf17c83c 295 LIST_HEAD(buf_list);
2159ad93
MB		 296 const struct firmware *firmware;
297 struct regmap *regmap = dsp->regmap;
298 unsigned int pos = 0;
299 const struct wmfw_header *header;
300 const struct wmfw_adsp1_sizes *adsp1_sizes;
301 const struct wmfw_adsp2_sizes *adsp2_sizes;
302 const struct wmfw_footer *footer;
303 const struct wmfw_region *region;
304 const struct wm_adsp_region *mem;
305 const char *region_name;
306 char *file, *text;
cf17c83c 307 struct wm_adsp_buf *buf;
2159ad93
MB		 308 unsigned int reg;
309 int regions = 0;
310 int ret, offset, type, sizes;
311
312 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
313 if (file == NULL)
314 return -ENOMEM;
315
1023dbd9
MB		 316 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
317 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 318 file[PAGE_SIZE - 1] = '\0';
319
320 ret = request_firmware(&firmware, file, dsp->dev);
321 if (ret != 0) {
322 adsp_err(dsp, "Failed to request '%s'\n", file);
323 goto out;
324 }
325 ret = -EINVAL;
326
327 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
328 if (pos >= firmware->size) {
329 adsp_err(dsp, "%s: file too short, %zu bytes\n",
330 file, firmware->size);
331 goto out_fw;
332 }
333
334 header = (void*)&firmware->data[0];
335
336 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
337 adsp_err(dsp, "%s: invalid magic\n", file);
338 goto out_fw;
339 }
340
341 if (header->ver != 0) {
342 adsp_err(dsp, "%s: unknown file format %d\n",
343 file, header->ver);
344 goto out_fw;
345 }
346
347 if (header->core != dsp->type) {
348 adsp_err(dsp, "%s: invalid core %d != %d\n",
349 file, header->core, dsp->type);
350 goto out_fw;
351 }
352
353 switch (dsp->type) {
354 case WMFW_ADSP1:
355 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
356 adsp1_sizes = (void *)&(header[1]);
357 footer = (void *)&(adsp1_sizes[1]);
358 sizes = sizeof(*adsp1_sizes);
359
360 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
361 file, le32_to_cpu(adsp1_sizes->dm),
362 le32_to_cpu(adsp1_sizes->pm),
363 le32_to_cpu(adsp1_sizes->zm));
364 break;
365
366 case WMFW_ADSP2:
367 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
368 adsp2_sizes = (void *)&(header[1]);
369 footer = (void *)&(adsp2_sizes[1]);
370 sizes = sizeof(*adsp2_sizes);
371
372 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
373 file, le32_to_cpu(adsp2_sizes->xm),
374 le32_to_cpu(adsp2_sizes->ym),
375 le32_to_cpu(adsp2_sizes->pm),
376 le32_to_cpu(adsp2_sizes->zm));
377 break;
378
379 default:
380 BUG_ON(NULL == "Unknown DSP type");
381 goto out_fw;
382 }
383
384 if (le32_to_cpu(header->len) != sizeof(*header) +
385 sizes + sizeof(*footer)) {
386 adsp_err(dsp, "%s: unexpected header length %d\n",
387 file, le32_to_cpu(header->len));
388 goto out_fw;
389 }
390
391 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
392 le64_to_cpu(footer->timestamp));
393
394 while (pos < firmware->size &&
395 pos - firmware->size > sizeof(*region)) {
396 region = (void *)&(firmware->data[pos]);
397 region_name = "Unknown";
398 reg = 0;
399 text = NULL;
400 offset = le32_to_cpu(region->offset) & 0xffffff;
401 type = be32_to_cpu(region->type) & 0xff;
402 mem = wm_adsp_find_region(dsp, type);
403
404 switch (type) {
405 case WMFW_NAME_TEXT:
406 region_name = "Firmware name";
407 text = kzalloc(le32_to_cpu(region->len) + 1,
408 GFP_KERNEL);
409 break;
410 case WMFW_INFO_TEXT:
411 region_name = "Information";
412 text = kzalloc(le32_to_cpu(region->len) + 1,
413 GFP_KERNEL);
414 break;
415 case WMFW_ABSOLUTE:
416 region_name = "Absolute";
417 reg = offset;
418 break;
419 case WMFW_ADSP1_PM:
420 BUG_ON(!mem);
421 region_name = "PM";
45b9ee72 422 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 423 break;
424 case WMFW_ADSP1_DM:
425 BUG_ON(!mem);
426 region_name = "DM";
45b9ee72 427 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 428 break;
429 case WMFW_ADSP2_XM:
430 BUG_ON(!mem);
431 region_name = "XM";
45b9ee72 432 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 433 break;
434 case WMFW_ADSP2_YM:
435 BUG_ON(!mem);
436 region_name = "YM";
45b9ee72 437 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 438 break;
439 case WMFW_ADSP1_ZM:
440 BUG_ON(!mem);
441 region_name = "ZM";
45b9ee72 442 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 443 break;
444 default:
445 adsp_warn(dsp,
446 "%s.%d: Unknown region type %x at %d(%x)\n",
447 file, regions, type, pos, pos);
448 break;
449 }
450
451 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
452 regions, le32_to_cpu(region->len), offset,
453 region_name);
454
455 if (text) {
456 memcpy(text, region->data, le32_to_cpu(region->len));
457 adsp_info(dsp, "%s: %s\n", file, text);
458 kfree(text);
459 }
460
461 if (reg) {
cf17c83c
MB		 462 buf = wm_adsp_buf_alloc(region->data,
463 le32_to_cpu(region->len),
464 &buf_list);
a76fefab
MB		 465 if (!buf) {
466 adsp_err(dsp, "Out of memory\n");
467 return -ENOMEM;
468 }
469
cf17c83c
MB		 470 ret = regmap_raw_write_async(regmap, reg, buf->buf,
471 le32_to_cpu(region->len));
2159ad93
MB		 472 if (ret != 0) {
473 adsp_err(dsp,
474 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
475 file, regions,
476 le32_to_cpu(region->len), offset,
477 region_name, ret);
478 goto out_fw;
479 }
480 }
481
482 pos += le32_to_cpu(region->len) + sizeof(*region);
483 regions++;
484 }
cf17c83c
MB		 485
486 ret = regmap_async_complete(regmap);
487 if (ret != 0) {
488 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
489 goto out_fw;
490 }
491
2159ad93
MB		 492 if (pos > firmware->size)
493 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
494 file, regions, pos - firmware->size);
495
496out_fw:
cf17c83c
MB		 497 regmap_async_complete(regmap);
498 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 499 release_firmware(firmware);
500out:
501 kfree(file);
502
503 return ret;
504}
505
db40517c
MB		 506static int wm_adsp_setup_algs(struct wm_adsp *dsp)
507{
508 struct regmap *regmap = dsp->regmap;
509 struct wmfw_adsp1_id_hdr adsp1_id;
510 struct wmfw_adsp2_id_hdr adsp2_id;
511 struct wmfw_adsp1_alg_hdr *adsp1_alg;
512 struct wmfw_adsp2_alg_hdr *adsp2_alg;
d62f4bc6 513 void *alg, *buf;
471f4885 514 struct wm_adsp_alg_region *region;
db40517c
MB		 515 const struct wm_adsp_region *mem;
516 unsigned int pos, term;
d62f4bc6 517 size_t algs, buf_size;
db40517c
MB		 518 __be32 val;
519 int i, ret;
520
521 switch (dsp->type) {
522 case WMFW_ADSP1:
523 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
524 break;
525 case WMFW_ADSP2:
526 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
527 break;
528 default:
529 mem = NULL;
530 break;
531 }
532
533 if (mem == NULL) {
534 BUG_ON(mem != NULL);
535 return -EINVAL;
536 }
537
538 switch (dsp->type) {
539 case WMFW_ADSP1:
540 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
541 sizeof(adsp1_id));
542 if (ret != 0) {
543 adsp_err(dsp, "Failed to read algorithm info: %d\n",
544 ret);
545 return ret;
546 }
547
d62f4bc6
MB		 548 buf = &adsp1_id;
549 buf_size = sizeof(adsp1_id);
550
db40517c
MB		 551 algs = be32_to_cpu(adsp1_id.algs);
552 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
553 be32_to_cpu(adsp1_id.fw.id),
554 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
555 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
556 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
557 algs);
558
559 pos = sizeof(adsp1_id) / 2;
560 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
561 break;
562
563 case WMFW_ADSP2:
564 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
565 sizeof(adsp2_id));
566 if (ret != 0) {
567 adsp_err(dsp, "Failed to read algorithm info: %d\n",
568 ret);
569 return ret;
570 }
571
d62f4bc6
MB		 572 buf = &adsp2_id;
573 buf_size = sizeof(adsp2_id);
574
db40517c
MB		 575 algs = be32_to_cpu(adsp2_id.algs);
576 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
577 be32_to_cpu(adsp2_id.fw.id),
578 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
579 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
580 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
581 algs);
582
583 pos = sizeof(adsp2_id) / 2;
584 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
585 break;
586
587 default:
588 BUG_ON(NULL == "Unknown DSP type");
589 return -EINVAL;
590 }
591
592 if (algs == 0) {
593 adsp_err(dsp, "No algorithms\n");
594 return -EINVAL;
595 }
596
d62f4bc6
MB		 597 if (algs > 1024) {
598 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
599 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
600 buf, buf_size);
601 return -EINVAL;
602 }
603
db40517c
MB		 604 /* Read the terminator first to validate the length */
605 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
606 if (ret != 0) {
607 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
608 ret);
609 return ret;
610 }
611
612 if (be32_to_cpu(val) != 0xbedead)
613 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
614 term, be32_to_cpu(val));
615
f2a93e2a 616 alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA);
db40517c
MB		 617 if (!alg)
618 return -ENOMEM;
619
620 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
621 if (ret != 0) {
622 adsp_err(dsp, "Failed to read algorithm list: %d\n",
623 ret);
624 goto out;
625 }
626
627 adsp1_alg = alg;
628 adsp2_alg = alg;
629
630 for (i = 0; i < algs; i++) {
631 switch (dsp->type) {
632 case WMFW_ADSP1:
471f4885 633 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
db40517c
MB		 634 i, be32_to_cpu(adsp1_alg[i].alg.id),
635 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
636 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 637 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
638 be32_to_cpu(adsp1_alg[i].dm),
639 be32_to_cpu(adsp1_alg[i].zm));
640
7480800e
MB		 641 region = kzalloc(sizeof(*region), GFP_KERNEL);
642 if (!region)
643 return -ENOMEM;
644 region->type = WMFW_ADSP1_DM;
645 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
646 region->base = be32_to_cpu(adsp1_alg[i].dm);
647 list_add_tail(&region->list, &dsp->alg_regions);
471f4885 648
7480800e
MB		 649 region = kzalloc(sizeof(*region), GFP_KERNEL);
650 if (!region)
651 return -ENOMEM;
652 region->type = WMFW_ADSP1_ZM;
653 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
654 region->base = be32_to_cpu(adsp1_alg[i].zm);
655 list_add_tail(&region->list, &dsp->alg_regions);
db40517c
MB		 656 break;
657
658 case WMFW_ADSP2:
471f4885
MB		 659 adsp_info(dsp,
660 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
db40517c
MB		 661 i, be32_to_cpu(adsp2_alg[i].alg.id),
662 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
663 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 664 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
665 be32_to_cpu(adsp2_alg[i].xm),
666 be32_to_cpu(adsp2_alg[i].ym),
667 be32_to_cpu(adsp2_alg[i].zm));
668
7480800e
MB		 669 region = kzalloc(sizeof(*region), GFP_KERNEL);
670 if (!region)
671 return -ENOMEM;
672 region->type = WMFW_ADSP2_XM;
673 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
674 region->base = be32_to_cpu(adsp2_alg[i].xm);
675 list_add_tail(&region->list, &dsp->alg_regions);
471f4885 676
7480800e
MB		 677 region = kzalloc(sizeof(*region), GFP_KERNEL);
678 if (!region)
679 return -ENOMEM;
680 region->type = WMFW_ADSP2_YM;
681 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
682 region->base = be32_to_cpu(adsp2_alg[i].ym);
683 list_add_tail(&region->list, &dsp->alg_regions);
471f4885 684
7480800e
MB		 685 region = kzalloc(sizeof(*region), GFP_KERNEL);
686 if (!region)
687 return -ENOMEM;
688 region->type = WMFW_ADSP2_ZM;
689 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
690 region->base = be32_to_cpu(adsp2_alg[i].zm);
691 list_add_tail(&region->list, &dsp->alg_regions);
db40517c
MB		 692 break;
693 }
694 }
695
696out:
697 kfree(alg);
698 return ret;
699}
700
2159ad93
MB		 701static int wm_adsp_load_coeff(struct wm_adsp *dsp)
702{
cf17c83c 703 LIST_HEAD(buf_list);
2159ad93
MB		 704 struct regmap *regmap = dsp->regmap;
705 struct wmfw_coeff_hdr *hdr;
706 struct wmfw_coeff_item *blk;
707 const struct firmware *firmware;
471f4885
MB		 708 const struct wm_adsp_region *mem;
709 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 710 const char *region_name;
711 int ret, pos, blocks, type, offset, reg;
712 char *file;
cf17c83c 713 struct wm_adsp_buf *buf;
2159ad93
MB		 714
715 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
716 if (file == NULL)
717 return -ENOMEM;
718
1023dbd9
MB		 719 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
720 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 721 file[PAGE_SIZE - 1] = '\0';
722
723 ret = request_firmware(&firmware, file, dsp->dev);
724 if (ret != 0) {
725 adsp_warn(dsp, "Failed to request '%s'\n", file);
726 ret = 0;
727 goto out;
728 }
729 ret = -EINVAL;
730
731 if (sizeof(*hdr) >= firmware->size) {
732 adsp_err(dsp, "%s: file too short, %zu bytes\n",
733 file, firmware->size);
734 goto out_fw;
735 }
736
737 hdr = (void*)&firmware->data[0];
738 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
739 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 740 goto out_fw;
2159ad93
MB		 741 }
742
c712326d
MB		 743 switch (be32_to_cpu(hdr->rev) & 0xff) {
744 case 1:
745 break;
746 default:
747 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
748 file, be32_to_cpu(hdr->rev) & 0xff);
749 ret = -EINVAL;
750 goto out_fw;
751 }
752
2159ad93
MB		 753 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
754 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
755 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
756 le32_to_cpu(hdr->ver) & 0xff);
757
758 pos = le32_to_cpu(hdr->len);
759
760 blocks = 0;
761 while (pos < firmware->size &&
762 pos - firmware->size > sizeof(*blk)) {
763 blk = (void*)(&firmware->data[pos]);
764
c712326d
MB		 765 type = le16_to_cpu(blk->type);
766 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 767
768 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
769 file, blocks, le32_to_cpu(blk->id),
770 (le32_to_cpu(blk->ver) >> 16) & 0xff,
771 (le32_to_cpu(blk->ver) >> 8) & 0xff,
772 le32_to_cpu(blk->ver) & 0xff);
773 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
774 file, blocks, le32_to_cpu(blk->len), offset, type);
775
776 reg = 0;
777 region_name = "Unknown";
778 switch (type) {
c712326d
MB		 779 case (WMFW_NAME_TEXT << 8):
780 case (WMFW_INFO_TEXT << 8):
2159ad93 781 break;
c712326d 782 case (WMFW_ABSOLUTE << 8):
2159ad93
MB		 783 region_name = "register";
784 reg = offset;
785 break;
471f4885
MB		 786
787 case WMFW_ADSP1_DM:
788 case WMFW_ADSP1_ZM:
789 case WMFW_ADSP2_XM:
790 case WMFW_ADSP2_YM:
791 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
792 file, blocks, le32_to_cpu(blk->len),
793 type, le32_to_cpu(blk->id));
794
795 mem = wm_adsp_find_region(dsp, type);
796 if (!mem) {
797 adsp_err(dsp, "No base for region %x\n", type);
798 break;
799 }
800
801 reg = 0;
802 list_for_each_entry(alg_region,
803 &dsp->alg_regions, list) {
804 if (le32_to_cpu(blk->id) == alg_region->alg &&
805 type == alg_region->type) {
338c5188 806 reg = alg_region->base;
471f4885
MB		 807 reg = wm_adsp_region_to_reg(mem,
808 reg);
338c5188 809 reg += offset;
471f4885
MB		 810 }
811 }
812
813 if (reg == 0)
814 adsp_err(dsp, "No %x for algorithm %x\n",
815 type, le32_to_cpu(blk->id));
816 break;
817
2159ad93 818 default:
25c62f7e
MB		 819 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
820 file, blocks, type, pos);
2159ad93
MB		 821 break;
822 }
823
824 if (reg) {
cf17c83c
MB		 825 buf = wm_adsp_buf_alloc(blk->data,
826 le32_to_cpu(blk->len),
827 &buf_list);
a76fefab
MB		 828 if (!buf) {
829 adsp_err(dsp, "Out of memory\n");
830 return -ENOMEM;
831 }
832
20da6d5a
MB		 833 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
834 file, blocks, le32_to_cpu(blk->len),
835 reg);
cf17c83c
MB		 836 ret = regmap_raw_write_async(regmap, reg, buf->buf,
837 le32_to_cpu(blk->len));
2159ad93
MB		 838 if (ret != 0) {
839 adsp_err(dsp,
840 "%s.%d: Failed to write to %x in %s\n",
841 file, blocks, reg, region_name);
842 }
843 }
844
845 pos += le32_to_cpu(blk->len) + sizeof(*blk);
846 blocks++;
847 }
848
cf17c83c
MB		 849 ret = regmap_async_complete(regmap);
850 if (ret != 0)
851 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
852
2159ad93
MB		 853 if (pos > firmware->size)
854 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
855 file, blocks, pos - firmware->size);
856
857out_fw:
858 release_firmware(firmware);
cf17c83c 859 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 860out:
861 kfree(file);
862 return 0;
863}
864
5e7a7a22
MB		 865int wm_adsp1_init(struct wm_adsp *adsp)
866{
867 INIT_LIST_HEAD(&adsp->alg_regions);
868
869 return 0;
870}
871EXPORT_SYMBOL_GPL(wm_adsp1_init);
872
2159ad93
MB		 873int wm_adsp1_event(struct snd_soc_dapm_widget *w,
874 struct snd_kcontrol *kcontrol,
875 int event)
876{
877 struct snd_soc_codec *codec = w->codec;
878 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
879 struct wm_adsp *dsp = &dsps[w->shift];
880 int ret;
94e205bf 881 int val;
2159ad93
MB		 882
883 switch (event) {
884 case SND_SOC_DAPM_POST_PMU:
885 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
886 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
887
94e205bf
CR		 888 /*
889 * For simplicity set the DSP clock rate to be the
890 * SYSCLK rate rather than making it configurable.
891 */
892 if(dsp->sysclk_reg) {
893 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
894 if (ret != 0) {
895 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
896 ret);
897 return ret;
898 }
899
900 val = (val & dsp->sysclk_mask)
901 >> dsp->sysclk_shift;
902
903 ret = regmap_update_bits(dsp->regmap,
904 dsp->base + ADSP1_CONTROL_31,
905 ADSP1_CLK_SEL_MASK, val);
906 if (ret != 0) {
907 adsp_err(dsp, "Failed to set clock rate: %d\n",
908 ret);
909 return ret;
910 }
911 }
912
2159ad93
MB		 913 ret = wm_adsp_load(dsp);
914 if (ret != 0)
915 goto err;
916
db40517c
MB		 917 ret = wm_adsp_setup_algs(dsp);
918 if (ret != 0)
919 goto err;
920
2159ad93
MB		 921 ret = wm_adsp_load_coeff(dsp);
922 if (ret != 0)
923 goto err;
924
925 /* Start the core running */
926 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
927 ADSP1_CORE_ENA | ADSP1_START,
928 ADSP1_CORE_ENA | ADSP1_START);
929 break;
930
931 case SND_SOC_DAPM_PRE_PMD:
932 /* Halt the core */
933 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
934 ADSP1_CORE_ENA | ADSP1_START, 0);
935
936 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
937 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
938
939 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
940 ADSP1_SYS_ENA, 0);
941 break;
942
943 default:
944 break;
945 }
946
947 return 0;
948
949err:
950 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
951 ADSP1_SYS_ENA, 0);
952 return ret;
953}
954EXPORT_SYMBOL_GPL(wm_adsp1_event);
955
956static int wm_adsp2_ena(struct wm_adsp *dsp)
957{
958 unsigned int val;
959 int ret, count;
960
961 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
962 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
963 if (ret != 0)
964 return ret;
965
966 /* Wait for the RAM to start, should be near instantaneous */
967 count = 0;
968 do {
969 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
970 &val);
971 if (ret != 0)
972 return ret;
973 } while (!(val & ADSP2_RAM_RDY) && ++count < 10);
974
975 if (!(val & ADSP2_RAM_RDY)) {
976 adsp_err(dsp, "Failed to start DSP RAM\n");
977 return -EBUSY;
978 }
979
980 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
981 adsp_info(dsp, "RAM ready after %d polls\n", count);
982
983 return 0;
984}
985
986int wm_adsp2_event(struct snd_soc_dapm_widget *w,
987 struct snd_kcontrol *kcontrol, int event)
988{
989 struct snd_soc_codec *codec = w->codec;
990 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
991 struct wm_adsp *dsp = &dsps[w->shift];
471f4885 992 struct wm_adsp_alg_region *alg_region;
973838a0 993 unsigned int val;
2159ad93
MB		 994 int ret;
995
996 switch (event) {
997 case SND_SOC_DAPM_POST_PMU:
dd49e2c8
MB		 998 /*
999 * For simplicity set the DSP clock rate to be the
1000 * SYSCLK rate rather than making it configurable.
1001 */
1002 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1003 if (ret != 0) {
1004 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1005 ret);
1006 return ret;
1007 }
1008 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1009 >> ARIZONA_SYSCLK_FREQ_SHIFT;
1010
1011 ret = regmap_update_bits(dsp->regmap,
1012 dsp->base + ADSP2_CLOCKING,
1013 ADSP2_CLK_SEL_MASK, val);
1014 if (ret != 0) {
1015 adsp_err(dsp, "Failed to set clock rate: %d\n",
1016 ret);
1017 return ret;
1018 }
1019
973838a0
MB		 1020 if (dsp->dvfs) {
1021 ret = regmap_read(dsp->regmap,
1022 dsp->base + ADSP2_CLOCKING, &val);
1023 if (ret != 0) {
1024 dev_err(dsp->dev,
1025 "Failed to read clocking: %d\n", ret);
1026 return ret;
1027 }
1028
25c6fdb0 1029 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
973838a0
MB		 1030 ret = regulator_enable(dsp->dvfs);
1031 if (ret != 0) {
1032 dev_err(dsp->dev,
1033 "Failed to enable supply: %d\n",
1034 ret);
1035 return ret;
1036 }
1037
1038 ret = regulator_set_voltage(dsp->dvfs,
1039 1800000,
1040 1800000);
1041 if (ret != 0) {
1042 dev_err(dsp->dev,
1043 "Failed to raise supply: %d\n",
1044 ret);
1045 return ret;
1046 }
1047 }
1048 }
1049
2159ad93
MB		 1050 ret = wm_adsp2_ena(dsp);
1051 if (ret != 0)
1052 return ret;
1053
1054 ret = wm_adsp_load(dsp);
1055 if (ret != 0)
1056 goto err;
1057
db40517c
MB		 1058 ret = wm_adsp_setup_algs(dsp);
1059 if (ret != 0)
1060 goto err;
1061
2159ad93
MB		 1062 ret = wm_adsp_load_coeff(dsp);
1063 if (ret != 0)
1064 goto err;
1065
1066 ret = regmap_update_bits(dsp->regmap,
1067 dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 1068 ADSP2_CORE_ENA | ADSP2_START,
1069 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 1070 if (ret != 0)
1071 goto err;
1023dbd9
MB		 1072
1073 dsp->running = true;
2159ad93
MB		 1074 break;
1075
1076 case SND_SOC_DAPM_PRE_PMD:
1023dbd9
MB		 1077 dsp->running = false;
1078
2159ad93 1079 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 1080 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1081 ADSP2_START, 0);
973838a0 1082
2d30b575
MB		 1083 /* Make sure DMAs are quiesced */
1084 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1085 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1086 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1087
973838a0
MB		 1088 if (dsp->dvfs) {
1089 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1090 1800000);
1091 if (ret != 0)
1092 dev_warn(dsp->dev,
1093 "Failed to lower supply: %d\n",
1094 ret);
1095
1096 ret = regulator_disable(dsp->dvfs);
1097 if (ret != 0)
1098 dev_err(dsp->dev,
1099 "Failed to enable supply: %d\n",
1100 ret);
1101 }
471f4885
MB		 1102
1103 while (!list_empty(&dsp->alg_regions)) {
1104 alg_region = list_first_entry(&dsp->alg_regions,
1105 struct wm_adsp_alg_region,
1106 list);
1107 list_del(&alg_region->list);
1108 kfree(alg_region);
1109 }
2159ad93
MB		 1110 break;
1111
1112 default:
1113 break;
1114 }
1115
1116 return 0;
1117err:
1118 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 1119 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 1120 return ret;
1121}
1122EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0
MB		 1123
1124int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
1125{
1126 int ret;
1127
10a2b662
MB		 1128 /*
1129 * Disable the DSP memory by default when in reset for a small
1130 * power saving.
1131 */
1132 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
1133 ADSP2_MEM_ENA, 0);
1134 if (ret != 0) {
1135 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
1136 return ret;
1137 }
1138
471f4885
MB		 1139 INIT_LIST_HEAD(&adsp->alg_regions);
1140
973838a0
MB		 1141 if (dvfs) {
1142 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
1143 if (IS_ERR(adsp->dvfs)) {
1144 ret = PTR_ERR(adsp->dvfs);
1145 dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret);
1146 return ret;
1147 }
1148
1149 ret = regulator_enable(adsp->dvfs);
1150 if (ret != 0) {
1151 dev_err(adsp->dev, "Failed to enable DCVDD: %d\n",
1152 ret);
1153 return ret;
1154 }
1155
1156 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
1157 if (ret != 0) {
1158 dev_err(adsp->dev, "Failed to initialise DVFS: %d\n",
1159 ret);
1160 return ret;
1161 }
1162
1163 ret = regulator_disable(adsp->dvfs);
1164 if (ret != 0) {
1165 dev_err(adsp->dev, "Failed to disable DCVDD: %d\n",
1166 ret);
1167 return ret;
1168 }
1169 }
1170
1171 return 0;
1172}
1173EXPORT_SYMBOL_GPL(wm_adsp2_init);
kernel source for telekom puls (alcatel/mediatek)