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Merge tag 'mmc-fixes-for-3.10-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8995.c
CommitLineData
6a504a75
DP		 1/*
2 * wm8995.c -- WM8995 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * Based on wm8994.c and wm_hubs.c by Mark Brown
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
c42da642 21#include <linux/regmap.h>
6a504a75 22#include <linux/spi/spi.h>
219d8df8 23#include <linux/regulator/consumer.h>
6a504a75
DP		 24#include <linux/slab.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
33#include "wm8995.h"
34
219d8df8
DP		 35#define WM8995_NUM_SUPPLIES 8
36static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = {
37 "DCVDD",
38 "DBVDD1",
39 "DBVDD2",
40 "DBVDD3",
41 "AVDD1",
42 "AVDD2",
43 "CPVDD",
44 "MICVDD"
45};
46
c42da642
MB		 47static struct reg_default wm8995_reg_defaults[] = {
48 { 0, 0x8995 },
49 { 5, 0x0100 },
50 { 16, 0x000b },
51 { 17, 0x000b },
52 { 24, 0x02c0 },
53 { 25, 0x02c0 },
54 { 26, 0x02c0 },
55 { 27, 0x02c0 },
56 { 28, 0x000f },
57 { 32, 0x0005 },
58 { 33, 0x0005 },
59 { 40, 0x0003 },
60 { 41, 0x0013 },
61 { 48, 0x0004 },
62 { 56, 0x09f8 },
63 { 64, 0x1f25 },
64 { 69, 0x0004 },
65 { 82, 0xaaaa },
66 { 84, 0x2a2a },
67 { 146, 0x0060 },
68 { 256, 0x0002 },
69 { 257, 0x8004 },
70 { 520, 0x0010 },
71 { 528, 0x0083 },
72 { 529, 0x0083 },
73 { 548, 0x0c80 },
74 { 580, 0x0c80 },
75 { 768, 0x4050 },
76 { 769, 0x4000 },
77 { 771, 0x0040 },
78 { 772, 0x0040 },
79 { 773, 0x0040 },
80 { 774, 0x0004 },
81 { 775, 0x0100 },
82 { 784, 0x4050 },
83 { 785, 0x4000 },
84 { 787, 0x0040 },
85 { 788, 0x0040 },
86 { 789, 0x0040 },
87 { 1024, 0x00c0 },
88 { 1025, 0x00c0 },
89 { 1026, 0x00c0 },
90 { 1027, 0x00c0 },
91 { 1028, 0x00c0 },
92 { 1029, 0x00c0 },
93 { 1030, 0x00c0 },
94 { 1031, 0x00c0 },
95 { 1056, 0x0200 },
96 { 1057, 0x0010 },
97 { 1058, 0x0200 },
98 { 1059, 0x0010 },
99 { 1088, 0x0098 },
100 { 1089, 0x0845 },
101 { 1104, 0x0098 },
102 { 1105, 0x0845 },
103 { 1152, 0x6318 },
104 { 1153, 0x6300 },
105 { 1154, 0x0fca },
106 { 1155, 0x0400 },
107 { 1156, 0x00d8 },
108 { 1157, 0x1eb5 },
109 { 1158, 0xf145 },
110 { 1159, 0x0b75 },
111 { 1160, 0x01c5 },
112 { 1161, 0x1c58 },
113 { 1162, 0xf373 },
114 { 1163, 0x0a54 },
115 { 1164, 0x0558 },
116 { 1165, 0x168e },
117 { 1166, 0xf829 },
118 { 1167, 0x07ad },
119 { 1168, 0x1103 },
120 { 1169, 0x0564 },
121 { 1170, 0x0559 },
122 { 1171, 0x4000 },
123 { 1184, 0x6318 },
124 { 1185, 0x6300 },
125 { 1186, 0x0fca },
126 { 1187, 0x0400 },
127 { 1188, 0x00d8 },
128 { 1189, 0x1eb5 },
129 { 1190, 0xf145 },
130 { 1191, 0x0b75 },
131 { 1192, 0x01c5 },
132 { 1193, 0x1c58 },
133 { 1194, 0xf373 },
134 { 1195, 0x0a54 },
135 { 1196, 0x0558 },
136 { 1197, 0x168e },
137 { 1198, 0xf829 },
138 { 1199, 0x07ad },
139 { 1200, 0x1103 },
140 { 1201, 0x0564 },
141 { 1202, 0x0559 },
142 { 1203, 0x4000 },
143 { 1280, 0x00c0 },
144 { 1281, 0x00c0 },
145 { 1282, 0x00c0 },
146 { 1283, 0x00c0 },
147 { 1312, 0x0200 },
148 { 1313, 0x0010 },
149 { 1344, 0x0098 },
150 { 1345, 0x0845 },
151 { 1408, 0x6318 },
152 { 1409, 0x6300 },
153 { 1410, 0x0fca },
154 { 1411, 0x0400 },
155 { 1412, 0x00d8 },
156 { 1413, 0x1eb5 },
157 { 1414, 0xf145 },
158 { 1415, 0x0b75 },
159 { 1416, 0x01c5 },
160 { 1417, 0x1c58 },
161 { 1418, 0xf373 },
162 { 1419, 0x0a54 },
163 { 1420, 0x0558 },
164 { 1421, 0x168e },
165 { 1422, 0xf829 },
166 { 1423, 0x07ad },
167 { 1424, 0x1103 },
168 { 1425, 0x0564 },
169 { 1426, 0x0559 },
170 { 1427, 0x4000 },
171 { 1568, 0x0002 },
172 { 1792, 0xa100 },
173 { 1793, 0xa101 },
174 { 1794, 0xa101 },
175 { 1795, 0xa101 },
176 { 1796, 0xa101 },
177 { 1797, 0xa101 },
178 { 1798, 0xa101 },
179 { 1799, 0xa101 },
180 { 1800, 0xa101 },
181 { 1801, 0xa101 },
182 { 1802, 0xa101 },
183 { 1803, 0xa101 },
184 { 1804, 0xa101 },
185 { 1805, 0xa101 },
186 { 1825, 0x0055 },
187 { 1848, 0x3fff },
188 { 1849, 0x1fff },
189 { 2049, 0x0001 },
190 { 2050, 0x0069 },
191 { 2056, 0x0002 },
192 { 2057, 0x0003 },
193 { 2058, 0x0069 },
194 { 12288, 0x0001 },
195 { 12289, 0x0001 },
196 { 12291, 0x0006 },
197 { 12292, 0x0040 },
198 { 12293, 0x0001 },
199 { 12294, 0x000f },
200 { 12295, 0x0006 },
201 { 12296, 0x0001 },
202 { 12297, 0x0003 },
203 { 12298, 0x0104 },
204 { 12300, 0x0060 },
205 { 12301, 0x0011 },
206 { 12302, 0x0401 },
207 { 12304, 0x0050 },
208 { 12305, 0x0003 },
209 { 12306, 0x0100 },
210 { 12308, 0x0051 },
211 { 12309, 0x0003 },
212 { 12310, 0x0104 },
213 { 12311, 0x000a },
214 { 12312, 0x0060 },
215 { 12313, 0x003b },
216 { 12314, 0x0502 },
217 { 12315, 0x0100 },
218 { 12316, 0x2fff },
219 { 12320, 0x2fff },
220 { 12324, 0x2fff },
221 { 12328, 0x2fff },
222 { 12332, 0x2fff },
223 { 12336, 0x2fff },
224 { 12340, 0x2fff },
225 { 12344, 0x2fff },
226 { 12348, 0x2fff },
227 { 12352, 0x0001 },
228 { 12353, 0x0001 },
229 { 12355, 0x0006 },
230 { 12356, 0x0040 },
231 { 12357, 0x0001 },
232 { 12358, 0x000f },
233 { 12359, 0x0006 },
234 { 12360, 0x0001 },
235 { 12361, 0x0003 },
236 { 12362, 0x0104 },
237 { 12364, 0x0060 },
238 { 12365, 0x0011 },
239 { 12366, 0x0401 },
240 { 12368, 0x0050 },
241 { 12369, 0x0003 },
242 { 12370, 0x0100 },
243 { 12372, 0x0060 },
244 { 12373, 0x003b },
245 { 12374, 0x0502 },
246 { 12375, 0x0100 },
247 { 12376, 0x2fff },
248 { 12380, 0x2fff },
249 { 12384, 0x2fff },
250 { 12388, 0x2fff },
251 { 12392, 0x2fff },
252 { 12396, 0x2fff },
253 { 12400, 0x2fff },
254 { 12404, 0x2fff },
255 { 12408, 0x2fff },
256 { 12412, 0x2fff },
257 { 12416, 0x0001 },
258 { 12417, 0x0001 },
259 { 12419, 0x0006 },
260 { 12420, 0x0040 },
261 { 12421, 0x0001 },
262 { 12422, 0x000f },
263 { 12423, 0x0006 },
264 { 12424, 0x0001 },
265 { 12425, 0x0003 },
266 { 12426, 0x0106 },
267 { 12428, 0x0061 },
268 { 12429, 0x0011 },
269 { 12430, 0x0401 },
270 { 12432, 0x0050 },
271 { 12433, 0x0003 },
272 { 12434, 0x0102 },
273 { 12436, 0x0051 },
274 { 12437, 0x0003 },
275 { 12438, 0x0106 },
276 { 12439, 0x000a },
277 { 12440, 0x0061 },
278 { 12441, 0x003b },
279 { 12442, 0x0502 },
280 { 12443, 0x0100 },
281 { 12444, 0x2fff },
282 { 12448, 0x2fff },
283 { 12452, 0x2fff },
284 { 12456, 0x2fff },
285 { 12460, 0x2fff },
286 { 12464, 0x2fff },
287 { 12468, 0x2fff },
288 { 12472, 0x2fff },
289 { 12476, 0x2fff },
290 { 12480, 0x0001 },
291 { 12481, 0x0001 },
292 { 12483, 0x0006 },
293 { 12484, 0x0040 },
294 { 12485, 0x0001 },
295 { 12486, 0x000f },
296 { 12487, 0x0006 },
297 { 12488, 0x0001 },
298 { 12489, 0x0003 },
299 { 12490, 0x0106 },
300 { 12492, 0x0061 },
301 { 12493, 0x0011 },
302 { 12494, 0x0401 },
303 { 12496, 0x0050 },
304 { 12497, 0x0003 },
305 { 12498, 0x0102 },
306 { 12500, 0x0061 },
307 { 12501, 0x003b },
308 { 12502, 0x0502 },
309 { 12503, 0x0100 },
310 { 12504, 0x2fff },
311 { 12508, 0x2fff },
312 { 12512, 0x2fff },
313 { 12516, 0x2fff },
314 { 12520, 0x2fff },
315 { 12524, 0x2fff },
316 { 12528, 0x2fff },
317 { 12532, 0x2fff },
318 { 12536, 0x2fff },
319 { 12540, 0x2fff },
320 { 12544, 0x0060 },
321 { 12546, 0x0601 },
322 { 12548, 0x0050 },
323 { 12550, 0x0100 },
324 { 12552, 0x0001 },
325 { 12554, 0x0104 },
326 { 12555, 0x0100 },
327 { 12556, 0x2fff },
328 { 12560, 0x2fff },
329 { 12564, 0x2fff },
330 { 12568, 0x2fff },
331 { 12572, 0x2fff },
332 { 12576, 0x2fff },
333 { 12580, 0x2fff },
334 { 12584, 0x2fff },
335 { 12588, 0x2fff },
336 { 12592, 0x2fff },
337 { 12596, 0x2fff },
338 { 12600, 0x2fff },
339 { 12604, 0x2fff },
340 { 12608, 0x0061 },
341 { 12610, 0x0601 },
342 { 12612, 0x0050 },
343 { 12614, 0x0102 },
344 { 12616, 0x0001 },
345 { 12618, 0x0106 },
346 { 12619, 0x0100 },
347 { 12620, 0x2fff },
348 { 12624, 0x2fff },
349 { 12628, 0x2fff },
350 { 12632, 0x2fff },
351 { 12636, 0x2fff },
352 { 12640, 0x2fff },
353 { 12644, 0x2fff },
354 { 12648, 0x2fff },
355 { 12652, 0x2fff },
356 { 12656, 0x2fff },
357 { 12660, 0x2fff },
358 { 12664, 0x2fff },
359 { 12668, 0x2fff },
360 { 12672, 0x0060 },
361 { 12674, 0x0601 },
362 { 12676, 0x0061 },
363 { 12678, 0x0601 },
364 { 12680, 0x0050 },
365 { 12682, 0x0300 },
366 { 12684, 0x0001 },
367 { 12686, 0x0304 },
368 { 12688, 0x0040 },
369 { 12690, 0x000f },
370 { 12692, 0x0001 },
371 { 12695, 0x0100 },
6a504a75
DP		 372};
373
374struct fll_config {
375 int src;
376 int in;
377 int out;
378};
379
380struct wm8995_priv {
c42da642 381 struct regmap *regmap;
6a504a75
DP		 382 int sysclk[2];
383 int mclk[2];
384 int aifclk[2];
385 struct fll_config fll[2], fll_suspend[2];
219d8df8
DP		 386 struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES];
387 struct notifier_block disable_nb[WM8995_NUM_SUPPLIES];
388 struct snd_soc_codec *codec;
6a504a75
DP		 389};
390
219d8df8
DP		 391/*
392 * We can't use the same notifier block for more than one supply and
393 * there's no way I can see to get from a callback to the caller
394 * except container_of().
395 */
396#define WM8995_REGULATOR_EVENT(n) \
397static int wm8995_regulator_event_##n(struct notifier_block *nb, \
398 unsigned long event, void *data) \
399{ \
400 struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \
401 disable_nb[n]); \
402 if (event & REGULATOR_EVENT_DISABLE) { \
c42da642 403 regcache_mark_dirty(wm8995->regmap); \
219d8df8
DP		 404 } \
405 return 0; \
406}
407
408WM8995_REGULATOR_EVENT(0)
409WM8995_REGULATOR_EVENT(1)
410WM8995_REGULATOR_EVENT(2)
411WM8995_REGULATOR_EVENT(3)
412WM8995_REGULATOR_EVENT(4)
413WM8995_REGULATOR_EVENT(5)
414WM8995_REGULATOR_EVENT(6)
415WM8995_REGULATOR_EVENT(7)
416
6a504a75
DP		 417static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
418static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
419static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0);
420static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
421
422static const char *in1l_text[] = {
423 "Differential", "Single-ended IN1LN", "Single-ended IN1LP"
424};
425
426static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
427 2, in1l_text);
428
429static const char *in1r_text[] = {
430 "Differential", "Single-ended IN1RN", "Single-ended IN1RP"
431};
432
433static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
434 0, in1r_text);
435
436static const char *dmic_src_text[] = {
437 "DMICDAT1", "DMICDAT2", "DMICDAT3"
438};
439
440static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5,
441 8, dmic_src_text);
442static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5,
443 6, dmic_src_text);
444
445static const struct snd_kcontrol_new wm8995_snd_controls[] = {
446 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME,
447 WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
448 SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME,
449 WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1),
450
451 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME,
452 WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
453 SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME,
454 WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1),
455
456 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME,
457 WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
458 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME,
459 WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
460 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME,
461 WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
462
463 SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME,
464 WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv),
465
466 SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL,
467 4, 3, 0, in1l_boost_tlv),
468
469 SOC_ENUM("IN1L Mode", in1l_enum),
470 SOC_ENUM("IN1R Mode", in1r_enum),
471
472 SOC_ENUM("DMIC1 SRC", dmic_src1_enum),
473 SOC_ENUM("DMIC2 SRC", dmic_src2_enum),
474
475 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5,
476 24, 0, sidetone_tlv),
477 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5,
478 24, 0, sidetone_tlv),
479
480 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME,
481 WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
482 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME,
483 WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
484 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME,
485 WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv)
486};
487
488static void wm8995_update_class_w(struct snd_soc_codec *codec)
489{
490 int enable = 1;
491 int source = 0; /* GCC flow analysis can't track enable */
492 int reg, reg_r;
493
494 /* We also need the same setting for L/R and only one path */
495 reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING);
496 switch (reg) {
497 case WM8995_AIF2DACL_TO_DAC1L:
498 dev_dbg(codec->dev, "Class W source AIF2DAC\n");
499 source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT;
500 break;
501 case WM8995_AIF1DAC2L_TO_DAC1L:
502 dev_dbg(codec->dev, "Class W source AIF1DAC2\n");
503 source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT;
504 break;
505 case WM8995_AIF1DAC1L_TO_DAC1L:
506 dev_dbg(codec->dev, "Class W source AIF1DAC1\n");
507 source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT;
508 break;
509 default:
510 dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg);
511 enable = 0;
512 break;
513 }
514
515 reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING);
516 if (reg_r != reg) {
517 dev_dbg(codec->dev, "Left and right DAC mixers different\n");
518 enable = 0;
519 }
520
521 if (enable) {
522 dev_dbg(codec->dev, "Class W enabled\n");
523 snd_soc_update_bits(codec, WM8995_CLASS_W_1,
524 WM8995_CP_DYN_PWR_MASK |
525 WM8995_CP_DYN_SRC_SEL_MASK,
526 source | WM8995_CP_DYN_PWR);
527 } else {
528 dev_dbg(codec->dev, "Class W disabled\n");
529 snd_soc_update_bits(codec, WM8995_CLASS_W_1,
530 WM8995_CP_DYN_PWR_MASK, 0);
531 }
532}
533
534static int check_clk_sys(struct snd_soc_dapm_widget *source,
535 struct snd_soc_dapm_widget *sink)
536{
537 unsigned int reg;
538 const char *clk;
539
540 reg = snd_soc_read(source->codec, WM8995_CLOCKING_1);
541 /* Check what we're currently using for CLK_SYS */
542 if (reg & WM8995_SYSCLK_SRC)
543 clk = "AIF2CLK";
544 else
545 clk = "AIF1CLK";
546 return !strcmp(source->name, clk);
547}
548
549static int wm8995_put_class_w(struct snd_kcontrol *kcontrol,
550 struct snd_ctl_elem_value *ucontrol)
551{
9d03545d
JN		 552 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
553 struct snd_soc_dapm_widget *w = wlist->widgets[0];
6a504a75
DP		 554 struct snd_soc_codec *codec;
555 int ret;
556
6a504a75
DP		 557 codec = w->codec;
558 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
559 wm8995_update_class_w(codec);
560 return ret;
561}
562
563static int hp_supply_event(struct snd_soc_dapm_widget *w,
564 struct snd_kcontrol *kcontrol, int event)
565{
566 struct snd_soc_codec *codec;
567 struct wm8995_priv *wm8995;
568
569 codec = w->codec;
570 wm8995 = snd_soc_codec_get_drvdata(codec);
571
572 switch (event) {
573 case SND_SOC_DAPM_PRE_PMU:
574 /* Enable the headphone amp */
575 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
576 WM8995_HPOUT1L_ENA_MASK |
577 WM8995_HPOUT1R_ENA_MASK,
578 WM8995_HPOUT1L_ENA |
579 WM8995_HPOUT1R_ENA);
580
581 /* Enable the second stage */
582 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
583 WM8995_HPOUT1L_DLY_MASK |
584 WM8995_HPOUT1R_DLY_MASK,
585 WM8995_HPOUT1L_DLY |
586 WM8995_HPOUT1R_DLY);
587 break;
588 case SND_SOC_DAPM_PRE_PMD:
589 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
590 WM8995_CP_ENA_MASK, 0);
591 break;
592 }
593
594 return 0;
595}
596
597static void dc_servo_cmd(struct snd_soc_codec *codec,
598 unsigned int reg, unsigned int val, unsigned int mask)
599{
600 int timeout = 10;
601
602 dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
603 __func__, reg, val, mask);
604
605 snd_soc_write(codec, reg, val);
606 while (timeout--) {
607 msleep(10);
608 val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0);
609 if ((val & mask) == mask)
610 return;
611 }
612
613 dev_err(codec->dev, "Timed out waiting for DC Servo\n");
614}
615
616static int hp_event(struct snd_soc_dapm_widget *w,
617 struct snd_kcontrol *kcontrol, int event)
618{
619 struct snd_soc_codec *codec;
620 unsigned int reg;
621
622 codec = w->codec;
623 reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1);
624
625 switch (event) {
626 case SND_SOC_DAPM_POST_PMU:
627 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
628 WM8995_CP_ENA_MASK, WM8995_CP_ENA);
629
630 msleep(5);
631
632 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
633 WM8995_HPOUT1L_ENA_MASK |
634 WM8995_HPOUT1R_ENA_MASK,
635 WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA);
636
637 udelay(20);
638
639 reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY;
640 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
641
642 snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
643 WM8995_DCS_ENA_CHAN_1);
644
645 dc_servo_cmd(codec, WM8995_DC_SERVO_2,
646 WM8995_DCS_TRIG_STARTUP_0 |
647 WM8995_DCS_TRIG_STARTUP_1,
648 WM8995_DCS_TRIG_DAC_WR_0 |
649 WM8995_DCS_TRIG_DAC_WR_1);
650
651 reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT |
652 WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT;
653 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
654
655 break;
656 case SND_SOC_DAPM_PRE_PMD:
657 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
658 WM8995_HPOUT1L_OUTP_MASK |
659 WM8995_HPOUT1R_OUTP_MASK |
660 WM8995_HPOUT1L_RMV_SHORT_MASK |
661 WM8995_HPOUT1R_RMV_SHORT_MASK, 0);
662
663 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
664 WM8995_HPOUT1L_DLY_MASK |
665 WM8995_HPOUT1R_DLY_MASK, 0);
666
667 snd_soc_write(codec, WM8995_DC_SERVO_1, 0);
668
669 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
670 WM8995_HPOUT1L_ENA_MASK |
671 WM8995_HPOUT1R_ENA_MASK,
672 0);
673 break;
674 }
675
676 return 0;
677}
678
679static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
680{
681 struct wm8995_priv *wm8995;
682 int rate;
683 int reg1 = 0;
684 int offset;
685
686 wm8995 = snd_soc_codec_get_drvdata(codec);
687
688 if (aif)
689 offset = 4;
690 else
691 offset = 0;
692
693 switch (wm8995->sysclk[aif]) {
694 case WM8995_SYSCLK_MCLK1:
695 rate = wm8995->mclk[0];
696 break;
697 case WM8995_SYSCLK_MCLK2:
698 reg1 |= 0x8;
699 rate = wm8995->mclk[1];
700 break;
701 case WM8995_SYSCLK_FLL1:
702 reg1 |= 0x10;
703 rate = wm8995->fll[0].out;
704 break;
705 case WM8995_SYSCLK_FLL2:
706 reg1 |= 0x18;
707 rate = wm8995->fll[1].out;
708 break;
709 default:
710 return -EINVAL;
711 }
712
713 if (rate >= 13500000) {
714 rate /= 2;
715 reg1 |= WM8995_AIF1CLK_DIV;
716
717 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
718 aif + 1, rate);
719 }
720
721 wm8995->aifclk[aif] = rate;
722
723 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset,
724 WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK,
725 reg1);
726 return 0;
727}
728
729static int configure_clock(struct snd_soc_codec *codec)
730{
731 struct wm8995_priv *wm8995;
73478755 732 int change, new;
6a504a75
DP		 733
734 wm8995 = snd_soc_codec_get_drvdata(codec);
735
736 /* Bring up the AIF clocks first */
737 configure_aif_clock(codec, 0);
738 configure_aif_clock(codec, 1);
739
740 /*
741 * Then switch CLK_SYS over to the higher of them; a change
742 * can only happen as a result of a clocking change which can
743 * only be made outside of DAPM so we can safely redo the
744 * clocking.
745 */
746
747 /* If they're equal it doesn't matter which is used */
748 if (wm8995->aifclk[0] == wm8995->aifclk[1])
749 return 0;
750
751 if (wm8995->aifclk[0] < wm8995->aifclk[1])
752 new = WM8995_SYSCLK_SRC;
753 else
754 new = 0;
755
73478755
AL		 756 change = snd_soc_update_bits(codec, WM8995_CLOCKING_1,
757 WM8995_SYSCLK_SRC_MASK, new);
758 if (!change)
6a504a75
DP		 759 return 0;
760
6a504a75
DP		 761 snd_soc_dapm_sync(&codec->dapm);
762
763 return 0;
764}
765
766static int clk_sys_event(struct snd_soc_dapm_widget *w,
767 struct snd_kcontrol *kcontrol, int event)
768{
769 struct snd_soc_codec *codec;
770
771 codec = w->codec;
772
773 switch (event) {
774 case SND_SOC_DAPM_PRE_PMU:
775 return configure_clock(codec);
776
777 case SND_SOC_DAPM_POST_PMD:
778 configure_clock(codec);
779 break;
780 }
781
782 return 0;
783}
784
785static const char *sidetone_text[] = {
786 "ADC/DMIC1", "DMIC2",
787};
788
789static const struct soc_enum sidetone1_enum =
790 SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text);
791
792static const struct snd_kcontrol_new sidetone1_mux =
793 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
794
795static const struct soc_enum sidetone2_enum =
796 SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text);
797
798static const struct snd_kcontrol_new sidetone2_mux =
799 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
800
801static const struct snd_kcontrol_new aif1adc1l_mix[] = {
802 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
803 1, 1, 0),
804 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
805 0, 1, 0),
806};
807
808static const struct snd_kcontrol_new aif1adc1r_mix[] = {
809 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
810 1, 1, 0),
811 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
812 0, 1, 0),
813};
814
815static const struct snd_kcontrol_new aif1adc2l_mix[] = {
816 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
817 1, 1, 0),
818 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
819 0, 1, 0),
820};
821
822static const struct snd_kcontrol_new aif1adc2r_mix[] = {
823 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
824 1, 1, 0),
825 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
826 0, 1, 0),
827};
828
829static const struct snd_kcontrol_new dac1l_mix[] = {
830 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
831 5, 1, 0),
832 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
833 4, 1, 0),
834 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
835 2, 1, 0),
836 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
837 1, 1, 0),
838 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
839 0, 1, 0),
840};
841
842static const struct snd_kcontrol_new dac1r_mix[] = {
843 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
844 5, 1, 0),
845 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
846 4, 1, 0),
847 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
848 2, 1, 0),
849 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
850 1, 1, 0),
851 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
852 0, 1, 0),
853};
854
855static const struct snd_kcontrol_new aif2dac2l_mix[] = {
856 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
857 5, 1, 0),
858 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
859 4, 1, 0),
860 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
861 2, 1, 0),
862 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
863 1, 1, 0),
864 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
865 0, 1, 0),
866};
867
868static const struct snd_kcontrol_new aif2dac2r_mix[] = {
869 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
870 5, 1, 0),
871 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
872 4, 1, 0),
873 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
874 2, 1, 0),
875 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
876 1, 1, 0),
877 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
878 0, 1, 0),
879};
880
881static const struct snd_kcontrol_new in1l_pga =
882 SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0);
883
884static const struct snd_kcontrol_new in1r_pga =
885 SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0);
886
887static const char *adc_mux_text[] = {
888 "ADC",
889 "DMIC",
890};
891
892static const struct soc_enum adc_enum =
893 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
894
895static const struct snd_kcontrol_new adcl_mux =
896 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
897
898static const struct snd_kcontrol_new adcr_mux =
899 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
900
901static const char *spk_src_text[] = {
902 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
903};
904
905static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1,
906 0, spk_src_text);
907static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1,
908 0, spk_src_text);
909static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2,
910 0, spk_src_text);
911static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2,
912 0, spk_src_text);
913
914static const struct snd_kcontrol_new spk1l_mux =
915 SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum);
916static const struct snd_kcontrol_new spk1r_mux =
917 SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum);
918static const struct snd_kcontrol_new spk2l_mux =
919 SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum);
920static const struct snd_kcontrol_new spk2r_mux =
921 SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum);
922
923static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
924 SND_SOC_DAPM_INPUT("DMIC1DAT"),
925 SND_SOC_DAPM_INPUT("DMIC2DAT"),
926
927 SND_SOC_DAPM_INPUT("IN1L"),
928 SND_SOC_DAPM_INPUT("IN1R"),
929
930 SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0,
931 &in1l_pga, 1),
932 SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0,
933 &in1r_pga, 1),
934
9ce31623
MB		 935 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0,
936 NULL, 0),
937 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0,
938 NULL, 0),
6a504a75
DP		 939
940 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0),
941 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0),
942 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0),
943 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0),
944 SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0),
945 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
946 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
947
948 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0,
949 WM8995_POWER_MANAGEMENT_3, 9, 0),
950 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0,
951 WM8995_POWER_MANAGEMENT_3, 8, 0),
952 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0,
953 SND_SOC_NOPM, 0, 0),
954 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
955 0, WM8995_POWER_MANAGEMENT_3, 11, 0),
956 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
957 0, WM8995_POWER_MANAGEMENT_3, 10, 0),
958
959 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0,
960 &adcl_mux),
961 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
962 &adcr_mux),
963
964 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
965 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
966 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0),
967 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0),
968
969 SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0),
970 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
971
972 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
973 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
974 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
975 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
976 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
977 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
978 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
979 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
980
981 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
982 9, 0),
983 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
984 8, 0),
985 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM,
986 0, 0),
987
988 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
989 11, 0),
990 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
991 10, 0),
992
993 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
994 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
995 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
996 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
997
998 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0),
999 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0),
1000 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0),
1001 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0),
1002
1003 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix,
1004 ARRAY_SIZE(dac1l_mix)),
1005 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix,
1006 ARRAY_SIZE(dac1r_mix)),
1007
1008 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1009 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1010
1011 SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1012 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1013
1014 SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0,
1015 hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1016
1017 SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1,
1018 4, 0, &spk1l_mux),
1019 SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1,
1020 4, 0, &spk1r_mux),
1021 SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2,
1022 4, 0, &spk2l_mux),
1023 SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2,
1024 4, 0, &spk2r_mux),
1025
1026 SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
1027
1028 SND_SOC_DAPM_OUTPUT("HP1L"),
1029 SND_SOC_DAPM_OUTPUT("HP1R"),
1030 SND_SOC_DAPM_OUTPUT("SPK1L"),
1031 SND_SOC_DAPM_OUTPUT("SPK1R"),
1032 SND_SOC_DAPM_OUTPUT("SPK2L"),
1033 SND_SOC_DAPM_OUTPUT("SPK2R")
1034};
1035
1036static const struct snd_soc_dapm_route wm8995_intercon[] = {
1037 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1038 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1039
1040 { "DSP1CLK", NULL, "CLK_SYS" },
1041 { "DSP2CLK", NULL, "CLK_SYS" },
1042 { "SYSDSPCLK", NULL, "CLK_SYS" },
1043
1044 { "AIF1ADC1L", NULL, "AIF1CLK" },
1045 { "AIF1ADC1L", NULL, "DSP1CLK" },
1046 { "AIF1ADC1R", NULL, "AIF1CLK" },
1047 { "AIF1ADC1R", NULL, "DSP1CLK" },
1048 { "AIF1ADC1R", NULL, "SYSDSPCLK" },
1049
1050 { "AIF1ADC2L", NULL, "AIF1CLK" },
1051 { "AIF1ADC2L", NULL, "DSP1CLK" },
1052 { "AIF1ADC2R", NULL, "AIF1CLK" },
1053 { "AIF1ADC2R", NULL, "DSP1CLK" },
1054 { "AIF1ADC2R", NULL, "SYSDSPCLK" },
1055
1056 { "DMIC1L", NULL, "DMIC1DAT" },
1057 { "DMIC1L", NULL, "CLK_SYS" },
1058 { "DMIC1R", NULL, "DMIC1DAT" },
1059 { "DMIC1R", NULL, "CLK_SYS" },
1060 { "DMIC2L", NULL, "DMIC2DAT" },
1061 { "DMIC2L", NULL, "CLK_SYS" },
1062 { "DMIC2R", NULL, "DMIC2DAT" },
1063 { "DMIC2R", NULL, "CLK_SYS" },
1064
1065 { "ADCL", NULL, "AIF1CLK" },
1066 { "ADCL", NULL, "DSP1CLK" },
1067 { "ADCL", NULL, "SYSDSPCLK" },
1068
1069 { "ADCR", NULL, "AIF1CLK" },
1070 { "ADCR", NULL, "DSP1CLK" },
1071 { "ADCR", NULL, "SYSDSPCLK" },
1072
1073 { "IN1L PGA", "IN1L Switch", "IN1L" },
1074 { "IN1R PGA", "IN1R Switch", "IN1R" },
1075 { "IN1L PGA", NULL, "LDO2" },
1076 { "IN1R PGA", NULL, "LDO2" },
1077
1078 { "ADCL", NULL, "IN1L PGA" },
1079 { "ADCR", NULL, "IN1R PGA" },
1080
1081 { "ADCL Mux", "ADC", "ADCL" },
1082 { "ADCL Mux", "DMIC", "DMIC1L" },
1083 { "ADCR Mux", "ADC", "ADCR" },
1084 { "ADCR Mux", "DMIC", "DMIC1R" },
1085
1086 /* AIF1 outputs */
1087 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1088 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1089
1090 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1091 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1092
1093 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1094 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1095
1096 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1097 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1098
1099 /* Sidetone */
1100 { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" },
1101 { "Left Sidetone", "DMIC2", "AIF1ADC2L" },
1102 { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" },
1103 { "Right Sidetone", "DMIC2", "AIF1ADC2R" },
1104
1105 { "AIF1DAC1L", NULL, "AIF1CLK" },
1106 { "AIF1DAC1L", NULL, "DSP1CLK" },
1107 { "AIF1DAC1R", NULL, "AIF1CLK" },
1108 { "AIF1DAC1R", NULL, "DSP1CLK" },
1109 { "AIF1DAC1R", NULL, "SYSDSPCLK" },
1110
1111 { "AIF1DAC2L", NULL, "AIF1CLK" },
1112 { "AIF1DAC2L", NULL, "DSP1CLK" },
1113 { "AIF1DAC2R", NULL, "AIF1CLK" },
1114 { "AIF1DAC2R", NULL, "DSP1CLK" },
1115 { "AIF1DAC2R", NULL, "SYSDSPCLK" },
1116
1117 { "DAC1L", NULL, "AIF1CLK" },
1118 { "DAC1L", NULL, "DSP1CLK" },
1119 { "DAC1L", NULL, "SYSDSPCLK" },
1120
1121 { "DAC1R", NULL, "AIF1CLK" },
1122 { "DAC1R", NULL, "DSP1CLK" },
1123 { "DAC1R", NULL, "SYSDSPCLK" },
1124
1125 { "AIF1DAC1L", NULL, "AIF1DACDAT" },
1126 { "AIF1DAC1R", NULL, "AIF1DACDAT" },
1127 { "AIF1DAC2L", NULL, "AIF1DACDAT" },
1128 { "AIF1DAC2R", NULL, "AIF1DACDAT" },
1129
1130 /* DAC1 inputs */
1131 { "DAC1L", NULL, "DAC1L Mixer" },
1132 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1133 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1134 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1135 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1136
1137 { "DAC1R", NULL, "DAC1R Mixer" },
1138 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1139 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1140 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1141 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1142
1143 /* DAC2/AIF2 outputs */
1144 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1145 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1146 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1147
1148 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1149 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1150 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1151
1152 /* Output stages */
1153 { "Headphone PGA", NULL, "DAC1L" },
1154 { "Headphone PGA", NULL, "DAC1R" },
1155
1156 { "Headphone PGA", NULL, "DAC2L" },
1157 { "Headphone PGA", NULL, "DAC2R" },
1158
1159 { "Headphone PGA", NULL, "Headphone Supply" },
1160 { "Headphone PGA", NULL, "CLK_SYS" },
1161 { "Headphone PGA", NULL, "LDO2" },
1162
1163 { "HP1L", NULL, "Headphone PGA" },
1164 { "HP1R", NULL, "Headphone PGA" },
1165
1166 { "SPK1L Driver", "DAC1L", "DAC1L" },
1167 { "SPK1L Driver", "DAC1R", "DAC1R" },
1168 { "SPK1L Driver", "DAC2L", "DAC2L" },
1169 { "SPK1L Driver", "DAC2R", "DAC2R" },
1170 { "SPK1L Driver", NULL, "CLK_SYS" },
1171
1172 { "SPK1R Driver", "DAC1L", "DAC1L" },
1173 { "SPK1R Driver", "DAC1R", "DAC1R" },
1174 { "SPK1R Driver", "DAC2L", "DAC2L" },
1175 { "SPK1R Driver", "DAC2R", "DAC2R" },
1176 { "SPK1R Driver", NULL, "CLK_SYS" },
1177
1178 { "SPK2L Driver", "DAC1L", "DAC1L" },
1179 { "SPK2L Driver", "DAC1R", "DAC1R" },
1180 { "SPK2L Driver", "DAC2L", "DAC2L" },
1181 { "SPK2L Driver", "DAC2R", "DAC2R" },
1182 { "SPK2L Driver", NULL, "CLK_SYS" },
1183
1184 { "SPK2R Driver", "DAC1L", "DAC1L" },
1185 { "SPK2R Driver", "DAC1R", "DAC1R" },
1186 { "SPK2R Driver", "DAC2L", "DAC2L" },
1187 { "SPK2R Driver", "DAC2R", "DAC2R" },
1188 { "SPK2R Driver", NULL, "CLK_SYS" },
1189
1190 { "SPK1L", NULL, "SPK1L Driver" },
1191 { "SPK1R", NULL, "SPK1R Driver" },
1192 { "SPK2L", NULL, "SPK2L Driver" },
1193 { "SPK2R", NULL, "SPK2R Driver" }
1194};
1195
c42da642 1196static bool wm8995_readable(struct device *dev, unsigned int reg)
6a504a75 1197{
6a504a75
DP		 1198 switch (reg) {
1199 case WM8995_SOFTWARE_RESET:
c42da642
MB		 1200 case WM8995_POWER_MANAGEMENT_1:
1201 case WM8995_POWER_MANAGEMENT_2:
1202 case WM8995_POWER_MANAGEMENT_3:
1203 case WM8995_POWER_MANAGEMENT_4:
1204 case WM8995_POWER_MANAGEMENT_5:
1205 case WM8995_LEFT_LINE_INPUT_1_VOLUME:
1206 case WM8995_RIGHT_LINE_INPUT_1_VOLUME:
1207 case WM8995_LEFT_LINE_INPUT_CONTROL:
1208 case WM8995_DAC1_LEFT_VOLUME:
1209 case WM8995_DAC1_RIGHT_VOLUME:
1210 case WM8995_DAC2_LEFT_VOLUME:
1211 case WM8995_DAC2_RIGHT_VOLUME:
1212 case WM8995_OUTPUT_VOLUME_ZC_1:
1213 case WM8995_MICBIAS_1:
1214 case WM8995_MICBIAS_2:
1215 case WM8995_LDO_1:
1216 case WM8995_LDO_2:
1217 case WM8995_ACCESSORY_DETECT_MODE1:
1218 case WM8995_ACCESSORY_DETECT_MODE2:
1219 case WM8995_HEADPHONE_DETECT1:
1220 case WM8995_HEADPHONE_DETECT2:
1221 case WM8995_MIC_DETECT_1:
1222 case WM8995_MIC_DETECT_2:
1223 case WM8995_CHARGE_PUMP_1:
1224 case WM8995_CLASS_W_1:
1225 case WM8995_DC_SERVO_1:
1226 case WM8995_DC_SERVO_2:
1227 case WM8995_DC_SERVO_3:
1228 case WM8995_DC_SERVO_5:
1229 case WM8995_DC_SERVO_6:
1230 case WM8995_DC_SERVO_7:
6a504a75 1231 case WM8995_DC_SERVO_READBACK_0:
c42da642
MB		 1232 case WM8995_ANALOGUE_HP_1:
1233 case WM8995_ANALOGUE_HP_2:
1234 case WM8995_CHIP_REVISION:
1235 case WM8995_CONTROL_INTERFACE_1:
1236 case WM8995_CONTROL_INTERFACE_2:
1237 case WM8995_WRITE_SEQUENCER_CTRL_1:
1238 case WM8995_WRITE_SEQUENCER_CTRL_2:
1239 case WM8995_AIF1_CLOCKING_1:
1240 case WM8995_AIF1_CLOCKING_2:
1241 case WM8995_AIF2_CLOCKING_1:
1242 case WM8995_AIF2_CLOCKING_2:
1243 case WM8995_CLOCKING_1:
1244 case WM8995_CLOCKING_2:
1245 case WM8995_AIF1_RATE:
1246 case WM8995_AIF2_RATE:
1247 case WM8995_RATE_STATUS:
1248 case WM8995_FLL1_CONTROL_1:
1249 case WM8995_FLL1_CONTROL_2:
1250 case WM8995_FLL1_CONTROL_3:
1251 case WM8995_FLL1_CONTROL_4:
1252 case WM8995_FLL1_CONTROL_5:
1253 case WM8995_FLL2_CONTROL_1:
1254 case WM8995_FLL2_CONTROL_2:
1255 case WM8995_FLL2_CONTROL_3:
1256 case WM8995_FLL2_CONTROL_4:
1257 case WM8995_FLL2_CONTROL_5:
1258 case WM8995_AIF1_CONTROL_1:
1259 case WM8995_AIF1_CONTROL_2:
1260 case WM8995_AIF1_MASTER_SLAVE:
1261 case WM8995_AIF1_BCLK:
1262 case WM8995_AIF1ADC_LRCLK:
1263 case WM8995_AIF1DAC_LRCLK:
1264 case WM8995_AIF1DAC_DATA:
1265 case WM8995_AIF1ADC_DATA:
1266 case WM8995_AIF2_CONTROL_1:
1267 case WM8995_AIF2_CONTROL_2:
1268 case WM8995_AIF2_MASTER_SLAVE:
1269 case WM8995_AIF2_BCLK:
1270 case WM8995_AIF2ADC_LRCLK:
1271 case WM8995_AIF2DAC_LRCLK:
1272 case WM8995_AIF2DAC_DATA:
1273 case WM8995_AIF2ADC_DATA:
1274 case WM8995_AIF1_ADC1_LEFT_VOLUME:
1275 case WM8995_AIF1_ADC1_RIGHT_VOLUME:
1276 case WM8995_AIF1_DAC1_LEFT_VOLUME:
1277 case WM8995_AIF1_DAC1_RIGHT_VOLUME:
1278 case WM8995_AIF1_ADC2_LEFT_VOLUME:
1279 case WM8995_AIF1_ADC2_RIGHT_VOLUME:
1280 case WM8995_AIF1_DAC2_LEFT_VOLUME:
1281 case WM8995_AIF1_DAC2_RIGHT_VOLUME:
1282 case WM8995_AIF1_ADC1_FILTERS:
1283 case WM8995_AIF1_ADC2_FILTERS:
1284 case WM8995_AIF1_DAC1_FILTERS_1:
1285 case WM8995_AIF1_DAC1_FILTERS_2:
1286 case WM8995_AIF1_DAC2_FILTERS_1:
1287 case WM8995_AIF1_DAC2_FILTERS_2:
1288 case WM8995_AIF1_DRC1_1:
1289 case WM8995_AIF1_DRC1_2:
1290 case WM8995_AIF1_DRC1_3:
1291 case WM8995_AIF1_DRC1_4:
1292 case WM8995_AIF1_DRC1_5:
1293 case WM8995_AIF1_DRC2_1:
1294 case WM8995_AIF1_DRC2_2:
1295 case WM8995_AIF1_DRC2_3:
1296 case WM8995_AIF1_DRC2_4:
1297 case WM8995_AIF1_DRC2_5:
1298 case WM8995_AIF1_DAC1_EQ_GAINS_1:
1299 case WM8995_AIF1_DAC1_EQ_GAINS_2:
1300 case WM8995_AIF1_DAC1_EQ_BAND_1_A:
1301 case WM8995_AIF1_DAC1_EQ_BAND_1_B:
1302 case WM8995_AIF1_DAC1_EQ_BAND_1_PG:
1303 case WM8995_AIF1_DAC1_EQ_BAND_2_A:
1304 case WM8995_AIF1_DAC1_EQ_BAND_2_B:
1305 case WM8995_AIF1_DAC1_EQ_BAND_2_C:
1306 case WM8995_AIF1_DAC1_EQ_BAND_2_PG:
1307 case WM8995_AIF1_DAC1_EQ_BAND_3_A:
1308 case WM8995_AIF1_DAC1_EQ_BAND_3_B:
1309 case WM8995_AIF1_DAC1_EQ_BAND_3_C:
1310 case WM8995_AIF1_DAC1_EQ_BAND_3_PG:
1311 case WM8995_AIF1_DAC1_EQ_BAND_4_A:
1312 case WM8995_AIF1_DAC1_EQ_BAND_4_B:
1313 case WM8995_AIF1_DAC1_EQ_BAND_4_C:
1314 case WM8995_AIF1_DAC1_EQ_BAND_4_PG:
1315 case WM8995_AIF1_DAC1_EQ_BAND_5_A:
1316 case WM8995_AIF1_DAC1_EQ_BAND_5_B:
1317 case WM8995_AIF1_DAC1_EQ_BAND_5_PG:
1318 case WM8995_AIF1_DAC2_EQ_GAINS_1:
1319 case WM8995_AIF1_DAC2_EQ_GAINS_2:
1320 case WM8995_AIF1_DAC2_EQ_BAND_1_A:
1321 case WM8995_AIF1_DAC2_EQ_BAND_1_B:
1322 case WM8995_AIF1_DAC2_EQ_BAND_1_PG:
1323 case WM8995_AIF1_DAC2_EQ_BAND_2_A:
1324 case WM8995_AIF1_DAC2_EQ_BAND_2_B:
1325 case WM8995_AIF1_DAC2_EQ_BAND_2_C:
1326 case WM8995_AIF1_DAC2_EQ_BAND_2_PG:
1327 case WM8995_AIF1_DAC2_EQ_BAND_3_A:
1328 case WM8995_AIF1_DAC2_EQ_BAND_3_B:
1329 case WM8995_AIF1_DAC2_EQ_BAND_3_C:
1330 case WM8995_AIF1_DAC2_EQ_BAND_3_PG:
1331 case WM8995_AIF1_DAC2_EQ_BAND_4_A:
1332 case WM8995_AIF1_DAC2_EQ_BAND_4_B:
1333 case WM8995_AIF1_DAC2_EQ_BAND_4_C:
1334 case WM8995_AIF1_DAC2_EQ_BAND_4_PG:
1335 case WM8995_AIF1_DAC2_EQ_BAND_5_A:
1336 case WM8995_AIF1_DAC2_EQ_BAND_5_B:
1337 case WM8995_AIF1_DAC2_EQ_BAND_5_PG:
1338 case WM8995_AIF2_ADC_LEFT_VOLUME:
1339 case WM8995_AIF2_ADC_RIGHT_VOLUME:
1340 case WM8995_AIF2_DAC_LEFT_VOLUME:
1341 case WM8995_AIF2_DAC_RIGHT_VOLUME:
1342 case WM8995_AIF2_ADC_FILTERS:
1343 case WM8995_AIF2_DAC_FILTERS_1:
1344 case WM8995_AIF2_DAC_FILTERS_2:
1345 case WM8995_AIF2_DRC_1:
1346 case WM8995_AIF2_DRC_2:
1347 case WM8995_AIF2_DRC_3:
1348 case WM8995_AIF2_DRC_4:
1349 case WM8995_AIF2_DRC_5:
1350 case WM8995_AIF2_EQ_GAINS_1:
1351 case WM8995_AIF2_EQ_GAINS_2:
1352 case WM8995_AIF2_EQ_BAND_1_A:
1353 case WM8995_AIF2_EQ_BAND_1_B:
1354 case WM8995_AIF2_EQ_BAND_1_PG:
1355 case WM8995_AIF2_EQ_BAND_2_A:
1356 case WM8995_AIF2_EQ_BAND_2_B:
1357 case WM8995_AIF2_EQ_BAND_2_C:
1358 case WM8995_AIF2_EQ_BAND_2_PG:
1359 case WM8995_AIF2_EQ_BAND_3_A:
1360 case WM8995_AIF2_EQ_BAND_3_B:
1361 case WM8995_AIF2_EQ_BAND_3_C:
1362 case WM8995_AIF2_EQ_BAND_3_PG:
1363 case WM8995_AIF2_EQ_BAND_4_A:
1364 case WM8995_AIF2_EQ_BAND_4_B:
1365 case WM8995_AIF2_EQ_BAND_4_C:
1366 case WM8995_AIF2_EQ_BAND_4_PG:
1367 case WM8995_AIF2_EQ_BAND_5_A:
1368 case WM8995_AIF2_EQ_BAND_5_B:
1369 case WM8995_AIF2_EQ_BAND_5_PG:
1370 case WM8995_DAC1_MIXER_VOLUMES:
1371 case WM8995_DAC1_LEFT_MIXER_ROUTING:
1372 case WM8995_DAC1_RIGHT_MIXER_ROUTING:
1373 case WM8995_DAC2_MIXER_VOLUMES:
1374 case WM8995_DAC2_LEFT_MIXER_ROUTING:
1375 case WM8995_DAC2_RIGHT_MIXER_ROUTING:
1376 case WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING:
1377 case WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING:
1378 case WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING:
1379 case WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING:
1380 case WM8995_DAC_SOFTMUTE:
1381 case WM8995_OVERSAMPLING:
1382 case WM8995_SIDETONE:
1383 case WM8995_GPIO_1:
1384 case WM8995_GPIO_2:
1385 case WM8995_GPIO_3:
1386 case WM8995_GPIO_4:
1387 case WM8995_GPIO_5:
1388 case WM8995_GPIO_6:
1389 case WM8995_GPIO_7:
1390 case WM8995_GPIO_8:
1391 case WM8995_GPIO_9:
1392 case WM8995_GPIO_10:
1393 case WM8995_GPIO_11:
1394 case WM8995_GPIO_12:
1395 case WM8995_GPIO_13:
1396 case WM8995_GPIO_14:
1397 case WM8995_PULL_CONTROL_1:
1398 case WM8995_PULL_CONTROL_2:
6a504a75
DP		 1399 case WM8995_INTERRUPT_STATUS_1:
1400 case WM8995_INTERRUPT_STATUS_2:
c42da642 1401 case WM8995_INTERRUPT_RAW_STATUS_2:
6a504a75
DP		 1402 case WM8995_INTERRUPT_STATUS_1_MASK:
1403 case WM8995_INTERRUPT_STATUS_2_MASK:
1404 case WM8995_INTERRUPT_CONTROL:
c42da642
MB		 1405 case WM8995_LEFT_PDM_SPEAKER_1:
1406 case WM8995_RIGHT_PDM_SPEAKER_1:
1407 case WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE:
1408 case WM8995_LEFT_PDM_SPEAKER_2:
1409 case WM8995_RIGHT_PDM_SPEAKER_2:
1410 case WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE:
1411 return true;
1412 default:
1413 return false;
1414 }
1415}
1416
1417static bool wm8995_volatile(struct device *dev, unsigned int reg)
1418{
1419 switch (reg) {
1420 case WM8995_SOFTWARE_RESET:
1421 case WM8995_DC_SERVO_READBACK_0:
1422 case WM8995_INTERRUPT_STATUS_1:
1423 case WM8995_INTERRUPT_STATUS_2:
1424 case WM8995_INTERRUPT_CONTROL:
6a504a75
DP		 1425 case WM8995_ACCESSORY_DETECT_MODE1:
1426 case WM8995_ACCESSORY_DETECT_MODE2:
1427 case WM8995_HEADPHONE_DETECT1:
1428 case WM8995_HEADPHONE_DETECT2:
c42da642
MB		 1429 case WM8995_RATE_STATUS:
1430 return true;
1431 default:
1432 return false;
6a504a75 1433 }
6a504a75
DP		 1434}
1435
1436static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute)
1437{
1438 struct snd_soc_codec *codec = dai->codec;
1439 int mute_reg;
1440
1441 switch (dai->id) {
1442 case 0:
1443 mute_reg = WM8995_AIF1_DAC1_FILTERS_1;
1444 break;
1445 case 1:
1446 mute_reg = WM8995_AIF2_DAC_FILTERS_1;
1447 break;
1448 default:
1449 return -EINVAL;
1450 }
1451
1452 snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
1453 !!mute << WM8995_AIF1DAC1_MUTE_SHIFT);
1454 return 0;
1455}
1456
1457static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1458{
1459 struct snd_soc_codec *codec;
1460 int master;
1461 int aif;
1462
1463 codec = dai->codec;
1464
1465 master = 0;
1466 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1467 case SND_SOC_DAIFMT_CBS_CFS:
1468 break;
1469 case SND_SOC_DAIFMT_CBM_CFM:
1470 master = WM8995_AIF1_MSTR;
1471 break;
1472 default:
1473 dev_err(dai->dev, "Unknown master/slave configuration\n");
1474 return -EINVAL;
1475 }
1476
1477 aif = 0;
1478 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1479 case SND_SOC_DAIFMT_DSP_B:
1480 aif |= WM8995_AIF1_LRCLK_INV;
1481 case SND_SOC_DAIFMT_DSP_A:
1482 aif |= (0x3 << WM8995_AIF1_FMT_SHIFT);
1483 break;
1484 case SND_SOC_DAIFMT_I2S:
1485 aif |= (0x2 << WM8995_AIF1_FMT_SHIFT);
1486 break;
1487 case SND_SOC_DAIFMT_RIGHT_J:
1488 break;
1489 case SND_SOC_DAIFMT_LEFT_J:
1490 aif |= (0x1 << WM8995_AIF1_FMT_SHIFT);
1491 break;
1492 default:
1493 dev_err(dai->dev, "Unknown dai format\n");
1494 return -EINVAL;
1495 }
1496
1497 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1498 case SND_SOC_DAIFMT_DSP_A:
1499 case SND_SOC_DAIFMT_DSP_B:
1500 /* frame inversion not valid for DSP modes */
1501 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1502 case SND_SOC_DAIFMT_NB_NF:
1503 break;
1504 case SND_SOC_DAIFMT_IB_NF:
1505 aif |= WM8995_AIF1_BCLK_INV;
1506 break;
1507 default:
1508 return -EINVAL;
1509 }
1510 break;
1511
1512 case SND_SOC_DAIFMT_I2S:
1513 case SND_SOC_DAIFMT_RIGHT_J:
1514 case SND_SOC_DAIFMT_LEFT_J:
1515 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1516 case SND_SOC_DAIFMT_NB_NF:
1517 break;
1518 case SND_SOC_DAIFMT_IB_IF:
1519 aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV;
1520 break;
1521 case SND_SOC_DAIFMT_IB_NF:
1522 aif |= WM8995_AIF1_BCLK_INV;
1523 break;
1524 case SND_SOC_DAIFMT_NB_IF:
1525 aif |= WM8995_AIF1_LRCLK_INV;
1526 break;
1527 default:
1528 return -EINVAL;
1529 }
1530 break;
1531 default:
1532 return -EINVAL;
1533 }
1534
1535 snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1,
1536 WM8995_AIF1_BCLK_INV_MASK |
1537 WM8995_AIF1_LRCLK_INV_MASK |
1538 WM8995_AIF1_FMT_MASK, aif);
1539 snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE,
1540 WM8995_AIF1_MSTR_MASK, master);
1541 return 0;
1542}
1543
1544static const int srs[] = {
1545 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100,
1546 48000, 88200, 96000
1547};
1548
1549static const int fs_ratios[] = {
1550 -1 /* reserved */,
1551 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
1552};
1553
1554static const int bclk_divs[] = {
1555 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480
1556};
1557
1558static int wm8995_hw_params(struct snd_pcm_substream *substream,
1559 struct snd_pcm_hw_params *params,
1560 struct snd_soc_dai *dai)
1561{
1562 struct snd_soc_codec *codec;
1563 struct wm8995_priv *wm8995;
1564 int aif1_reg;
1565 int bclk_reg;
1566 int lrclk_reg;
1567 int rate_reg;
1568 int bclk_rate;
1569 int aif1;
1570 int lrclk, bclk;
1571 int i, rate_val, best, best_val, cur_val;
1572
1573 codec = dai->codec;
1574 wm8995 = snd_soc_codec_get_drvdata(codec);
1575
1576 switch (dai->id) {
1577 case 0:
1578 aif1_reg = WM8995_AIF1_CONTROL_1;
1579 bclk_reg = WM8995_AIF1_BCLK;
1580 rate_reg = WM8995_AIF1_RATE;
1581 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1582 wm8995->lrclk_shared[0] */) {
1583 lrclk_reg = WM8995_AIF1DAC_LRCLK;
1584 } else {
1585 lrclk_reg = WM8995_AIF1ADC_LRCLK;
1586 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
1587 }
1588 break;
1589 case 1:
1590 aif1_reg = WM8995_AIF2_CONTROL_1;
1591 bclk_reg = WM8995_AIF2_BCLK;
1592 rate_reg = WM8995_AIF2_RATE;
1593 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1594 wm8995->lrclk_shared[1] */) {
1595 lrclk_reg = WM8995_AIF2DAC_LRCLK;
1596 } else {
1597 lrclk_reg = WM8995_AIF2ADC_LRCLK;
1598 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
1599 }
1600 break;
1601 default:
1602 return -EINVAL;
1603 }
1604
1605 bclk_rate = snd_soc_params_to_bclk(params);
1606 if (bclk_rate < 0)
1607 return bclk_rate;
1608
1609 aif1 = 0;
1610 switch (params_format(params)) {
1611 case SNDRV_PCM_FORMAT_S16_LE:
1612 break;
1613 case SNDRV_PCM_FORMAT_S20_3LE:
1614 aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT);
1615 break;
1616 case SNDRV_PCM_FORMAT_S24_LE:
1617 aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT);
1618 break;
1619 case SNDRV_PCM_FORMAT_S32_LE:
1620 aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT);
1621 break;
1622 default:
1623 dev_err(dai->dev, "Unsupported word length %u\n",
1624 params_format(params));
1625 return -EINVAL;
1626 }
1627
1628 /* try to find a suitable sample rate */
1629 for (i = 0; i < ARRAY_SIZE(srs); ++i)
1630 if (srs[i] == params_rate(params))
1631 break;
1632 if (i == ARRAY_SIZE(srs)) {
1633 dev_err(dai->dev, "Sample rate %d is not supported\n",
1634 params_rate(params));
1635 return -EINVAL;
1636 }
1637 rate_val = i << WM8995_AIF1_SR_SHIFT;
1638
1639 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
1640 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1641 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
1642
1643 /* AIFCLK/fs ratio; look for a close match in either direction */
1644 best = 1;
1645 best_val = abs((fs_ratios[1] * params_rate(params))
1646 - wm8995->aifclk[dai->id]);
1647 for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) {
1648 cur_val = abs((fs_ratios[i] * params_rate(params))
1649 - wm8995->aifclk[dai->id]);
1650 if (cur_val >= best_val)
1651 continue;
1652 best = i;
1653 best_val = cur_val;
1654 }
1655 rate_val |= best;
1656
1657 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1658 dai->id + 1, fs_ratios[best]);
1659
1660 /*
1661 * We may not get quite the right frequency if using
1662 * approximate clocks so look for the closest match that is
1663 * higher than the target (we need to ensure that there enough
1664 * BCLKs to clock out the samples).
1665 */
1666 best = 0;
1667 bclk = 0;
1668 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1669 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
1670 if (cur_val < 0) /* BCLK table is sorted */
1671 break;
1672 best = i;
1673 }
1674 bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT;
1675
1676 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
1677 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1678 bclk_divs[best], bclk_rate);
1679
1680 lrclk = bclk_rate / params_rate(params);
1681 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1682 lrclk, bclk_rate / lrclk);
1683
1684 snd_soc_update_bits(codec, aif1_reg,
1685 WM8995_AIF1_WL_MASK, aif1);
1686 snd_soc_update_bits(codec, bclk_reg,
1687 WM8995_AIF1_BCLK_DIV_MASK, bclk);
1688 snd_soc_update_bits(codec, lrclk_reg,
1689 WM8995_AIF1DAC_RATE_MASK, lrclk);
1690 snd_soc_update_bits(codec, rate_reg,
1691 WM8995_AIF1_SR_MASK |
1692 WM8995_AIF1CLK_RATE_MASK, rate_val);
1693 return 0;
1694}
1695
1696static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
1697{
1698 struct snd_soc_codec *codec = codec_dai->codec;
1699 int reg, val, mask;
1700
1701 switch (codec_dai->id) {
1702 case 0:
1703 reg = WM8995_AIF1_MASTER_SLAVE;
1704 mask = WM8995_AIF1_TRI;
1705 break;
1706 case 1:
1707 reg = WM8995_AIF2_MASTER_SLAVE;
1708 mask = WM8995_AIF2_TRI;
1709 break;
1710 case 2:
1711 reg = WM8995_POWER_MANAGEMENT_5;
1712 mask = WM8995_AIF3_TRI;
1713 break;
1714 default:
1715 return -EINVAL;
1716 }
1717
1718 if (tristate)
1719 val = mask;
1720 else
1721 val = 0;
1722
a2828792 1723 return snd_soc_update_bits(codec, reg, mask, val);
6a504a75
DP		 1724}
1725
1726/* The size in bits of the FLL divide multiplied by 10
1727 * to allow rounding later */
1728#define FIXED_FLL_SIZE ((1 << 16) * 10)
1729
1730struct fll_div {
1731 u16 outdiv;
1732 u16 n;
1733 u16 k;
1734 u16 clk_ref_div;
1735 u16 fll_fratio;
1736};
1737
1738static int wm8995_get_fll_config(struct fll_div *fll,
1739 int freq_in, int freq_out)
1740{
1741 u64 Kpart;
1742 unsigned int K, Ndiv, Nmod;
1743
1744 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1745
1746 /* Scale the input frequency down to <= 13.5MHz */
1747 fll->clk_ref_div = 0;
1748 while (freq_in > 13500000) {
1749 fll->clk_ref_div++;
1750 freq_in /= 2;
1751
1752 if (fll->clk_ref_div > 3)
1753 return -EINVAL;
1754 }
1755 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1756
1757 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1758 fll->outdiv = 3;
1759 while (freq_out * (fll->outdiv + 1) < 90000000) {
1760 fll->outdiv++;
1761 if (fll->outdiv > 63)
1762 return -EINVAL;
1763 }
1764 freq_out *= fll->outdiv + 1;
1765 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1766
1767 if (freq_in > 1000000) {
1768 fll->fll_fratio = 0;
1769 } else if (freq_in > 256000) {
1770 fll->fll_fratio = 1;
1771 freq_in *= 2;
1772 } else if (freq_in > 128000) {
1773 fll->fll_fratio = 2;
1774 freq_in *= 4;
1775 } else if (freq_in > 64000) {
1776 fll->fll_fratio = 3;
1777 freq_in *= 8;
1778 } else {
1779 fll->fll_fratio = 4;
1780 freq_in *= 16;
1781 }
1782 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1783
1784 /* Now, calculate N.K */
1785 Ndiv = freq_out / freq_in;
1786
1787 fll->n = Ndiv;
1788 Nmod = freq_out % freq_in;
1789 pr_debug("Nmod=%d\n", Nmod);
1790
1791 /* Calculate fractional part - scale up so we can round. */
1792 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1793
1794 do_div(Kpart, freq_in);
1795
1796 K = Kpart & 0xFFFFFFFF;
1797
1798 if ((K % 10) >= 5)
1799 K += 5;
1800
1801 /* Move down to proper range now rounding is done */
1802 fll->k = K / 10;
1803
1804 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1805
1806 return 0;
1807}
1808
1809static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
1810 int src, unsigned int freq_in,
1811 unsigned int freq_out)
1812{
1813 struct snd_soc_codec *codec;
1814 struct wm8995_priv *wm8995;
1815 int reg_offset, ret;
1816 struct fll_div fll;
1817 u16 reg, aif1, aif2;
1818
1819 codec = dai->codec;
1820 wm8995 = snd_soc_codec_get_drvdata(codec);
1821
1822 aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1)
1823 & WM8995_AIF1CLK_ENA;
1824
1825 aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1)
1826 & WM8995_AIF2CLK_ENA;
1827
1828 switch (id) {
1829 case WM8995_FLL1:
1830 reg_offset = 0;
1831 id = 0;
1832 break;
1833 case WM8995_FLL2:
1834 reg_offset = 0x20;
1835 id = 1;
1836 break;
1837 default:
1838 return -EINVAL;
1839 }
1840
1841 switch (src) {
1842 case 0:
1843 /* Allow no source specification when stopping */
1844 if (freq_out)
1845 return -EINVAL;
1846 break;
1847 case WM8995_FLL_SRC_MCLK1:
1848 case WM8995_FLL_SRC_MCLK2:
1849 case WM8995_FLL_SRC_LRCLK:
1850 case WM8995_FLL_SRC_BCLK:
1851 break;
1852 default:
1853 return -EINVAL;
1854 }
1855
1856 /* Are we changing anything? */
1857 if (wm8995->fll[id].src == src &&
1858 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out)
1859 return 0;
1860
1861 /* If we're stopping the FLL redo the old config - no
1862 * registers will actually be written but we avoid GCC flow
1863 * analysis bugs spewing warnings.
1864 */
1865 if (freq_out)
1866 ret = wm8995_get_fll_config(&fll, freq_in, freq_out);
1867 else
1868 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in,
1869 wm8995->fll[id].out);
1870 if (ret < 0)
1871 return ret;
1872
1873 /* Gate the AIF clocks while we reclock */
1874 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
1875 WM8995_AIF1CLK_ENA_MASK, 0);
1876 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
1877 WM8995_AIF2CLK_ENA_MASK, 0);
1878
1879 /* We always need to disable the FLL while reconfiguring */
1880 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
1881 WM8995_FLL1_ENA_MASK, 0);
1882
1883 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) |
1884 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT);
1885 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset,
1886 WM8995_FLL1_OUTDIV_MASK |
1887 WM8995_FLL1_FRATIO_MASK, reg);
1888
1889 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
1890
1891 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset,
1892 WM8995_FLL1_N_MASK,
1893 fll.n << WM8995_FLL1_N_SHIFT);
1894
1895 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset,
1896 WM8995_FLL1_REFCLK_DIV_MASK |
1897 WM8995_FLL1_REFCLK_SRC_MASK,
1898 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) |
1899 (src - 1));
1900
1901 if (freq_out)
1902 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
1903 WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA);
1904
1905 wm8995->fll[id].in = freq_in;
1906 wm8995->fll[id].out = freq_out;
1907 wm8995->fll[id].src = src;
1908
1909 /* Enable any gated AIF clocks */
1910 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
1911 WM8995_AIF1CLK_ENA_MASK, aif1);
1912 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
1913 WM8995_AIF2CLK_ENA_MASK, aif2);
1914
1915 configure_clock(codec);
1916
1917 return 0;
1918}
1919
1920static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
1921 int clk_id, unsigned int freq, int dir)
1922{
1923 struct snd_soc_codec *codec;
1924 struct wm8995_priv *wm8995;
1925
1926 codec = dai->codec;
1927 wm8995 = snd_soc_codec_get_drvdata(codec);
1928
1929 switch (dai->id) {
1930 case 0:
1931 case 1:
1932 break;
1933 default:
1934 /* AIF3 shares clocking with AIF1/2 */
1935 return -EINVAL;
1936 }
1937
1938 switch (clk_id) {
1939 case WM8995_SYSCLK_MCLK1:
1940 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1941 wm8995->mclk[0] = freq;
1942 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1943 dai->id + 1, freq);
1944 break;
1945 case WM8995_SYSCLK_MCLK2:
1946 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1947 wm8995->mclk[1] = freq;
1948 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1949 dai->id + 1, freq);
1950 break;
1951 case WM8995_SYSCLK_FLL1:
1952 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
1953 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
1954 break;
1955 case WM8995_SYSCLK_FLL2:
1956 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
1957 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
1958 break;
1959 case WM8995_SYSCLK_OPCLK:
1960 default:
1961 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
1962 return -EINVAL;
1963 }
1964
1965 configure_clock(codec);
1966
1967 return 0;
1968}
1969
1970static int wm8995_set_bias_level(struct snd_soc_codec *codec,
1971 enum snd_soc_bias_level level)
1972{
1973 struct wm8995_priv *wm8995;
1974 int ret;
1975
1976 wm8995 = snd_soc_codec_get_drvdata(codec);
1977 switch (level) {
1978 case SND_SOC_BIAS_ON:
1979 case SND_SOC_BIAS_PREPARE:
1980 break;
1981 case SND_SOC_BIAS_STANDBY:
1982 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
219d8df8
DP		 1983 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
1984 wm8995->supplies);
1985 if (ret)
1986 return ret;
1987
c42da642 1988 ret = regcache_sync(wm8995->regmap);
6a504a75
DP		 1989 if (ret) {
1990 dev_err(codec->dev,
1991 "Failed to sync cache: %d\n", ret);
1992 return ret;
1993 }
1994
1995 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
1996 WM8995_BG_ENA_MASK, WM8995_BG_ENA);
6a504a75
DP		 1997 }
1998 break;
1999 case SND_SOC_BIAS_OFF:
2000 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
2001 WM8995_BG_ENA_MASK, 0);
219d8df8
DP		 2002 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies),
2003 wm8995->supplies);
6a504a75
DP		 2004 break;
2005 }
2006
2007 codec->dapm.bias_level = level;
2008 return 0;
2009}
2010
2011#ifdef CONFIG_PM
84b315ee 2012static int wm8995_suspend(struct snd_soc_codec *codec)
6a504a75
DP		 2013{
2014 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF);
2015 return 0;
2016}
2017
2018static int wm8995_resume(struct snd_soc_codec *codec)
2019{
2020 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2021 return 0;
2022}
2023#else
2024#define wm8995_suspend NULL
2025#define wm8995_resume NULL
2026#endif
2027
2028static int wm8995_remove(struct snd_soc_codec *codec)
2029{
2030 struct wm8995_priv *wm8995;
5992c587 2031 int i;
6a504a75 2032
6a504a75
DP		 2033 wm8995 = snd_soc_codec_get_drvdata(codec);
2034 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF);
5992c587
AL		 2035
2036 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); ++i)
2037 regulator_unregister_notifier(wm8995->supplies[i].consumer,
2038 &wm8995->disable_nb[i]);
2039
2040 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
6a504a75
DP		 2041 return 0;
2042}
2043
2044static int wm8995_probe(struct snd_soc_codec *codec)
2045{
2046 struct wm8995_priv *wm8995;
219d8df8 2047 int i;
6a504a75
DP		 2048 int ret;
2049
6a504a75 2050 wm8995 = snd_soc_codec_get_drvdata(codec);
219d8df8 2051 wm8995->codec = codec;
6a504a75 2052
6f8d272a 2053 codec->control_data = wm8995->regmap;
c42da642 2054 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
6a504a75
DP		 2055 if (ret < 0) {
2056 dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
2057 return ret;
2058 }
2059
219d8df8
DP		 2060 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++)
2061 wm8995->supplies[i].supply = wm8995_supply_names[i];
2062
2063 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8995->supplies),
2064 wm8995->supplies);
2065 if (ret) {
2066 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2067 return ret;
2068 }
2069
2070 wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0;
2071 wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1;
2072 wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2;
2073 wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3;
2074 wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4;
2075 wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5;
2076 wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6;
2077 wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7;
2078
2079 /* This should really be moved into the regulator core */
2080 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) {
2081 ret = regulator_register_notifier(wm8995->supplies[i].consumer,
2082 &wm8995->disable_nb[i]);
2083 if (ret) {
2084 dev_err(codec->dev,
2085 "Failed to register regulator notifier: %d\n",
2086 ret);
2087 }
2088 }
2089
2090 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
2091 wm8995->supplies);
2092 if (ret) {
2093 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2094 goto err_reg_get;
2095 }
2096
6a504a75
DP		 2097 ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET);
2098 if (ret < 0) {
2099 dev_err(codec->dev, "Failed to read device ID: %d\n", ret);
219d8df8 2100 goto err_reg_enable;
6a504a75
DP		 2101 }
2102
2103 if (ret != 0x8995) {
2104 dev_err(codec->dev, "Invalid device ID: %#x\n", ret);
6fa0c25b 2105 ret = -EINVAL;
219d8df8 2106 goto err_reg_enable;
6a504a75
DP		 2107 }
2108
2109 ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0);
2110 if (ret < 0) {
2111 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
219d8df8 2112 goto err_reg_enable;
6a504a75
DP		 2113 }
2114
2115 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2116
2117 /* Latch volume updates (right only; we always do left then right). */
2118 snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME,
2119 WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU);
2120 snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME,
2121 WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU);
2122 snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME,
2123 WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU);
2124 snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME,
2125 WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU);
2126 snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME,
2127 WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU);
2128 snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME,
2129 WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU);
2130 snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME,
2131 WM8995_DAC1_VU_MASK, WM8995_DAC1_VU);
2132 snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME,
2133 WM8995_DAC2_VU_MASK, WM8995_DAC2_VU);
2134 snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
2135 WM8995_IN1_VU_MASK, WM8995_IN1_VU);
2136
2137 wm8995_update_class_w(codec);
2138
022658be 2139 snd_soc_add_codec_controls(codec, wm8995_snd_controls,
6a504a75
DP		 2140 ARRAY_SIZE(wm8995_snd_controls));
2141 snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets,
2142 ARRAY_SIZE(wm8995_dapm_widgets));
2143 snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon,
2144 ARRAY_SIZE(wm8995_intercon));
2145
2146 return 0;
219d8df8
DP		 2147
2148err_reg_enable:
2149 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
2150err_reg_get:
2151 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
2152 return ret;
6a504a75
DP		 2153}
2154
2155#define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2156 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2157
85e7652d 2158static const struct snd_soc_dai_ops wm8995_aif1_dai_ops = {
6a504a75
DP		 2159 .set_sysclk = wm8995_set_dai_sysclk,
2160 .set_fmt = wm8995_set_dai_fmt,
2161 .hw_params = wm8995_hw_params,
2162 .digital_mute = wm8995_aif_mute,
2163 .set_pll = wm8995_set_fll,
2164 .set_tristate = wm8995_set_tristate,
2165};
2166
85e7652d 2167static const struct snd_soc_dai_ops wm8995_aif2_dai_ops = {
6a504a75
DP		 2168 .set_sysclk = wm8995_set_dai_sysclk,
2169 .set_fmt = wm8995_set_dai_fmt,
2170 .hw_params = wm8995_hw_params,
2171 .digital_mute = wm8995_aif_mute,
2172 .set_pll = wm8995_set_fll,
2173 .set_tristate = wm8995_set_tristate,
2174};
2175
85e7652d 2176static const struct snd_soc_dai_ops wm8995_aif3_dai_ops = {
6a504a75
DP		 2177 .set_tristate = wm8995_set_tristate,
2178};
2179
2180static struct snd_soc_dai_driver wm8995_dai[] = {
2181 {
2182 .name = "wm8995-aif1",
2183 .playback = {
2184 .stream_name = "AIF1 Playback",
2185 .channels_min = 2,
2186 .channels_max = 2,
2187 .rates = SNDRV_PCM_RATE_8000_96000,
2188 .formats = WM8995_FORMATS
2189 },
2190 .capture = {
2191 .stream_name = "AIF1 Capture",
2192 .channels_min = 2,
2193 .channels_max = 2,
2194 .rates = SNDRV_PCM_RATE_8000_48000,
2195 .formats = WM8995_FORMATS
2196 },
2197 .ops = &wm8995_aif1_dai_ops
2198 },
2199 {
2200 .name = "wm8995-aif2",
2201 .playback = {
2202 .stream_name = "AIF2 Playback",
2203 .channels_min = 2,
2204 .channels_max = 2,
2205 .rates = SNDRV_PCM_RATE_8000_96000,
2206 .formats = WM8995_FORMATS
2207 },
2208 .capture = {
2209 .stream_name = "AIF2 Capture",
2210 .channels_min = 2,
2211 .channels_max = 2,
2212 .rates = SNDRV_PCM_RATE_8000_48000,
2213 .formats = WM8995_FORMATS
2214 },
2215 .ops = &wm8995_aif2_dai_ops
2216 },
2217 {
2218 .name = "wm8995-aif3",
2219 .playback = {
2220 .stream_name = "AIF3 Playback",
2221 .channels_min = 2,
2222 .channels_max = 2,
2223 .rates = SNDRV_PCM_RATE_8000_96000,
2224 .formats = WM8995_FORMATS
2225 },
2226 .capture = {
2227 .stream_name = "AIF3 Capture",
2228 .channels_min = 2,
2229 .channels_max = 2,
2230 .rates = SNDRV_PCM_RATE_8000_48000,
2231 .formats = WM8995_FORMATS
2232 },
2233 .ops = &wm8995_aif3_dai_ops
2234 }
2235};
2236
2237static struct snd_soc_codec_driver soc_codec_dev_wm8995 = {
2238 .probe = wm8995_probe,
2239 .remove = wm8995_remove,
2240 .suspend = wm8995_suspend,
2241 .resume = wm8995_resume,
2242 .set_bias_level = wm8995_set_bias_level,
eb3032f8 2243 .idle_bias_off = true,
c42da642
MB		 2244};
2245
2246static struct regmap_config wm8995_regmap = {
2247 .reg_bits = 16,
2248 .val_bits = 16,
2249
2250 .max_register = WM8995_MAX_REGISTER,
2251 .reg_defaults = wm8995_reg_defaults,
2252 .num_reg_defaults = ARRAY_SIZE(wm8995_reg_defaults),
2253 .volatile_reg = wm8995_volatile,
2254 .readable_reg = wm8995_readable,
2255 .cache_type = REGCACHE_RBTREE,
6a504a75
DP		 2256};
2257
2258#if defined(CONFIG_SPI_MASTER)
7a79e94e 2259static int wm8995_spi_probe(struct spi_device *spi)
6a504a75
DP		 2260{
2261 struct wm8995_priv *wm8995;
2262 int ret;
2263
d5ff3c8a 2264 wm8995 = devm_kzalloc(&spi->dev, sizeof(*wm8995), GFP_KERNEL);
6a504a75
DP		 2265 if (!wm8995)
2266 return -ENOMEM;
2267
6a504a75
DP		 2268 spi_set_drvdata(spi, wm8995);
2269
d2d1fe90 2270 wm8995->regmap = devm_regmap_init_spi(spi, &wm8995_regmap);
c42da642
MB		 2271 if (IS_ERR(wm8995->regmap)) {
2272 ret = PTR_ERR(wm8995->regmap);
2273 dev_err(&spi->dev, "Failed to register regmap: %d\n", ret);
d5ff3c8a 2274 return ret;
c42da642
MB		 2275 }
2276
6a504a75
DP		 2277 ret = snd_soc_register_codec(&spi->dev,
2278 &soc_codec_dev_wm8995, wm8995_dai,
2279 ARRAY_SIZE(wm8995_dai));
6a504a75
DP		 2280 return ret;
2281}
2282
7a79e94e 2283static int wm8995_spi_remove(struct spi_device *spi)
6a504a75
DP		 2284{
2285 snd_soc_unregister_codec(&spi->dev);
6a504a75
DP		 2286 return 0;
2287}
2288
2289static struct spi_driver wm8995_spi_driver = {
2290 .driver = {
2291 .name = "wm8995",
2292 .owner = THIS_MODULE,
2293 },
2294 .probe = wm8995_spi_probe,
7a79e94e 2295 .remove = wm8995_spi_remove
6a504a75
DP		 2296};
2297#endif
2298
2299#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
7a79e94e
BP		 2300static int wm8995_i2c_probe(struct i2c_client *i2c,
2301 const struct i2c_device_id *id)
6a504a75
DP		 2302{
2303 struct wm8995_priv *wm8995;
2304 int ret;
2305
d5ff3c8a 2306 wm8995 = devm_kzalloc(&i2c->dev, sizeof(*wm8995), GFP_KERNEL);
6a504a75
DP		 2307 if (!wm8995)
2308 return -ENOMEM;
2309
6a504a75
DP		 2310 i2c_set_clientdata(i2c, wm8995);
2311
d2d1fe90 2312 wm8995->regmap = devm_regmap_init_i2c(i2c, &wm8995_regmap);
c42da642
MB		 2313 if (IS_ERR(wm8995->regmap)) {
2314 ret = PTR_ERR(wm8995->regmap);
2315 dev_err(&i2c->dev, "Failed to register regmap: %d\n", ret);
d5ff3c8a 2316 return ret;
c42da642
MB		 2317 }
2318
6a504a75
DP		 2319 ret = snd_soc_register_codec(&i2c->dev,
2320 &soc_codec_dev_wm8995, wm8995_dai,
2321 ARRAY_SIZE(wm8995_dai));
d2d1fe90 2322 if (ret < 0)
c42da642 2323 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
c42da642 2324
6a504a75
DP		 2325 return ret;
2326}
2327
7a79e94e 2328static int wm8995_i2c_remove(struct i2c_client *client)
6a504a75
DP		 2329{
2330 snd_soc_unregister_codec(&client->dev);
6a504a75
DP		 2331 return 0;
2332}
2333
2334static const struct i2c_device_id wm8995_i2c_id[] = {
2335 {"wm8995", 0},
2336 {}
2337};
2338
2339MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id);
2340
2341static struct i2c_driver wm8995_i2c_driver = {
2342 .driver = {
2343 .name = "wm8995",
2344 .owner = THIS_MODULE,
2345 },
2346 .probe = wm8995_i2c_probe,
7a79e94e 2347 .remove = wm8995_i2c_remove,
6a504a75
DP		 2348 .id_table = wm8995_i2c_id
2349};
2350#endif
2351
2352static int __init wm8995_modinit(void)
2353{
2354 int ret = 0;
2355
2356#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2357 ret = i2c_add_driver(&wm8995_i2c_driver);
2358 if (ret) {
2359 printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n",
2360 ret);
2361 }
2362#endif
2363#if defined(CONFIG_SPI_MASTER)
2364 ret = spi_register_driver(&wm8995_spi_driver);
2365 if (ret) {
2366 printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n",
2367 ret);
2368 }
2369#endif
2370 return ret;
2371}
2372
2373module_init(wm8995_modinit);
2374
2375static void __exit wm8995_exit(void)
2376{
2377#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2378 i2c_del_driver(&wm8995_i2c_driver);
2379#endif
2380#if defined(CONFIG_SPI_MASTER)
2381 spi_unregister_driver(&wm8995_spi_driver);
2382#endif
2383}
2384
2385module_exit(wm8995_exit);
2386
2387MODULE_DESCRIPTION("ASoC WM8995 driver");
2388MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
2389MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)