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Merge branch 'common/pfc' into common/pinctrl
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
bfd37bb5
MB		 49static struct {
50 unsigned int reg;
51 unsigned int mask;
52} wm8994_vu_bits[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63
64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
80};
81
9e6e96a1
MB		 82static int wm8994_drc_base[] = {
83 WM8994_AIF1_DRC1_1,
84 WM8994_AIF1_DRC2_1,
85 WM8994_AIF2_DRC_1,
86};
87
88static int wm8994_retune_mobile_base[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1,
90 WM8994_AIF1_DAC2_EQ_GAINS_1,
91 WM8994_AIF2_EQ_GAINS_1,
92};
93
b00adf76
MB		 94static void wm8958_default_micdet(u16 status, void *data);
95
af6b6fe4 96static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 97 { 32768, true, 1, 4 },
98 { 32768, false, 1, 1 },
604533de
MB		 99 { 44100 * 256, true, 7, 10 },
100 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 101};
102
af6b6fe4
MB		 103static const struct wm8958_micd_rate jackdet_rates[] = {
104 { 32768, true, 0, 1 },
105 { 32768, false, 0, 1 },
e9d9a968
MB		 106 { 44100 * 256, true, 10, 10 },
107 { 44100 * 256, false, 7, 8 },
af6b6fe4
MB		 108};
109
b00adf76
MB		 110static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
111{
112 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
113 int best, i, sysclk, val;
114 bool idle;
af6b6fe4
MB		 115 const struct wm8958_micd_rate *rates;
116 int num_rates;
b00adf76 117
fcdc4de7
MB		 118 if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
119 wm8994->jack_cb != wm8958_default_micdet)
b00adf76
MB		 120 return;
121
122 idle = !wm8994->jack_mic;
123
124 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
125 if (sysclk & WM8994_SYSCLK_SRC)
126 sysclk = wm8994->aifclk[1];
127 else
128 sysclk = wm8994->aifclk[0];
129
cd1707a9
MB		 130 if (wm8994->pdata && wm8994->pdata->micd_rates) {
131 rates = wm8994->pdata->micd_rates;
132 num_rates = wm8994->pdata->num_micd_rates;
133 } else if (wm8994->jackdet) {
af6b6fe4
MB		 134 rates = jackdet_rates;
135 num_rates = ARRAY_SIZE(jackdet_rates);
136 } else {
137 rates = micdet_rates;
138 num_rates = ARRAY_SIZE(micdet_rates);
139 }
140
b00adf76 141 best = 0;
af6b6fe4
MB		 142 for (i = 0; i < num_rates; i++) {
143 if (rates[i].idle != idle)
b00adf76 144 continue;
af6b6fe4
MB		 145 if (abs(rates[i].sysclk - sysclk) <
146 abs(rates[best].sysclk - sysclk))
b00adf76 147 best = i;
af6b6fe4 148 else if (rates[best].idle != idle)
b00adf76
MB		 149 best = i;
150 }
151
af6b6fe4
MB		 152 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
153 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76 154
3a334ada
MB		 155 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
156 rates[best].start, rates[best].rate, sysclk,
157 idle ? "idle" : "active");
158
b00adf76
MB		 159 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
160 WM8958_MICD_BIAS_STARTTIME_MASK |
161 WM8958_MICD_RATE_MASK, val);
162}
163
9e6e96a1
MB		 164static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
165{
b2c812e2 166 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 167 int rate;
168 int reg1 = 0;
169 int offset;
170
171 if (aif)
172 offset = 4;
173 else
174 offset = 0;
175
176 switch (wm8994->sysclk[aif]) {
177 case WM8994_SYSCLK_MCLK1:
178 rate = wm8994->mclk[0];
179 break;
180
181 case WM8994_SYSCLK_MCLK2:
182 reg1 |= 0x8;
183 rate = wm8994->mclk[1];
184 break;
185
186 case WM8994_SYSCLK_FLL1:
187 reg1 |= 0x10;
188 rate = wm8994->fll[0].out;
189 break;
190
191 case WM8994_SYSCLK_FLL2:
192 reg1 |= 0x18;
193 rate = wm8994->fll[1].out;
194 break;
195
196 default:
197 return -EINVAL;
198 }
199
200 if (rate >= 13500000) {
201 rate /= 2;
202 reg1 |= WM8994_AIF1CLK_DIV;
203
204 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
205 aif + 1, rate);
206 }
5e5e2bef 207
9e6e96a1
MB		 208 wm8994->aifclk[aif] = rate;
209
210 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
211 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
212 reg1);
213
214 return 0;
215}
216
217static int configure_clock(struct snd_soc_codec *codec)
218{
b2c812e2 219 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 220 int change, new;
9e6e96a1
MB		 221
222 /* Bring up the AIF clocks first */
223 configure_aif_clock(codec, 0);
224 configure_aif_clock(codec, 1);
225
226 /* Then switch CLK_SYS over to the higher of them; a change
227 * can only happen as a result of a clocking change which can
228 * only be made outside of DAPM so we can safely redo the
229 * clocking.
230 */
231
232 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 233 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
234 wm8958_micd_set_rate(codec);
9e6e96a1 235 return 0;
b00adf76 236 }
9e6e96a1
MB		 237
238 if (wm8994->aifclk[0] < wm8994->aifclk[1])
239 new = WM8994_SYSCLK_SRC;
240 else
241 new = 0;
242
04f45c49
AL		 243 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
244 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 245 if (change)
246 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 247
b00adf76
MB		 248 wm8958_micd_set_rate(codec);
249
9e6e96a1
MB		 250 return 0;
251}
252
253static int check_clk_sys(struct snd_soc_dapm_widget *source,
254 struct snd_soc_dapm_widget *sink)
255{
256 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
257 const char *clk;
258
259 /* Check what we're currently using for CLK_SYS */
260 if (reg & WM8994_SYSCLK_SRC)
261 clk = "AIF2CLK";
262 else
263 clk = "AIF1CLK";
264
265 return strcmp(source->name, clk) == 0;
266}
267
268static const char *sidetone_hpf_text[] = {
269 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
270};
271
272static const struct soc_enum sidetone_hpf =
273 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
274
146fd574
UK		 275static const char *adc_hpf_text[] = {
276 "HiFi", "Voice 1", "Voice 2", "Voice 3"
277};
278
279static const struct soc_enum aif1adc1_hpf =
280 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
281
282static const struct soc_enum aif1adc2_hpf =
283 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
284
285static const struct soc_enum aif2adc_hpf =
286 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
287
9e6e96a1
MB		 288static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
289static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
290static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
291static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
292static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 293static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 294static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 295
296#define WM8994_DRC_SWITCH(xname, reg, shift) \
297{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
298 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
299 .put = wm8994_put_drc_sw, \
300 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
301
302static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
303 struct snd_ctl_elem_value *ucontrol)
304{
305 struct soc_mixer_control *mc =
306 (struct soc_mixer_control *)kcontrol->private_value;
307 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
308 int mask, ret;
309
310 /* Can't enable both ADC and DAC paths simultaneously */
311 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
312 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
313 WM8994_AIF1ADC1R_DRC_ENA_MASK;
314 else
315 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
316
317 ret = snd_soc_read(codec, mc->reg);
318 if (ret < 0)
319 return ret;
320 if (ret & mask)
321 return -EINVAL;
322
323 return snd_soc_put_volsw(kcontrol, ucontrol);
324}
325
9e6e96a1
MB		 326static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
327{
b2c812e2 328 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 329 struct wm8994_pdata *pdata = wm8994->pdata;
330 int base = wm8994_drc_base[drc];
331 int cfg = wm8994->drc_cfg[drc];
332 int save, i;
333
334 /* Save any enables; the configuration should clear them. */
335 save = snd_soc_read(codec, base);
336 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
337 WM8994_AIF1ADC1R_DRC_ENA;
338
339 for (i = 0; i < WM8994_DRC_REGS; i++)
340 snd_soc_update_bits(codec, base + i, 0xffff,
341 pdata->drc_cfgs[cfg].regs[i]);
342
343 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
344 WM8994_AIF1ADC1L_DRC_ENA |
345 WM8994_AIF1ADC1R_DRC_ENA, save);
346}
347
348/* Icky as hell but saves code duplication */
349static int wm8994_get_drc(const char *name)
350{
351 if (strcmp(name, "AIF1DRC1 Mode") == 0)
352 return 0;
353 if (strcmp(name, "AIF1DRC2 Mode") == 0)
354 return 1;
355 if (strcmp(name, "AIF2DRC Mode") == 0)
356 return 2;
357 return -EINVAL;
358}
359
360static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
361 struct snd_ctl_elem_value *ucontrol)
362{
363 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 364 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 365 struct wm8994_pdata *pdata = wm8994->pdata;
366 int drc = wm8994_get_drc(kcontrol->id.name);
367 int value = ucontrol->value.integer.value[0];
368
369 if (drc < 0)
370 return drc;
371
372 if (value >= pdata->num_drc_cfgs)
373 return -EINVAL;
374
375 wm8994->drc_cfg[drc] = value;
376
377 wm8994_set_drc(codec, drc);
378
379 return 0;
380}
381
382static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
383 struct snd_ctl_elem_value *ucontrol)
384{
385 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 386 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 387 int drc = wm8994_get_drc(kcontrol->id.name);
388
389 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
390
391 return 0;
392}
393
394static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
395{
b2c812e2 396 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 397 struct wm8994_pdata *pdata = wm8994->pdata;
398 int base = wm8994_retune_mobile_base[block];
399 int iface, best, best_val, save, i, cfg;
400
401 if (!pdata || !wm8994->num_retune_mobile_texts)
402 return;
403
404 switch (block) {
405 case 0:
406 case 1:
407 iface = 0;
408 break;
409 case 2:
410 iface = 1;
411 break;
412 default:
413 return;
414 }
415
416 /* Find the version of the currently selected configuration
417 * with the nearest sample rate. */
418 cfg = wm8994->retune_mobile_cfg[block];
419 best = 0;
420 best_val = INT_MAX;
421 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
422 if (strcmp(pdata->retune_mobile_cfgs[i].name,
423 wm8994->retune_mobile_texts[cfg]) == 0 &&
424 abs(pdata->retune_mobile_cfgs[i].rate
425 - wm8994->dac_rates[iface]) < best_val) {
426 best = i;
427 best_val = abs(pdata->retune_mobile_cfgs[i].rate
428 - wm8994->dac_rates[iface]);
429 }
430 }
431
432 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
433 block,
434 pdata->retune_mobile_cfgs[best].name,
435 pdata->retune_mobile_cfgs[best].rate,
436 wm8994->dac_rates[iface]);
437
438 /* The EQ will be disabled while reconfiguring it, remember the
c1a4ecd9 439 * current configuration.
9e6e96a1
MB		 440 */
441 save = snd_soc_read(codec, base);
442 save &= WM8994_AIF1DAC1_EQ_ENA;
443
444 for (i = 0; i < WM8994_EQ_REGS; i++)
445 snd_soc_update_bits(codec, base + i, 0xffff,
446 pdata->retune_mobile_cfgs[best].regs[i]);
447
448 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
449}
450
451/* Icky as hell but saves code duplication */
452static int wm8994_get_retune_mobile_block(const char *name)
453{
454 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
455 return 0;
456 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
457 return 1;
458 if (strcmp(name, "AIF2 EQ Mode") == 0)
459 return 2;
460 return -EINVAL;
461}
462
463static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
464 struct snd_ctl_elem_value *ucontrol)
465{
466 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 468 struct wm8994_pdata *pdata = wm8994->pdata;
469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483}
484
485static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
492 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
493
494 return 0;
495}
496
96b101ef 497static const char *aif_chan_src_text[] = {
f554885f
MB		 498 "Left", "Right"
499};
500
96b101ef
MB		 501static const struct soc_enum aif1adcl_src =
502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
503
504static const struct soc_enum aif1adcr_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
506
507static const struct soc_enum aif2adcl_src =
508 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
509
510static const struct soc_enum aif2adcr_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
512
f554885f 513static const struct soc_enum aif1dacl_src =
96b101ef 514 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 515
516static const struct soc_enum aif1dacr_src =
96b101ef 517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 518
519static const struct soc_enum aif2dacl_src =
96b101ef 520 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 521
522static const struct soc_enum aif2dacr_src =
96b101ef 523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 524
154b26aa
MB		 525static const char *osr_text[] = {
526 "Low Power", "High Performance",
527};
528
529static const struct soc_enum dac_osr =
530 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
531
532static const struct soc_enum adc_osr =
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
534
9e6e96a1
MB		 535static const struct snd_kcontrol_new wm8994_snd_controls[] = {
536SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME,
538 1, 119, 0, digital_tlv),
539SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
540 WM8994_AIF1_ADC2_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
543 WM8994_AIF2_ADC_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545
96b101ef
MB		 546SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
547SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 548SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
549SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 550
f554885f
MB		 551SOC_ENUM("AIF1DACL Source", aif1dacl_src),
552SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 553SOC_ENUM("AIF2DACL Source", aif2dacl_src),
554SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 555
9e6e96a1
MB		 556SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
557 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
558SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
559 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
560SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
561 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562
563SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
564SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
565
566SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
567SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
568SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
569
570WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
571WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
572WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
573
574WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
575WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
576WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
577
578WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
579WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
580WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
581
582SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
583 5, 12, 0, st_tlv),
584SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
585 0, 12, 0, st_tlv),
586SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
587 5, 12, 0, st_tlv),
588SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
589 0, 12, 0, st_tlv),
590SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
591SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
592
146fd574
UK		 593SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
594SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
595
596SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
597SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
598
599SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
600SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
601
154b26aa
MB		 602SOC_ENUM("ADC OSR", adc_osr),
603SOC_ENUM("DAC OSR", dac_osr),
604
9e6e96a1
MB		 605SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
606 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
607SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
608 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
609
610SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
611 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
612SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
613 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
614
615SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
616 6, 1, 1, wm_hubs_spkmix_tlv),
617SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
618 2, 1, 1, wm_hubs_spkmix_tlv),
619
620SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
621 6, 1, 1, wm_hubs_spkmix_tlv),
622SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
623 2, 1, 1, wm_hubs_spkmix_tlv),
624
625SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
626 10, 15, 0, wm8994_3d_tlv),
458350b3 627SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 628 8, 1, 0),
629SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
631SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
632 8, 1, 0),
458350b3 633SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 634 10, 15, 0, wm8994_3d_tlv),
458350b3 635SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 636 8, 1, 0),
637};
638
639static const struct snd_kcontrol_new wm8994_eq_controls[] = {
640SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
649 eq_tlv),
650
651SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
652 eq_tlv),
653SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
654 eq_tlv),
655SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
660 eq_tlv),
661
662SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
663 eq_tlv),
664SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
665 eq_tlv),
666SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
667 eq_tlv),
668SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
669 eq_tlv),
670SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
671 eq_tlv),
672};
673
1ddc07d0
MB		 674static const char *wm8958_ng_text[] = {
675 "30ms", "125ms", "250ms", "500ms",
676};
677
678static const struct soc_enum wm8958_aif1dac1_ng_hold =
679 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
680 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
681
682static const struct soc_enum wm8958_aif1dac2_ng_hold =
683 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
684 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
685
686static const struct soc_enum wm8958_aif2dac_ng_hold =
687 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
688 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
689
c4431df0
MB		 690static const struct snd_kcontrol_new wm8958_snd_controls[] = {
691SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 692
693SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
694 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
695SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
696SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
697 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
698 7, 1, ng_tlv),
699
700SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
701 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
702SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
703SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
704 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
705 7, 1, ng_tlv),
706
707SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
708 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
709SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
710SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
711 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
712 7, 1, ng_tlv),
c4431df0
MB		 713};
714
81204c84
MB		 715static const struct snd_kcontrol_new wm1811_snd_controls[] = {
716SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
717 mixin_boost_tlv),
718SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
719 mixin_boost_tlv),
720};
721
af6b6fe4
MB		 722/* We run all mode setting through a function to enforce audio mode */
723static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
724{
725 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
726
28e33269
MB		 727 if (!wm8994->jackdet || !wm8994->jack_cb)
728 return;
729
af6b6fe4
MB		 730 if (wm8994->active_refcount)
731 mode = WM1811_JACKDET_MODE_AUDIO;
732
4752a887 733 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 734 return;
735
4752a887 736 wm8994->jackdet_mode = mode;
1defde2a 737
4752a887
MB		 738 /* Always use audio mode to detect while the system is active */
739 if (mode != WM1811_JACKDET_MODE_NONE)
740 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 741
4752a887
MB		 742 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
743 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 744}
745
746static void active_reference(struct snd_soc_codec *codec)
747{
748 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
749
750 mutex_lock(&wm8994->accdet_lock);
751
752 wm8994->active_refcount++;
753
754 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
755 wm8994->active_refcount);
756
1defde2a
MB		 757 /* If we're using jack detection go into audio mode */
758 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 759
760 mutex_unlock(&wm8994->accdet_lock);
761}
762
763static void active_dereference(struct snd_soc_codec *codec)
764{
765 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
766 u16 mode;
767
768 mutex_lock(&wm8994->accdet_lock);
769
770 wm8994->active_refcount--;
771
772 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
773 wm8994->active_refcount);
774
775 if (wm8994->active_refcount == 0) {
776 /* Go into appropriate detection only mode */
1defde2a
MB		 777 if (wm8994->jack_mic || wm8994->mic_detecting)
778 mode = WM1811_JACKDET_MODE_MIC;
779 else
780 mode = WM1811_JACKDET_MODE_JACK;
781
782 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 783 }
784
785 mutex_unlock(&wm8994->accdet_lock);
786}
787
9e6e96a1
MB		 788static int clk_sys_event(struct snd_soc_dapm_widget *w,
789 struct snd_kcontrol *kcontrol, int event)
790{
791 struct snd_soc_codec *codec = w->codec;
792
793 switch (event) {
794 case SND_SOC_DAPM_PRE_PMU:
795 return configure_clock(codec);
796
797 case SND_SOC_DAPM_POST_PMD:
798 configure_clock(codec);
799 break;
800 }
801
802 return 0;
803}
804
4b7ed83a
MB		 805static void vmid_reference(struct snd_soc_codec *codec)
806{
807 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
808
db966f8a
MB		 809 pm_runtime_get_sync(codec->dev);
810
4b7ed83a
MB		 811 wm8994->vmid_refcount++;
812
813 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
814 wm8994->vmid_refcount);
815
816 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 817 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 818 WM8994_LINEOUT1_DISCH |
22f8d055 819 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 820
f7085641
MB		 821 wm_hubs_vmid_ena(codec);
822
22f8d055
MB		 823 switch (wm8994->vmid_mode) {
824 default:
cbd71f30 825 WARN_ON(NULL == "Invalid VMID mode");
22f8d055
MB		 826 case WM8994_VMID_NORMAL:
827 /* Startup bias, VMID ramp & buffer */
828 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
829 WM8994_BIAS_SRC |
830 WM8994_VMID_DISCH |
831 WM8994_STARTUP_BIAS_ENA |
832 WM8994_VMID_BUF_ENA |
833 WM8994_VMID_RAMP_MASK,
834 WM8994_BIAS_SRC |
835 WM8994_STARTUP_BIAS_ENA |
836 WM8994_VMID_BUF_ENA |
837 (0x3 << WM8994_VMID_RAMP_SHIFT));
838
839 /* Main bias enable, VMID=2x40k */
840 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
841 WM8994_BIAS_ENA |
842 WM8994_VMID_SEL_MASK,
843 WM8994_BIAS_ENA | 0x2);
844
845 msleep(50);
846
847 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
848 WM8994_VMID_RAMP_MASK |
849 WM8994_BIAS_SRC,
850 0);
851 break;
cc6d5a8c 852
22f8d055
MB		 853 case WM8994_VMID_FORCE:
854 /* Startup bias, slow VMID ramp & buffer */
855 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
856 WM8994_BIAS_SRC |
857 WM8994_VMID_DISCH |
858 WM8994_STARTUP_BIAS_ENA |
859 WM8994_VMID_BUF_ENA |
860 WM8994_VMID_RAMP_MASK,
861 WM8994_BIAS_SRC |
862 WM8994_STARTUP_BIAS_ENA |
863 WM8994_VMID_BUF_ENA |
864 (0x2 << WM8994_VMID_RAMP_SHIFT));
865
866 /* Main bias enable, VMID=2x40k */
867 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
868 WM8994_BIAS_ENA |
869 WM8994_VMID_SEL_MASK,
870 WM8994_BIAS_ENA | 0x2);
871
872 msleep(400);
873
874 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
875 WM8994_VMID_RAMP_MASK |
876 WM8994_BIAS_SRC,
877 0);
878 break;
879 }
4b7ed83a
MB		 880 }
881}
882
883static void vmid_dereference(struct snd_soc_codec *codec)
884{
885 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
886
887 wm8994->vmid_refcount--;
888
889 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
890 wm8994->vmid_refcount);
891
892 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 893 if (wm8994->hubs.lineout1_se)
894 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
895 WM8994_LINEOUT1N_ENA |
896 WM8994_LINEOUT1P_ENA,
897 WM8994_LINEOUT1N_ENA |
898 WM8994_LINEOUT1P_ENA);
899
900 if (wm8994->hubs.lineout2_se)
901 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
902 WM8994_LINEOUT2N_ENA |
903 WM8994_LINEOUT2P_ENA,
904 WM8994_LINEOUT2N_ENA |
905 WM8994_LINEOUT2P_ENA);
906
907 /* Start discharging VMID */
4b7ed83a
MB		 908 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
909 WM8994_BIAS_SRC |
22f8d055 910 WM8994_VMID_DISCH,
4b7ed83a 911 WM8994_BIAS_SRC |
22f8d055 912 WM8994_VMID_DISCH);
4b7ed83a 913
22f8d055
MB		 914 switch (wm8994->vmid_mode) {
915 case WM8994_VMID_FORCE:
916 msleep(350);
917 break;
918 default:
919 break;
920 }
4b7ed83a 921
22f8d055
MB		 922 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
923 WM8994_VROI, WM8994_VROI);
e85b26ce 924
22f8d055 925 /* Active discharge */
4b7ed83a
MB		 926 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
927 WM8994_LINEOUT1_DISCH |
928 WM8994_LINEOUT2_DISCH,
929 WM8994_LINEOUT1_DISCH |
930 WM8994_LINEOUT2_DISCH);
931
22f8d055
MB		 932 msleep(150);
933
934 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
935 WM8994_LINEOUT1N_ENA |
936 WM8994_LINEOUT1P_ENA |
937 WM8994_LINEOUT2N_ENA |
938 WM8994_LINEOUT2P_ENA, 0);
939
940 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
941 WM8994_VROI, 0);
4b7ed83a
MB		 942
943 /* Switch off startup biases */
944 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
945 WM8994_BIAS_SRC |
946 WM8994_STARTUP_BIAS_ENA |
947 WM8994_VMID_BUF_ENA |
948 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 949
950 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
951 WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
952
953 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
954 WM8994_VMID_RAMP_MASK, 0);
4b7ed83a 955 }
db966f8a
MB		 956
957 pm_runtime_put(codec->dev);
4b7ed83a
MB		 958}
959
960static int vmid_event(struct snd_soc_dapm_widget *w,
961 struct snd_kcontrol *kcontrol, int event)
962{
963 struct snd_soc_codec *codec = w->codec;
964
965 switch (event) {
966 case SND_SOC_DAPM_PRE_PMU:
967 vmid_reference(codec);
968 break;
969
970 case SND_SOC_DAPM_POST_PMD:
971 vmid_dereference(codec);
972 break;
973 }
974
975 return 0;
976}
977
c340304d 978static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
9e6e96a1 979{
9e6e96a1
MB		 980 int source = 0; /* GCC flow analysis can't track enable */
981 int reg, reg_r;
982
c340304d 983 /* We also need the same AIF source for L/R and only one path */
9e6e96a1
MB		 984 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
985 switch (reg) {
986 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 987 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 988 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
989 break;
990 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 991 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 992 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
993 break;
994 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 995 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 996 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
997 break;
998 default:
ee839a21 999 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
c340304d 1000 return false;
9e6e96a1
MB		 1001 }
1002
1003 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1004 if (reg_r != reg) {
ee839a21 1005 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
c340304d 1006 return false;
9e6e96a1
MB		 1007 }
1008
c340304d
MB		 1009 /* Set the source up */
1010 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1011 WM8994_CP_DYN_SRC_SEL_MASK, source);
c1a4ecd9 1012
c340304d 1013 return true;
9e6e96a1
MB		 1014}
1015
1a38336b
MB		 1016static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1017 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1018{
1019 struct snd_soc_codec *codec = w->codec;
1a38336b
MB		 1020 struct wm8994 *control = codec->control_data;
1021 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
bfd37bb5 1022 int i;
1a38336b
MB		 1023 int dac;
1024 int adc;
1025 int val;
1026
1027 switch (control->type) {
1028 case WM8994:
1029 case WM8958:
1030 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1031 break;
1032 default:
1033 break;
1034 }
173efa09
DP		 1035
1036 switch (event) {
1037 case SND_SOC_DAPM_PRE_PMU:
1a38336b
MB		 1038 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1039 if ((val & WM8994_AIF1ADCL_SRC) &&
1040 (val & WM8994_AIF1ADCR_SRC))
1041 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1042 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1043 !(val & WM8994_AIF1ADCR_SRC))
1044 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1045 else
1046 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1047 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1048
1049 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1050 if ((val & WM8994_AIF1DACL_SRC) &&
1051 (val & WM8994_AIF1DACR_SRC))
1052 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1053 else if (!(val & WM8994_AIF1DACL_SRC) &&
1054 !(val & WM8994_AIF1DACR_SRC))
1055 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1056 else
1057 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1058 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1059
1060 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1061 mask, adc);
1062 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1063 mask, dac);
1064 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1065 WM8994_AIF1DSPCLK_ENA |
1066 WM8994_SYSDSPCLK_ENA,
1067 WM8994_AIF1DSPCLK_ENA |
1068 WM8994_SYSDSPCLK_ENA);
1069 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1070 WM8994_AIF1ADC1R_ENA |
1071 WM8994_AIF1ADC1L_ENA |
1072 WM8994_AIF1ADC2R_ENA |
1073 WM8994_AIF1ADC2L_ENA);
1074 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1075 WM8994_AIF1DAC1R_ENA |
1076 WM8994_AIF1DAC1L_ENA |
1077 WM8994_AIF1DAC2R_ENA |
1078 WM8994_AIF1DAC2L_ENA);
173efa09 1079 break;
173efa09 1080
bfd37bb5
MB		 1081 case SND_SOC_DAPM_POST_PMU:
1082 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1083 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1084 snd_soc_read(codec,
1085 wm8994_vu_bits[i].reg));
1086 break;
1087
1a38336b
MB		 1088 case SND_SOC_DAPM_PRE_PMD:
1089 case SND_SOC_DAPM_POST_PMD:
1090 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1091 mask, 0);
1092 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1093 mask, 0);
1094
1095 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1096 if (val & WM8994_AIF2DSPCLK_ENA)
1097 val = WM8994_SYSDSPCLK_ENA;
1098 else
1099 val = 0;
1100 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1101 WM8994_SYSDSPCLK_ENA |
1102 WM8994_AIF1DSPCLK_ENA, val);
1103 break;
1104 }
c6b7b570 1105
173efa09
DP		 1106 return 0;
1107}
1108
1a38336b
MB		 1109static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1110 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1111{
1112 struct snd_soc_codec *codec = w->codec;
bfd37bb5 1113 int i;
1a38336b
MB		 1114 int dac;
1115 int adc;
1116 int val;
173efa09
DP		 1117
1118 switch (event) {
1a38336b
MB		 1119 case SND_SOC_DAPM_PRE_PMU:
1120 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1121 if ((val & WM8994_AIF2ADCL_SRC) &&
1122 (val & WM8994_AIF2ADCR_SRC))
1123 adc = WM8994_AIF2ADCR_ENA;
1124 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1125 !(val & WM8994_AIF2ADCR_SRC))
1126 adc = WM8994_AIF2ADCL_ENA;
1127 else
1128 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1129
1130
1131 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1132 if ((val & WM8994_AIF2DACL_SRC) &&
1133 (val & WM8994_AIF2DACR_SRC))
1134 dac = WM8994_AIF2DACR_ENA;
1135 else if (!(val & WM8994_AIF2DACL_SRC) &&
1136 !(val & WM8994_AIF2DACR_SRC))
1137 dac = WM8994_AIF2DACL_ENA;
1138 else
1139 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1140
1141 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1142 WM8994_AIF2ADCL_ENA |
1143 WM8994_AIF2ADCR_ENA, adc);
1144 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1145 WM8994_AIF2DACL_ENA |
1146 WM8994_AIF2DACR_ENA, dac);
1147 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1148 WM8994_AIF2DSPCLK_ENA |
1149 WM8994_SYSDSPCLK_ENA,
1150 WM8994_AIF2DSPCLK_ENA |
1151 WM8994_SYSDSPCLK_ENA);
1152 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1153 WM8994_AIF2ADCL_ENA |
1154 WM8994_AIF2ADCR_ENA,
1155 WM8994_AIF2ADCL_ENA |
1156 WM8994_AIF2ADCR_ENA);
1157 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1158 WM8994_AIF2DACL_ENA |
1159 WM8994_AIF2DACR_ENA,
1160 WM8994_AIF2DACL_ENA |
1161 WM8994_AIF2DACR_ENA);
1162 break;
1163
bfd37bb5
MB		 1164 case SND_SOC_DAPM_POST_PMU:
1165 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1166 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1167 snd_soc_read(codec,
1168 wm8994_vu_bits[i].reg));
1169 break;
1170
1a38336b 1171 case SND_SOC_DAPM_PRE_PMD:
173efa09 1172 case SND_SOC_DAPM_POST_PMD:
1a38336b
MB		 1173 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1174 WM8994_AIF2DACL_ENA |
1175 WM8994_AIF2DACR_ENA, 0);
c7f5f238 1176 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1a38336b
MB		 1177 WM8994_AIF2ADCL_ENA |
1178 WM8994_AIF2ADCR_ENA, 0);
1179
1180 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1181 if (val & WM8994_AIF1DSPCLK_ENA)
1182 val = WM8994_SYSDSPCLK_ENA;
1183 else
1184 val = 0;
1185 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1186 WM8994_SYSDSPCLK_ENA |
1187 WM8994_AIF2DSPCLK_ENA, val);
173efa09
DP		 1188 break;
1189 }
1190
1191 return 0;
1192}
1193
1a38336b
MB		 1194static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1195 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1196{
1197 struct snd_soc_codec *codec = w->codec;
1198 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1199
1200 switch (event) {
1201 case SND_SOC_DAPM_PRE_PMU:
1202 wm8994->aif1clk_enable = 1;
1203 break;
a3cff81a
DP		 1204 case SND_SOC_DAPM_POST_PMD:
1205 wm8994->aif1clk_disable = 1;
1206 break;
173efa09
DP		 1207 }
1208
1209 return 0;
1210}
1211
1a38336b
MB		 1212static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1213 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1214{
1215 struct snd_soc_codec *codec = w->codec;
1216 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1217
1218 switch (event) {
1219 case SND_SOC_DAPM_PRE_PMU:
1220 wm8994->aif2clk_enable = 1;
1221 break;
a3cff81a
DP		 1222 case SND_SOC_DAPM_POST_PMD:
1223 wm8994->aif2clk_disable = 1;
1224 break;
173efa09
DP		 1225 }
1226
1227 return 0;
1228}
1229
1a38336b
MB		 1230static int late_enable_ev(struct snd_soc_dapm_widget *w,
1231 struct snd_kcontrol *kcontrol, int event)
1232{
1233 struct snd_soc_codec *codec = w->codec;
1234 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1235
1236 switch (event) {
1237 case SND_SOC_DAPM_PRE_PMU:
1238 if (wm8994->aif1clk_enable) {
c8fdc1b5 1239 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1240 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1241 WM8994_AIF1CLK_ENA_MASK,
1242 WM8994_AIF1CLK_ENA);
c8fdc1b5 1243 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1244 wm8994->aif1clk_enable = 0;
1245 }
1246 if (wm8994->aif2clk_enable) {
c8fdc1b5 1247 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1248 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1249 WM8994_AIF2CLK_ENA_MASK,
1250 WM8994_AIF2CLK_ENA);
c8fdc1b5 1251 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1252 wm8994->aif2clk_enable = 0;
1253 }
1254 break;
1255 }
1256
1257 /* We may also have postponed startup of DSP, handle that. */
1258 wm8958_aif_ev(w, kcontrol, event);
1259
1260 return 0;
1261}
1262
1263static int late_disable_ev(struct snd_soc_dapm_widget *w,
1264 struct snd_kcontrol *kcontrol, int event)
1265{
1266 struct snd_soc_codec *codec = w->codec;
1267 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1268
1269 switch (event) {
1270 case SND_SOC_DAPM_POST_PMD:
1271 if (wm8994->aif1clk_disable) {
c8fdc1b5 1272 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1273 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1274 WM8994_AIF1CLK_ENA_MASK, 0);
c8fdc1b5 1275 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1276 wm8994->aif1clk_disable = 0;
1277 }
1278 if (wm8994->aif2clk_disable) {
c8fdc1b5 1279 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1280 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1281 WM8994_AIF2CLK_ENA_MASK, 0);
c8fdc1b5 1282 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1283 wm8994->aif2clk_disable = 0;
1284 }
1285 break;
1286 }
1287
1288 return 0;
1289}
1290
04d28681
DP		 1291static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1292 struct snd_kcontrol *kcontrol, int event)
1293{
1294 late_enable_ev(w, kcontrol, event);
1295 return 0;
1296}
1297
b462c6e6
DP		 1298static int micbias_ev(struct snd_soc_dapm_widget *w,
1299 struct snd_kcontrol *kcontrol, int event)
1300{
1301 late_enable_ev(w, kcontrol, event);
1302 return 0;
1303}
1304
c52fd021
DP		 1305static int dac_ev(struct snd_soc_dapm_widget *w,
1306 struct snd_kcontrol *kcontrol, int event)
1307{
1308 struct snd_soc_codec *codec = w->codec;
1309 unsigned int mask = 1 << w->shift;
1310
1311 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1312 mask, mask);
1313 return 0;
1314}
1315
9e6e96a1
MB		 1316static const char *adc_mux_text[] = {
1317 "ADC",
1318 "DMIC",
1319};
1320
1321static const struct soc_enum adc_enum =
1322 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1323
1324static const struct snd_kcontrol_new adcl_mux =
1325 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1326
1327static const struct snd_kcontrol_new adcr_mux =
1328 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1329
1330static const struct snd_kcontrol_new left_speaker_mixer[] = {
1331SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1332SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1333SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1334SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1335SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1336};
1337
1338static const struct snd_kcontrol_new right_speaker_mixer[] = {
1339SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1340SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1341SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1342SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1343SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1344};
1345
1346/* Debugging; dump chip status after DAPM transitions */
1347static int post_ev(struct snd_soc_dapm_widget *w,
1348 struct snd_kcontrol *kcontrol, int event)
1349{
1350 struct snd_soc_codec *codec = w->codec;
1351 dev_dbg(codec->dev, "SRC status: %x\n",
1352 snd_soc_read(codec,
1353 WM8994_RATE_STATUS));
1354 return 0;
1355}
1356
1357static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1358SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1359 1, 1, 0),
1360SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1361 0, 1, 0),
1362};
1363
1364static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1365SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1366 1, 1, 0),
1367SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1368 0, 1, 0),
1369};
1370
a3257ba8
MB		 1371static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1372SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1373 1, 1, 0),
1374SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1375 0, 1, 0),
1376};
1377
1378static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1379SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1380 1, 1, 0),
1381SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1382 0, 1, 0),
1383};
1384
9e6e96a1
MB		 1385static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1386SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1387 5, 1, 0),
1388SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1389 4, 1, 0),
1390SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1391 2, 1, 0),
1392SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1393 1, 1, 0),
1394SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1395 0, 1, 0),
1396};
1397
1398static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1399SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1400 5, 1, 0),
1401SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1402 4, 1, 0),
1403SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1404 2, 1, 0),
1405SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1406 1, 1, 0),
1407SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1408 0, 1, 0),
1409};
1410
1411#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1412{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1413 .info = snd_soc_info_volsw, \
1414 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1415 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1416
1417static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1418 struct snd_ctl_elem_value *ucontrol)
1419{
9d03545d
JN		 1420 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1421 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1422 struct snd_soc_codec *codec = w->codec;
1423 int ret;
1424
1425 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1426
c340304d 1427 wm_hubs_update_class_w(codec);
9e6e96a1
MB		 1428
1429 return ret;
1430}
1431
1432static const struct snd_kcontrol_new dac1l_mix[] = {
1433WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1434 5, 1, 0),
1435WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1436 4, 1, 0),
1437WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1438 2, 1, 0),
1439WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1440 1, 1, 0),
1441WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1442 0, 1, 0),
1443};
1444
1445static const struct snd_kcontrol_new dac1r_mix[] = {
1446WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1447 5, 1, 0),
1448WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1449 4, 1, 0),
1450WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1451 2, 1, 0),
1452WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1453 1, 1, 0),
1454WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1455 0, 1, 0),
1456};
1457
1458static const char *sidetone_text[] = {
1459 "ADC/DMIC1", "DMIC2",
1460};
1461
1462static const struct soc_enum sidetone1_enum =
1463 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1464
1465static const struct snd_kcontrol_new sidetone1_mux =
1466 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1467
1468static const struct soc_enum sidetone2_enum =
1469 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1470
1471static const struct snd_kcontrol_new sidetone2_mux =
1472 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1473
1474static const char *aif1dac_text[] = {
1475 "AIF1DACDAT", "AIF3DACDAT",
1476};
1477
1478static const struct soc_enum aif1dac_enum =
1479 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1480
1481static const struct snd_kcontrol_new aif1dac_mux =
1482 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1483
1484static const char *aif2dac_text[] = {
1485 "AIF2DACDAT", "AIF3DACDAT",
1486};
1487
1488static const struct soc_enum aif2dac_enum =
1489 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1490
1491static const struct snd_kcontrol_new aif2dac_mux =
1492 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1493
1494static const char *aif2adc_text[] = {
1495 "AIF2ADCDAT", "AIF3DACDAT",
1496};
1497
1498static const struct soc_enum aif2adc_enum =
1499 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1500
1501static const struct snd_kcontrol_new aif2adc_mux =
1502 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1503
1504static const char *aif3adc_text[] = {
c4431df0 1505 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1506};
1507
c4431df0 1508static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1509 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1510
c4431df0
MB		 1511static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1512 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1513
1514static const struct soc_enum wm8958_aif3adc_enum =
1515 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1516
1517static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1518 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1519
1520static const char *mono_pcm_out_text[] = {
c1a4ecd9 1521 "None", "AIF2ADCL", "AIF2ADCR",
c4431df0
MB		 1522};
1523
1524static const struct soc_enum mono_pcm_out_enum =
1525 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1526
1527static const struct snd_kcontrol_new mono_pcm_out_mux =
1528 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1529
1530static const char *aif2dac_src_text[] = {
1531 "AIF2", "AIF3",
1532};
1533
1534/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1535static const struct soc_enum aif2dacl_src_enum =
1536 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1537
1538static const struct snd_kcontrol_new aif2dacl_src_mux =
1539 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1540
1541static const struct soc_enum aif2dacr_src_enum =
1542 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1543
1544static const struct snd_kcontrol_new aif2dacr_src_mux =
1545 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1546
173efa09 1547static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1a38336b 1548SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
173efa09 1549 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1a38336b 1550SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
173efa09
DP		 1551 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1552
1553SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1554 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1555SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1556 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1557SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1558 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1559SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1560 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1561SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1562 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1563
1564SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1565 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1566 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1567SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1568 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1569 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1570SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
b70a51ba 1571 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1572SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
b70a51ba 1573 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1574
1575SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1576};
1577
1578static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1a38336b 1579SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
bfd37bb5
MB		 1580 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1581 SND_SOC_DAPM_PRE_PMD),
1a38336b 1582SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
bfd37bb5
MB		 1583 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1584 SND_SOC_DAPM_PRE_PMD),
b70a51ba
MB		 1585SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1586SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1587 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1588SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1589 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
c340304d
MB		 1590SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1591SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
173efa09
DP		 1592};
1593
c52fd021
DP		 1594static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1595SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1596 dac_ev, SND_SOC_DAPM_PRE_PMU),
1597SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1598 dac_ev, SND_SOC_DAPM_PRE_PMU),
1599SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1600 dac_ev, SND_SOC_DAPM_PRE_PMU),
1601SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1602 dac_ev, SND_SOC_DAPM_PRE_PMU),
1603};
1604
1605static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1606SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1607SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1608SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1609SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1610};
1611
04d28681 1612static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1613SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1614 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1615SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1616 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1617};
1618
1619static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1620SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1621SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1622};
1623
9e6e96a1
MB		 1624static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1625SND_SOC_DAPM_INPUT("DMIC1DAT"),
1626SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1627SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1628
b462c6e6
DP		 1629SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1630 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1631SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1632 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1633
9e6e96a1
MB		 1634SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1635 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1636
1a38336b
MB		 1637SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1638SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1639SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
9e6e96a1 1640
7f94de48 1641SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1a38336b 1642 0, SND_SOC_NOPM, 9, 0),
7f94de48 1643SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1a38336b 1644 0, SND_SOC_NOPM, 8, 0),
d6addcc9 1645SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1a38336b 1646 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
b2822a8c 1647 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1648SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1a38336b 1649 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
b2822a8c 1650 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1651
7f94de48 1652SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1a38336b 1653 0, SND_SOC_NOPM, 11, 0),
7f94de48 1654SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1a38336b 1655 0, SND_SOC_NOPM, 10, 0),
d6addcc9 1656SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1a38336b 1657 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
b2822a8c 1658 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1659SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1a38336b 1660 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
b2822a8c 1661 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1662
1663SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1664 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1665SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1666 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1667
a3257ba8
MB		 1668SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1669 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1670SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1671 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1672
9e6e96a1
MB		 1673SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1674 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1675SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1676 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1677
1678SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1679SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1680
1681SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1682 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1683SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1684 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1685
1686SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1a38336b 1687 SND_SOC_NOPM, 13, 0),
9e6e96a1 1688SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1a38336b 1689 SND_SOC_NOPM, 12, 0),
d6addcc9 1690SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1a38336b 1691 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
d6addcc9
MB		 1692 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1693SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1a38336b 1694 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
d6addcc9 1695 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1696
5567d8c6
MB		 1697SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1698SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1699SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1700SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1701
1702SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1703SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1704SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1705
5567d8c6
MB		 1706SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1707SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1708
1709SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1710
1711SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1712SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1713SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1714SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1715
1716/* Power is done with the muxes since the ADC power also controls the
1717 * downsampling chain, the chip will automatically manage the analogue
1718 * specific portions.
1719 */
1720SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1721SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1722
9e6e96a1
MB		 1723SND_SOC_DAPM_POST("Debug log", post_ev),
1724};
1725
c4431df0
MB		 1726static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1727SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1728};
9e6e96a1 1729
c4431df0 1730static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
8c5b842b 1731SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
c4431df0
MB		 1732SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1733SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1734SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1735SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1736};
1737
1738static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1739 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1740 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1741
1742 { "DSP1CLK", NULL, "CLK_SYS" },
1743 { "DSP2CLK", NULL, "CLK_SYS" },
1744 { "DSPINTCLK", NULL, "CLK_SYS" },
1745
1746 { "AIF1ADC1L", NULL, "AIF1CLK" },
1747 { "AIF1ADC1L", NULL, "DSP1CLK" },
1748 { "AIF1ADC1R", NULL, "AIF1CLK" },
1749 { "AIF1ADC1R", NULL, "DSP1CLK" },
1750 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1751
1752 { "AIF1DAC1L", NULL, "AIF1CLK" },
1753 { "AIF1DAC1L", NULL, "DSP1CLK" },
1754 { "AIF1DAC1R", NULL, "AIF1CLK" },
1755 { "AIF1DAC1R", NULL, "DSP1CLK" },
1756 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1757
1758 { "AIF1ADC2L", NULL, "AIF1CLK" },
1759 { "AIF1ADC2L", NULL, "DSP1CLK" },
1760 { "AIF1ADC2R", NULL, "AIF1CLK" },
1761 { "AIF1ADC2R", NULL, "DSP1CLK" },
1762 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1763
1764 { "AIF1DAC2L", NULL, "AIF1CLK" },
1765 { "AIF1DAC2L", NULL, "DSP1CLK" },
1766 { "AIF1DAC2R", NULL, "AIF1CLK" },
1767 { "AIF1DAC2R", NULL, "DSP1CLK" },
1768 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1769
1770 { "AIF2ADCL", NULL, "AIF2CLK" },
1771 { "AIF2ADCL", NULL, "DSP2CLK" },
1772 { "AIF2ADCR", NULL, "AIF2CLK" },
1773 { "AIF2ADCR", NULL, "DSP2CLK" },
1774 { "AIF2ADCR", NULL, "DSPINTCLK" },
1775
1776 { "AIF2DACL", NULL, "AIF2CLK" },
1777 { "AIF2DACL", NULL, "DSP2CLK" },
1778 { "AIF2DACR", NULL, "AIF2CLK" },
1779 { "AIF2DACR", NULL, "DSP2CLK" },
1780 { "AIF2DACR", NULL, "DSPINTCLK" },
1781
1782 { "DMIC1L", NULL, "DMIC1DAT" },
1783 { "DMIC1L", NULL, "CLK_SYS" },
1784 { "DMIC1R", NULL, "DMIC1DAT" },
1785 { "DMIC1R", NULL, "CLK_SYS" },
1786 { "DMIC2L", NULL, "DMIC2DAT" },
1787 { "DMIC2L", NULL, "CLK_SYS" },
1788 { "DMIC2R", NULL, "DMIC2DAT" },
1789 { "DMIC2R", NULL, "CLK_SYS" },
1790
1791 { "ADCL", NULL, "AIF1CLK" },
1792 { "ADCL", NULL, "DSP1CLK" },
1793 { "ADCL", NULL, "DSPINTCLK" },
1794
1795 { "ADCR", NULL, "AIF1CLK" },
1796 { "ADCR", NULL, "DSP1CLK" },
1797 { "ADCR", NULL, "DSPINTCLK" },
1798
1799 { "ADCL Mux", "ADC", "ADCL" },
1800 { "ADCL Mux", "DMIC", "DMIC1L" },
1801 { "ADCR Mux", "ADC", "ADCR" },
1802 { "ADCR Mux", "DMIC", "DMIC1R" },
1803
1804 { "DAC1L", NULL, "AIF1CLK" },
1805 { "DAC1L", NULL, "DSP1CLK" },
1806 { "DAC1L", NULL, "DSPINTCLK" },
1807
1808 { "DAC1R", NULL, "AIF1CLK" },
1809 { "DAC1R", NULL, "DSP1CLK" },
1810 { "DAC1R", NULL, "DSPINTCLK" },
1811
1812 { "DAC2L", NULL, "AIF2CLK" },
1813 { "DAC2L", NULL, "DSP2CLK" },
1814 { "DAC2L", NULL, "DSPINTCLK" },
1815
1816 { "DAC2R", NULL, "AIF2DACR" },
1817 { "DAC2R", NULL, "AIF2CLK" },
1818 { "DAC2R", NULL, "DSP2CLK" },
1819 { "DAC2R", NULL, "DSPINTCLK" },
1820
1821 { "TOCLK", NULL, "CLK_SYS" },
1822
5567d8c6
MB		 1823 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1824 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1825 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1826
1827 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1828 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1829 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1830
9e6e96a1
MB		 1831 /* AIF1 outputs */
1832 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1833 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1834 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1835
1836 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1837 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1838 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1839
a3257ba8
MB		 1840 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1841 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1842 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1843
1844 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1845 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1846 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1847
9e6e96a1
MB		 1848 /* Pin level routing for AIF3 */
1849 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1850 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1851 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1852 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1853
9e6e96a1
MB		 1854 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1855 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1856 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1857 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1858 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1859 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1860 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1861
1862 /* DAC1 inputs */
9e6e96a1
MB		 1863 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1864 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1865 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1866 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1867 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1868
9e6e96a1
MB		 1869 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1870 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1871 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1872 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1873 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1874
1875 /* DAC2/AIF2 outputs */
1876 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1877 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1878 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1879 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1880 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1881 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1882
1883 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1884 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1885 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1886 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1887 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1888 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1889
7f94de48
MB		 1890 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1891 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1892 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1893 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1894
9e6e96a1
MB		 1895 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1896
1897 /* AIF3 output */
1898 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1899 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1900 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1901 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1902 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1903 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1904 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1905 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1906
1907 /* Sidetone */
1908 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1909 { "Left Sidetone", "DMIC2", "DMIC2L" },
1910 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1911 { "Right Sidetone", "DMIC2", "DMIC2R" },
1912
1913 /* Output stages */
1914 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1915 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1916
1917 { "SPKL", "DAC1 Switch", "DAC1L" },
1918 { "SPKL", "DAC2 Switch", "DAC2L" },
1919
1920 { "SPKR", "DAC1 Switch", "DAC1R" },
1921 { "SPKR", "DAC2 Switch", "DAC2R" },
1922
1923 { "Left Headphone Mux", "DAC", "DAC1L" },
1924 { "Right Headphone Mux", "DAC", "DAC1R" },
1925};
1926
173efa09
DP		 1927static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1928 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1929 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1930 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1931 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1932 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1933 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1934 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1935 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1936};
1937
1938static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1939 { "DAC1L", NULL, "DAC1L Mixer" },
1940 { "DAC1R", NULL, "DAC1R Mixer" },
1941 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1942 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1943};
1944
6ed8f148
MB		 1945static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1946 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1947 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1948 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1949 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1950 { "MICBIAS1", NULL, "CLK_SYS" },
1951 { "MICBIAS1", NULL, "MICBIAS Supply" },
1952 { "MICBIAS2", NULL, "CLK_SYS" },
1953 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1954};
1955
c4431df0
MB		 1956static const struct snd_soc_dapm_route wm8994_intercon[] = {
1957 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1958 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1959 { "MICBIAS1", NULL, "VMID" },
1960 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1961};
1962
1963static const struct snd_soc_dapm_route wm8958_intercon[] = {
1964 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1965 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1966
1967 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1968 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1969 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1970 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1971
8c5b842b
MB		 1972 { "AIF3DACDAT", NULL, "AIF3" },
1973 { "AIF3ADCDAT", NULL, "AIF3" },
1974
c4431df0
MB		 1975 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1976 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1977
1978 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1979};
1980
9e6e96a1
MB		 1981/* The size in bits of the FLL divide multiplied by 10
1982 * to allow rounding later */
1983#define FIXED_FLL_SIZE ((1 << 16) * 10)
1984
1985struct fll_div {
1986 u16 outdiv;
1987 u16 n;
1988 u16 k;
1989 u16 clk_ref_div;
1990 u16 fll_fratio;
1991};
1992
1993static int wm8994_get_fll_config(struct fll_div *fll,
1994 int freq_in, int freq_out)
1995{
1996 u64 Kpart;
1997 unsigned int K, Ndiv, Nmod;
1998
1999 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2000
2001 /* Scale the input frequency down to <= 13.5MHz */
2002 fll->clk_ref_div = 0;
2003 while (freq_in > 13500000) {
2004 fll->clk_ref_div++;
2005 freq_in /= 2;
2006
2007 if (fll->clk_ref_div > 3)
2008 return -EINVAL;
2009 }
2010 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2011
2012 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2013 fll->outdiv = 3;
2014 while (freq_out * (fll->outdiv + 1) < 90000000) {
2015 fll->outdiv++;
2016 if (fll->outdiv > 63)
2017 return -EINVAL;
2018 }
2019 freq_out *= fll->outdiv + 1;
2020 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2021
2022 if (freq_in > 1000000) {
2023 fll->fll_fratio = 0;
7d48a6ac
MB		 2024 } else if (freq_in > 256000) {
2025 fll->fll_fratio = 1;
2026 freq_in *= 2;
2027 } else if (freq_in > 128000) {
2028 fll->fll_fratio = 2;
2029 freq_in *= 4;
2030 } else if (freq_in > 64000) {
9e6e96a1
MB		 2031 fll->fll_fratio = 3;
2032 freq_in *= 8;
7d48a6ac
MB		 2033 } else {
2034 fll->fll_fratio = 4;
2035 freq_in *= 16;
9e6e96a1
MB		 2036 }
2037 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2038
2039 /* Now, calculate N.K */
2040 Ndiv = freq_out / freq_in;
2041
2042 fll->n = Ndiv;
2043 Nmod = freq_out % freq_in;
2044 pr_debug("Nmod=%d\n", Nmod);
2045
2046 /* Calculate fractional part - scale up so we can round. */
2047 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2048
2049 do_div(Kpart, freq_in);
2050
2051 K = Kpart & 0xFFFFFFFF;
2052
2053 if ((K % 10) >= 5)
2054 K += 5;
2055
2056 /* Move down to proper range now rounding is done */
2057 fll->k = K / 10;
2058
2059 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2060
2061 return 0;
2062}
2063
f0fba2ad 2064static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 2065 unsigned int freq_in, unsigned int freq_out)
2066{
b2c812e2 2067 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2068 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2069 int reg_offset, ret;
2070 struct fll_div fll;
e413ba88 2071 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 2072 unsigned long timeout;
4b7ed83a 2073 bool was_enabled;
9e6e96a1 2074
9e6e96a1
MB		 2075 switch (id) {
2076 case WM8994_FLL1:
2077 reg_offset = 0;
2078 id = 0;
e413ba88 2079 aif_src = 0x10;
9e6e96a1
MB		 2080 break;
2081 case WM8994_FLL2:
2082 reg_offset = 0x20;
2083 id = 1;
e413ba88 2084 aif_src = 0x18;
9e6e96a1
MB		 2085 break;
2086 default:
2087 return -EINVAL;
2088 }
2089
4b7ed83a
MB		 2090 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2091 was_enabled = reg & WM8994_FLL1_ENA;
2092
136ff2a2 2093 switch (src) {
7add84aa
MB		 2094 case 0:
2095 /* Allow no source specification when stopping */
2096 if (freq_out)
2097 return -EINVAL;
4514e899 2098 src = wm8994->fll[id].src;
7add84aa 2099 break;
136ff2a2
MB		 2100 case WM8994_FLL_SRC_MCLK1:
2101 case WM8994_FLL_SRC_MCLK2:
2102 case WM8994_FLL_SRC_LRCLK:
2103 case WM8994_FLL_SRC_BCLK:
2104 break;
2105 default:
2106 return -EINVAL;
2107 }
2108
9e6e96a1
MB		 2109 /* Are we changing anything? */
2110 if (wm8994->fll[id].src == src &&
2111 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2112 return 0;
2113
2114 /* If we're stopping the FLL redo the old config - no
2115 * registers will actually be written but we avoid GCC flow
2116 * analysis bugs spewing warnings.
2117 */
2118 if (freq_out)
2119 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2120 else
2121 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2122 wm8994->fll[id].out);
2123 if (ret < 0)
2124 return ret;
2125
e413ba88
MB		 2126 /* Make sure that we're not providing SYSCLK right now */
2127 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2128 if (clk1 & WM8994_SYSCLK_SRC)
2129 aif_reg = WM8994_AIF2_CLOCKING_1;
2130 else
2131 aif_reg = WM8994_AIF1_CLOCKING_1;
2132 reg = snd_soc_read(codec, aif_reg);
2133
2134 if ((reg & WM8994_AIF1CLK_ENA) &&
2135 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2136 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2137 id + 1);
2138 return -EBUSY;
2139 }
9e6e96a1
MB		 2140
2141 /* We always need to disable the FLL while reconfiguring */
2142 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2143 WM8994_FLL1_ENA, 0);
2144
20dc24a9 2145 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
e05854dd 2146 freq_in == freq_out && freq_out) {
20dc24a9
MB		 2147 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2148 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2149 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2150 goto out;
2151 }
2152
9e6e96a1
MB		 2153 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2154 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2155 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2156 WM8994_FLL1_OUTDIV_MASK |
2157 WM8994_FLL1_FRATIO_MASK, reg);
2158
b16db745
MB		 2159 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2160 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 2161
2162 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2163 WM8994_FLL1_N_MASK,
2164 fll.n << WM8994_FLL1_N_SHIFT);
2165
2166 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
20dc24a9 2167 WM8958_FLL1_BYP |
136ff2a2
MB		 2168 WM8994_FLL1_REFCLK_DIV_MASK |
2169 WM8994_FLL1_REFCLK_SRC_MASK,
2170 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2171 (src - 1));
9e6e96a1 2172
f0f5039c
MB		 2173 /* Clear any pending completion from a previous failure */
2174 try_wait_for_completion(&wm8994->fll_locked[id]);
2175
9e6e96a1
MB		 2176 /* Enable (with fractional mode if required) */
2177 if (freq_out) {
4b7ed83a
MB		 2178 /* Enable VMID if we need it */
2179 if (!was_enabled) {
af6b6fe4
MB		 2180 active_reference(codec);
2181
4b7ed83a
MB		 2182 switch (control->type) {
2183 case WM8994:
2184 vmid_reference(codec);
2185 break;
2186 case WM8958:
2187 if (wm8994->revision < 1)
2188 vmid_reference(codec);
2189 break;
2190 default:
2191 break;
2192 }
2193 }
2194
9e6e96a1
MB		 2195 if (fll.k)
2196 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2197 else
2198 reg = WM8994_FLL1_ENA;
2199 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2200 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2201 reg);
8e9ddf81 2202
c7ebf932
MB		 2203 if (wm8994->fll_locked_irq) {
2204 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2205 msecs_to_jiffies(10));
2206 if (timeout == 0)
2207 dev_warn(codec->dev,
2208 "Timed out waiting for FLL lock\n");
2209 } else {
2210 msleep(5);
2211 }
4b7ed83a
MB		 2212 } else {
2213 if (was_enabled) {
2214 switch (control->type) {
2215 case WM8994:
2216 vmid_dereference(codec);
2217 break;
2218 case WM8958:
2219 if (wm8994->revision < 1)
2220 vmid_dereference(codec);
2221 break;
2222 default:
2223 break;
2224 }
af6b6fe4
MB		 2225
2226 active_dereference(codec);
4b7ed83a 2227 }
9e6e96a1
MB		 2228 }
2229
20dc24a9 2230out:
9e6e96a1
MB		 2231 wm8994->fll[id].in = freq_in;
2232 wm8994->fll[id].out = freq_out;
136ff2a2 2233 wm8994->fll[id].src = src;
9e6e96a1 2234
9e6e96a1
MB		 2235 configure_clock(codec);
2236
2237 return 0;
2238}
2239
c7ebf932
MB		 2240static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2241{
2242 struct completion *completion = data;
2243
2244 complete(completion);
2245
2246 return IRQ_HANDLED;
2247}
f0fba2ad 2248
66b47fdb
MB		 2249static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2250
f0fba2ad
LG		 2251static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2252 unsigned int freq_in, unsigned int freq_out)
2253{
2254 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2255}
2256
9e6e96a1
MB		 2257static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2258 int clk_id, unsigned int freq, int dir)
2259{
2260 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2261 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2262 int i;
9e6e96a1
MB		 2263
2264 switch (dai->id) {
2265 case 1:
2266 case 2:
2267 break;
2268
2269 default:
2270 /* AIF3 shares clocking with AIF1/2 */
2271 return -EINVAL;
2272 }
2273
2274 switch (clk_id) {
2275 case WM8994_SYSCLK_MCLK1:
2276 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2277 wm8994->mclk[0] = freq;
2278 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2279 dai->id, freq);
2280 break;
2281
2282 case WM8994_SYSCLK_MCLK2:
2283 /* TODO: Set GPIO AF */
2284 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2285 wm8994->mclk[1] = freq;
2286 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2287 dai->id, freq);
2288 break;
2289
2290 case WM8994_SYSCLK_FLL1:
2291 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2292 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2293 break;
2294
2295 case WM8994_SYSCLK_FLL2:
2296 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2297 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2298 break;
2299
66b47fdb
MB		 2300 case WM8994_SYSCLK_OPCLK:
2301 /* Special case - a division (times 10) is given and
c1a4ecd9 2302 * no effect on main clocking.
66b47fdb
MB		 2303 */
2304 if (freq) {
2305 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2306 if (opclk_divs[i] == freq)
2307 break;
2308 if (i == ARRAY_SIZE(opclk_divs))
2309 return -EINVAL;
2310 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2311 WM8994_OPCLK_DIV_MASK, i);
2312 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2313 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2314 } else {
2315 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2316 WM8994_OPCLK_ENA, 0);
2317 }
2318
9e6e96a1
MB		 2319 default:
2320 return -EINVAL;
2321 }
2322
2323 configure_clock(codec);
2324
2325 return 0;
2326}
2327
2328static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2329 enum snd_soc_bias_level level)
2330{
b6b05691 2331 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2332 struct wm8994 *control = wm8994->wm8994;
b6b05691 2333
5f2f3890
MB		 2334 wm_hubs_set_bias_level(codec, level);
2335
9e6e96a1
MB		 2336 switch (level) {
2337 case SND_SOC_BIAS_ON:
2338 break;
2339
2340 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2341 /* MICBIAS into regulating mode */
2342 switch (control->type) {
2343 case WM8958:
2344 case WM1811:
2345 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2346 WM8958_MICB1_MODE, 0);
2347 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2348 WM8958_MICB2_MODE, 0);
2349 break;
2350 default:
2351 break;
2352 }
af6b6fe4
MB		 2353
2354 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2355 active_reference(codec);
9e6e96a1
MB		 2356 break;
2357
2358 case SND_SOC_BIAS_STANDBY:
ce6120cc 2359 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2360 switch (control->type) {
8bc3c2c2
MB		 2361 case WM8958:
2362 if (wm8994->revision == 0) {
2363 /* Optimise performance for rev A */
8bc3c2c2
MB		 2364 snd_soc_update_bits(codec,
2365 WM8958_CHARGE_PUMP_2,
2366 WM8958_CP_DISCH,
2367 WM8958_CP_DISCH);
2368 }
2369 break;
81204c84 2370
462835e4 2371 default:
81204c84 2372 break;
b6b05691 2373 }
9e6e96a1
MB		 2374
2375 /* Discharge LINEOUT1 & 2 */
2376 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2377 WM8994_LINEOUT1_DISCH |
2378 WM8994_LINEOUT2_DISCH,
2379 WM8994_LINEOUT1_DISCH |
2380 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2381 }
2382
af6b6fe4
MB		 2383 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2384 active_dereference(codec);
2385
500fa30e
MB		 2386 /* MICBIAS into bypass mode on newer devices */
2387 switch (control->type) {
2388 case WM8958:
2389 case WM1811:
2390 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2391 WM8958_MICB1_MODE,
2392 WM8958_MICB1_MODE);
2393 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2394 WM8958_MICB2_MODE,
2395 WM8958_MICB2_MODE);
2396 break;
2397 default:
2398 break;
2399 }
9e6e96a1
MB		 2400 break;
2401
2402 case SND_SOC_BIAS_OFF:
4105ab84 2403 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2404 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2405 break;
2406 }
5f2f3890 2407
ce6120cc 2408 codec->dapm.bias_level = level;
af6b6fe4 2409
22f8d055
MB		 2410 return 0;
2411}
2412
2413int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2414{
2415 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2416
2417 switch (mode) {
2418 case WM8994_VMID_NORMAL:
2419 if (wm8994->hubs.lineout1_se) {
2420 snd_soc_dapm_disable_pin(&codec->dapm,
2421 "LINEOUT1N Driver");
2422 snd_soc_dapm_disable_pin(&codec->dapm,
2423 "LINEOUT1P Driver");
2424 }
2425 if (wm8994->hubs.lineout2_se) {
2426 snd_soc_dapm_disable_pin(&codec->dapm,
2427 "LINEOUT2N Driver");
2428 snd_soc_dapm_disable_pin(&codec->dapm,
2429 "LINEOUT2P Driver");
2430 }
2431
2432 /* Do the sync with the old mode to allow it to clean up */
2433 snd_soc_dapm_sync(&codec->dapm);
2434 wm8994->vmid_mode = mode;
2435 break;
2436
2437 case WM8994_VMID_FORCE:
2438 if (wm8994->hubs.lineout1_se) {
2439 snd_soc_dapm_force_enable_pin(&codec->dapm,
2440 "LINEOUT1N Driver");
2441 snd_soc_dapm_force_enable_pin(&codec->dapm,
2442 "LINEOUT1P Driver");
2443 }
2444 if (wm8994->hubs.lineout2_se) {
2445 snd_soc_dapm_force_enable_pin(&codec->dapm,
2446 "LINEOUT2N Driver");
2447 snd_soc_dapm_force_enable_pin(&codec->dapm,
2448 "LINEOUT2P Driver");
2449 }
2450
2451 wm8994->vmid_mode = mode;
2452 snd_soc_dapm_sync(&codec->dapm);
2453 break;
2454
2455 default:
2456 return -EINVAL;
2457 }
2458
9e6e96a1
MB		 2459 return 0;
2460}
2461
2462static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2463{
2464 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2465 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2466 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2467 int ms_reg;
2468 int aif1_reg;
2469 int ms = 0;
2470 int aif1 = 0;
2471
2472 switch (dai->id) {
2473 case 1:
2474 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2475 aif1_reg = WM8994_AIF1_CONTROL_1;
2476 break;
2477 case 2:
2478 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2479 aif1_reg = WM8994_AIF2_CONTROL_1;
2480 break;
2481 default:
2482 return -EINVAL;
2483 }
2484
2485 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2486 case SND_SOC_DAIFMT_CBS_CFS:
2487 break;
2488 case SND_SOC_DAIFMT_CBM_CFM:
2489 ms = WM8994_AIF1_MSTR;
2490 break;
2491 default:
2492 return -EINVAL;
2493 }
2494
2495 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2496 case SND_SOC_DAIFMT_DSP_B:
2497 aif1 |= WM8994_AIF1_LRCLK_INV;
2498 case SND_SOC_DAIFMT_DSP_A:
2499 aif1 |= 0x18;
2500 break;
2501 case SND_SOC_DAIFMT_I2S:
2502 aif1 |= 0x10;
2503 break;
2504 case SND_SOC_DAIFMT_RIGHT_J:
2505 break;
2506 case SND_SOC_DAIFMT_LEFT_J:
2507 aif1 |= 0x8;
2508 break;
2509 default:
2510 return -EINVAL;
2511 }
2512
2513 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2514 case SND_SOC_DAIFMT_DSP_A:
2515 case SND_SOC_DAIFMT_DSP_B:
2516 /* frame inversion not valid for DSP modes */
2517 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2518 case SND_SOC_DAIFMT_NB_NF:
2519 break;
2520 case SND_SOC_DAIFMT_IB_NF:
2521 aif1 |= WM8994_AIF1_BCLK_INV;
2522 break;
2523 default:
2524 return -EINVAL;
2525 }
2526 break;
2527
2528 case SND_SOC_DAIFMT_I2S:
2529 case SND_SOC_DAIFMT_RIGHT_J:
2530 case SND_SOC_DAIFMT_LEFT_J:
2531 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2532 case SND_SOC_DAIFMT_NB_NF:
2533 break;
2534 case SND_SOC_DAIFMT_IB_IF:
2535 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2536 break;
2537 case SND_SOC_DAIFMT_IB_NF:
2538 aif1 |= WM8994_AIF1_BCLK_INV;
2539 break;
2540 case SND_SOC_DAIFMT_NB_IF:
2541 aif1 |= WM8994_AIF1_LRCLK_INV;
2542 break;
2543 default:
2544 return -EINVAL;
2545 }
2546 break;
2547 default:
2548 return -EINVAL;
2549 }
2550
c4431df0
MB		 2551 /* The AIF2 format configuration needs to be mirrored to AIF3
2552 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2553 switch (control->type) {
2554 case WM1811:
2555 case WM8958:
2556 if (dai->id == 2)
2557 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2558 WM8994_AIF1_LRCLK_INV |
2559 WM8958_AIF3_FMT_MASK, aif1);
2560 break;
2561
2562 default:
2563 break;
2564 }
c4431df0 2565
9e6e96a1
MB		 2566 snd_soc_update_bits(codec, aif1_reg,
2567 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2568 WM8994_AIF1_FMT_MASK,
2569 aif1);
2570 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2571 ms);
2572
2573 return 0;
2574}
2575
2576static struct {
2577 int val, rate;
2578} srs[] = {
2579 { 0, 8000 },
2580 { 1, 11025 },
2581 { 2, 12000 },
2582 { 3, 16000 },
2583 { 4, 22050 },
2584 { 5, 24000 },
2585 { 6, 32000 },
2586 { 7, 44100 },
2587 { 8, 48000 },
2588 { 9, 88200 },
2589 { 10, 96000 },
2590};
2591
2592static int fs_ratios[] = {
2593 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2594};
2595
2596static int bclk_divs[] = {
2597 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2598 640, 880, 960, 1280, 1760, 1920
2599};
2600
2601static int wm8994_hw_params(struct snd_pcm_substream *substream,
2602 struct snd_pcm_hw_params *params,
2603 struct snd_soc_dai *dai)
2604{
2605 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2606 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2607 int aif1_reg;
b1e43d93 2608 int aif2_reg;
9e6e96a1
MB		 2609 int bclk_reg;
2610 int lrclk_reg;
2611 int rate_reg;
2612 int aif1 = 0;
b1e43d93 2613 int aif2 = 0;
9e6e96a1
MB		 2614 int bclk = 0;
2615 int lrclk = 0;
2616 int rate_val = 0;
2617 int id = dai->id - 1;
2618
2619 int i, cur_val, best_val, bclk_rate, best;
2620
2621 switch (dai->id) {
2622 case 1:
2623 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2624 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2625 bclk_reg = WM8994_AIF1_BCLK;
2626 rate_reg = WM8994_AIF1_RATE;
2627 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2628 wm8994->lrclk_shared[0]) {
9e6e96a1 2629 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2630 } else {
9e6e96a1 2631 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2632 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2633 }
9e6e96a1
MB		 2634 break;
2635 case 2:
2636 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2637 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2638 bclk_reg = WM8994_AIF2_BCLK;
2639 rate_reg = WM8994_AIF2_RATE;
2640 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2641 wm8994->lrclk_shared[1]) {
9e6e96a1 2642 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2643 } else {
9e6e96a1 2644 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2645 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2646 }
9e6e96a1
MB		 2647 break;
2648 default:
2649 return -EINVAL;
2650 }
2651
2652 bclk_rate = params_rate(params) * 2;
2653 switch (params_format(params)) {
2654 case SNDRV_PCM_FORMAT_S16_LE:
2655 bclk_rate *= 16;
2656 break;
2657 case SNDRV_PCM_FORMAT_S20_3LE:
2658 bclk_rate *= 20;
2659 aif1 |= 0x20;
2660 break;
2661 case SNDRV_PCM_FORMAT_S24_LE:
2662 bclk_rate *= 24;
2663 aif1 |= 0x40;
2664 break;
2665 case SNDRV_PCM_FORMAT_S32_LE:
2666 bclk_rate *= 32;
2667 aif1 |= 0x60;
2668 break;
2669 default:
2670 return -EINVAL;
2671 }
2672
2673 /* Try to find an appropriate sample rate; look for an exact match. */
2674 for (i = 0; i < ARRAY_SIZE(srs); i++)
2675 if (srs[i].rate == params_rate(params))
2676 break;
2677 if (i == ARRAY_SIZE(srs))
2678 return -EINVAL;
2679 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2680
2681 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2682 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2683 dai->id, wm8994->aifclk[id], bclk_rate);
2684
b1e43d93
MB		 2685 if (params_channels(params) == 1 &&
2686 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2687 aif2 |= WM8994_AIF1_MONO;
2688
9e6e96a1
MB		 2689 if (wm8994->aifclk[id] == 0) {
2690 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2691 return -EINVAL;
2692 }
2693
2694 /* AIFCLK/fs ratio; look for a close match in either direction */
2695 best = 0;
2696 best_val = abs((fs_ratios[0] * params_rate(params))
2697 - wm8994->aifclk[id]);
2698 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2699 cur_val = abs((fs_ratios[i] * params_rate(params))
2700 - wm8994->aifclk[id]);
2701 if (cur_val >= best_val)
2702 continue;
2703 best = i;
2704 best_val = cur_val;
2705 }
2706 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2707 dai->id, fs_ratios[best]);
2708 rate_val |= best;
2709
2710 /* We may not get quite the right frequency if using
2711 * approximate clocks so look for the closest match that is
2712 * higher than the target (we need to ensure that there enough
2713 * BCLKs to clock out the samples).
2714 */
2715 best = 0;
2716 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2717 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2718 if (cur_val < 0) /* BCLK table is sorted */
2719 break;
2720 best = i;
2721 }
07cd8ada 2722 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2723 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2724 bclk_divs[best], bclk_rate);
2725 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2726
2727 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2728 if (!lrclk) {
2729 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2730 bclk_rate);
2731 return -EINVAL;
2732 }
9e6e96a1
MB		 2733 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2734 lrclk, bclk_rate / lrclk);
2735
2736 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2737 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2738 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2739 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2740 lrclk);
2741 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2742 WM8994_AIF1CLK_RATE_MASK, rate_val);
2743
2744 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2745 switch (dai->id) {
2746 case 1:
2747 wm8994->dac_rates[0] = params_rate(params);
2748 wm8994_set_retune_mobile(codec, 0);
2749 wm8994_set_retune_mobile(codec, 1);
2750 break;
2751 case 2:
2752 wm8994->dac_rates[1] = params_rate(params);
2753 wm8994_set_retune_mobile(codec, 2);
2754 break;
2755 }
2756 }
2757
2758 return 0;
2759}
2760
c4431df0
MB		 2761static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2762 struct snd_pcm_hw_params *params,
2763 struct snd_soc_dai *dai)
2764{
2765 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2766 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2767 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2768 int aif1_reg;
2769 int aif1 = 0;
2770
2771 switch (dai->id) {
2772 case 3:
2773 switch (control->type) {
81204c84 2774 case WM1811:
c4431df0
MB		 2775 case WM8958:
2776 aif1_reg = WM8958_AIF3_CONTROL_1;
2777 break;
2778 default:
2779 return 0;
2780 }
2781 default:
2782 return 0;
2783 }
2784
2785 switch (params_format(params)) {
2786 case SNDRV_PCM_FORMAT_S16_LE:
2787 break;
2788 case SNDRV_PCM_FORMAT_S20_3LE:
2789 aif1 |= 0x20;
2790 break;
2791 case SNDRV_PCM_FORMAT_S24_LE:
2792 aif1 |= 0x40;
2793 break;
2794 case SNDRV_PCM_FORMAT_S32_LE:
2795 aif1 |= 0x60;
2796 break;
2797 default:
2798 return -EINVAL;
2799 }
2800
2801 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2802}
2803
9e6e96a1
MB		 2804static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2805{
2806 struct snd_soc_codec *codec = codec_dai->codec;
2807 int mute_reg;
2808 int reg;
2809
2810 switch (codec_dai->id) {
2811 case 1:
2812 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2813 break;
2814 case 2:
2815 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2816 break;
2817 default:
2818 return -EINVAL;
2819 }
2820
2821 if (mute)
2822 reg = WM8994_AIF1DAC1_MUTE;
2823 else
2824 reg = 0;
2825
2826 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2827
2828 return 0;
2829}
2830
778a76e2
MB		 2831static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2832{
2833 struct snd_soc_codec *codec = codec_dai->codec;
2834 int reg, val, mask;
2835
2836 switch (codec_dai->id) {
2837 case 1:
2838 reg = WM8994_AIF1_MASTER_SLAVE;
2839 mask = WM8994_AIF1_TRI;
2840 break;
2841 case 2:
2842 reg = WM8994_AIF2_MASTER_SLAVE;
2843 mask = WM8994_AIF2_TRI;
2844 break;
778a76e2
MB		 2845 default:
2846 return -EINVAL;
2847 }
2848
2849 if (tristate)
2850 val = mask;
2851 else
2852 val = 0;
2853
78b3fb46 2854 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2855}
2856
d09f3ecf
MB		 2857static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2858{
2859 struct snd_soc_codec *codec = dai->codec;
2860
2861 /* Disable the pulls on the AIF if we're using it to save power. */
2862 snd_soc_update_bits(codec, WM8994_GPIO_3,
2863 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2864 snd_soc_update_bits(codec, WM8994_GPIO_4,
2865 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2866 snd_soc_update_bits(codec, WM8994_GPIO_5,
2867 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2868
2869 return 0;
2870}
2871
9e6e96a1
MB		 2872#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2873
2874#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2875 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2876
85e7652d 2877static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2878 .set_sysclk = wm8994_set_dai_sysclk,
2879 .set_fmt = wm8994_set_dai_fmt,
2880 .hw_params = wm8994_hw_params,
2881 .digital_mute = wm8994_aif_mute,
2882 .set_pll = wm8994_set_fll,
778a76e2 2883 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2884};
2885
85e7652d 2886static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2887 .set_sysclk = wm8994_set_dai_sysclk,
2888 .set_fmt = wm8994_set_dai_fmt,
2889 .hw_params = wm8994_hw_params,
2890 .digital_mute = wm8994_aif_mute,
2891 .set_pll = wm8994_set_fll,
778a76e2
MB		 2892 .set_tristate = wm8994_set_tristate,
2893};
2894
85e7652d 2895static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2896 .hw_params = wm8994_aif3_hw_params,
9e6e96a1
MB		 2897};
2898
f0fba2ad 2899static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2900 {
f0fba2ad 2901 .name = "wm8994-aif1",
8c7f78b3 2902 .id = 1,
9e6e96a1
MB		 2903 .playback = {
2904 .stream_name = "AIF1 Playback",
b1e43d93 2905 .channels_min = 1,
9e6e96a1
MB		 2906 .channels_max = 2,
2907 .rates = WM8994_RATES,
2908 .formats = WM8994_FORMATS,
99b0292d 2909 .sig_bits = 24,
9e6e96a1
MB		 2910 },
2911 .capture = {
2912 .stream_name = "AIF1 Capture",
b1e43d93 2913 .channels_min = 1,
9e6e96a1
MB		 2914 .channels_max = 2,
2915 .rates = WM8994_RATES,
2916 .formats = WM8994_FORMATS,
99b0292d 2917 .sig_bits = 24,
9e6e96a1
MB		 2918 },
2919 .ops = &wm8994_aif1_dai_ops,
2920 },
2921 {
f0fba2ad 2922 .name = "wm8994-aif2",
8c7f78b3 2923 .id = 2,
9e6e96a1
MB		 2924 .playback = {
2925 .stream_name = "AIF2 Playback",
b1e43d93 2926 .channels_min = 1,
9e6e96a1
MB		 2927 .channels_max = 2,
2928 .rates = WM8994_RATES,
2929 .formats = WM8994_FORMATS,
99b0292d 2930 .sig_bits = 24,
9e6e96a1
MB		 2931 },
2932 .capture = {
2933 .stream_name = "AIF2 Capture",
b1e43d93 2934 .channels_min = 1,
9e6e96a1
MB		 2935 .channels_max = 2,
2936 .rates = WM8994_RATES,
2937 .formats = WM8994_FORMATS,
99b0292d 2938 .sig_bits = 24,
9e6e96a1 2939 },
d09f3ecf 2940 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2941 .ops = &wm8994_aif2_dai_ops,
2942 },
2943 {
f0fba2ad 2944 .name = "wm8994-aif3",
8c7f78b3 2945 .id = 3,
9e6e96a1
MB		 2946 .playback = {
2947 .stream_name = "AIF3 Playback",
b1e43d93 2948 .channels_min = 1,
9e6e96a1
MB		 2949 .channels_max = 2,
2950 .rates = WM8994_RATES,
2951 .formats = WM8994_FORMATS,
99b0292d 2952 .sig_bits = 24,
9e6e96a1 2953 },
a8462bde 2954 .capture = {
9e6e96a1 2955 .stream_name = "AIF3 Capture",
b1e43d93 2956 .channels_min = 1,
9e6e96a1
MB		 2957 .channels_max = 2,
2958 .rates = WM8994_RATES,
2959 .formats = WM8994_FORMATS,
99b0292d
MB		 2960 .sig_bits = 24,
2961 },
778a76e2 2962 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2963 }
2964};
9e6e96a1
MB		 2965
2966#ifdef CONFIG_PM
4752a887 2967static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 2968{
b2c812e2 2969 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2970 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2971 int i, ret;
2972
ca629928
MB		 2973 switch (control->type) {
2974 case WM8994:
2975 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2976 break;
81204c84 2977 case WM1811:
af6b6fe4
MB		 2978 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2979 WM1811_JACKDET_MODE_MASK, 0);
2980 /* Fall through */
ca629928
MB		 2981 case WM8958:
2982 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2983 WM8958_MICD_ENA, 0);
2984 break;
2985 }
2986
9e6e96a1
MB		 2987 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2988 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2989 sizeof(struct wm8994_fll_config));
f0fba2ad 2990 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2991 if (ret < 0)
2992 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2993 i + 1, ret);
2994 }
2995
2996 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2997
2998 return 0;
2999}
3000
4752a887 3001static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 3002{
b2c812e2 3003 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3004 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 3005 int i, ret;
c52fd021
DP		 3006 unsigned int val, mask;
3007
3008 if (wm8994->revision < 4) {
3009 /* force a HW read */
d9a7666f
MB		 3010 ret = regmap_read(control->regmap,
3011 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 3012
3013 /* modify the cache only */
3014 codec->cache_only = 1;
3015 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3016 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3017 val &= mask;
3018 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3019 mask, val);
3020 codec->cache_only = 0;
3021 }
9e6e96a1 3022
9e6e96a1 3023 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 3024 if (!wm8994->fll_suspend[i].out)
3025 continue;
3026
f0fba2ad 3027 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 3028 wm8994->fll_suspend[i].src,
3029 wm8994->fll_suspend[i].in,
3030 wm8994->fll_suspend[i].out);
3031 if (ret < 0)
3032 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3033 i + 1, ret);
3034 }
3035
ca629928
MB		 3036 switch (control->type) {
3037 case WM8994:
3038 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3039 snd_soc_update_bits(codec, WM8994_MICBIAS,
3040 WM8994_MICD_ENA, WM8994_MICD_ENA);
3041 break;
81204c84 3042 case WM1811:
af6b6fe4
MB		 3043 if (wm8994->jackdet && wm8994->jack_cb) {
3044 /* Restart from idle */
3045 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3046 WM1811_JACKDET_MODE_MASK,
3047 WM1811_JACKDET_MODE_JACK);
3048 break;
3049 }
6f8270cc 3050 break;
ca629928
MB		 3051 case WM8958:
3052 if (wm8994->jack_cb)
3053 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3054 WM8958_MICD_ENA, WM8958_MICD_ENA);
3055 break;
3056 }
3057
9e6e96a1
MB		 3058 return 0;
3059}
3060#else
4752a887
MB		 3061#define wm8994_codec_suspend NULL
3062#define wm8994_codec_resume NULL
9e6e96a1
MB		 3063#endif
3064
3065static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3066{
f0fba2ad 3067 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 3068 struct wm8994_pdata *pdata = wm8994->pdata;
3069 struct snd_kcontrol_new controls[] = {
3070 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3071 wm8994->retune_mobile_enum,
3072 wm8994_get_retune_mobile_enum,
3073 wm8994_put_retune_mobile_enum),
3074 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3075 wm8994->retune_mobile_enum,
3076 wm8994_get_retune_mobile_enum,
3077 wm8994_put_retune_mobile_enum),
3078 SOC_ENUM_EXT("AIF2 EQ Mode",
3079 wm8994->retune_mobile_enum,
3080 wm8994_get_retune_mobile_enum,
3081 wm8994_put_retune_mobile_enum),
3082 };
3083 int ret, i, j;
3084 const char **t;
3085
3086 /* We need an array of texts for the enum API but the number
3087 * of texts is likely to be less than the number of
3088 * configurations due to the sample rate dependency of the
3089 * configurations. */
3090 wm8994->num_retune_mobile_texts = 0;
3091 wm8994->retune_mobile_texts = NULL;
3092 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3093 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3094 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3095 wm8994->retune_mobile_texts[j]) == 0)
3096 break;
3097 }
3098
3099 if (j != wm8994->num_retune_mobile_texts)
3100 continue;
3101
3102 /* Expand the array... */
3103 t = krealloc(wm8994->retune_mobile_texts,
c1a4ecd9 3104 sizeof(char *) *
9e6e96a1
MB		 3105 (wm8994->num_retune_mobile_texts + 1),
3106 GFP_KERNEL);
3107 if (t == NULL)
3108 continue;
3109
3110 /* ...store the new entry... */
c1a4ecd9 3111 t[wm8994->num_retune_mobile_texts] =
9e6e96a1
MB		 3112 pdata->retune_mobile_cfgs[i].name;
3113
3114 /* ...and remember the new version. */
3115 wm8994->num_retune_mobile_texts++;
3116 wm8994->retune_mobile_texts = t;
3117 }
3118
3119 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3120 wm8994->num_retune_mobile_texts);
3121
3122 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3123 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3124
022658be 3125 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 3126 ARRAY_SIZE(controls));
3127 if (ret != 0)
f0fba2ad 3128 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 3129 "Failed to add ReTune Mobile controls: %d\n", ret);
3130}
3131
3132static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3133{
f0fba2ad 3134 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 3135 struct wm8994_pdata *pdata = wm8994->pdata;
3136 int ret, i;
3137
3138 if (!pdata)
3139 return;
3140
3141 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3142 pdata->lineout2_diff,
3143 pdata->lineout1fb,
3144 pdata->lineout2fb,
3145 pdata->jd_scthr,
3146 pdata->jd_thr,
3147 pdata->micbias1_lvl,
3148 pdata->micbias2_lvl);
3149
3150 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3151
3152 if (pdata->num_drc_cfgs) {
3153 struct snd_kcontrol_new controls[] = {
3154 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3155 wm8994_get_drc_enum, wm8994_put_drc_enum),
3156 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3157 wm8994_get_drc_enum, wm8994_put_drc_enum),
3158 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3159 wm8994_get_drc_enum, wm8994_put_drc_enum),
3160 };
3161
3162 /* We need an array of texts for the enum API */
7270cebe
MB		 3163 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
3164 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3165 if (!wm8994->drc_texts) {
f0fba2ad 3166 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 3167 "Failed to allocate %d DRC config texts\n",
3168 pdata->num_drc_cfgs);
3169 return;
3170 }
3171
3172 for (i = 0; i < pdata->num_drc_cfgs; i++)
3173 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3174
3175 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3176 wm8994->drc_enum.texts = wm8994->drc_texts;
3177
022658be 3178 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 3179 ARRAY_SIZE(controls));
3180 if (ret != 0)
f0fba2ad 3181 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 3182 "Failed to add DRC mode controls: %d\n", ret);
3183
3184 for (i = 0; i < WM8994_NUM_DRC; i++)
3185 wm8994_set_drc(codec, i);
3186 }
3187
3188 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3189 pdata->num_retune_mobile_cfgs);
3190
3191 if (pdata->num_retune_mobile_cfgs)
3192 wm8994_handle_retune_mobile_pdata(wm8994);
3193 else
022658be 3194 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 3195 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3196
3197 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3198 if (pdata->micbias[i]) {
3199 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3200 pdata->micbias[i] & 0xffff);
3201 }
3202 }
9e6e96a1
MB		 3203}
3204
88766984
MB		 3205/**
3206 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3207 *
3208 * @codec: WM8994 codec
3209 * @jack: jack to report detection events on
3210 * @micbias: microphone bias to detect on
88766984
MB		 3211 *
3212 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3213 * being used to bring out signals to the processor then only platform
5ab230a7 3214 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3215 * be configured using snd_soc_jack_add_gpios() instead.
3216 *
3217 * Configuration of detection levels is available via the micbias1_lvl
3218 * and micbias2_lvl platform data members.
3219 */
3220int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3221 int micbias)
88766984 3222{
b2c812e2 3223 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3224 struct wm8994_micdet *micdet;
2a8a856d 3225 struct wm8994 *control = wm8994->wm8994;
87092e3c 3226 int reg, ret;
88766984 3227
87092e3c
MB		 3228 if (control->type != WM8994) {
3229 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3230 return -EINVAL;
87092e3c 3231 }
3a423157 3232
88766984
MB		 3233 switch (micbias) {
3234 case 1:
3235 micdet = &wm8994->micdet[0];
87092e3c
MB		 3236 if (jack)
3237 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3238 "MICBIAS1");
3239 else
3240 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3241 "MICBIAS1");
88766984
MB		 3242 break;
3243 case 2:
3244 micdet = &wm8994->micdet[1];
87092e3c
MB		 3245 if (jack)
3246 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3247 "MICBIAS1");
3248 else
3249 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3250 "MICBIAS1");
88766984
MB		 3251 break;
3252 default:
87092e3c 3253 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3254 return -EINVAL;
87092e3c 3255 }
88766984 3256
87092e3c
MB		 3257 if (ret != 0)
3258 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3259 micbias, ret);
3260
3261 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3262 micbias, jack);
88766984
MB		 3263
3264 /* Store the configuration */
3265 micdet->jack = jack;
87092e3c 3266 micdet->detecting = true;
88766984
MB		 3267
3268 /* If either of the jacks is set up then enable detection */
3269 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3270 reg = WM8994_MICD_ENA;
87092e3c 3271 else
88766984
MB		 3272 reg = 0;
3273
3274 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3275
87092e3c
MB		 3276 snd_soc_dapm_sync(&codec->dapm);
3277
88766984
MB		 3278 return 0;
3279}
3280EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3281
e9b54de4 3282static void wm8994_mic_work(struct work_struct *work)
88766984 3283{
e9b54de4
MB		 3284 struct wm8994_priv *priv = container_of(work,
3285 struct wm8994_priv,
3286 mic_work.work);
fdfc4f3e
MB		 3287 struct regmap *regmap = priv->wm8994->regmap;
3288 struct device *dev = priv->wm8994->dev;
3289 unsigned int reg;
3290 int ret;
88766984
MB		 3291 int report;
3292
fdfc4f3e
MB		 3293 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3294 if (ret < 0) {
3295 dev_err(dev, "Failed to read microphone status: %d\n",
3296 ret);
e9b54de4 3297 return;
88766984
MB		 3298 }
3299
fdfc4f3e 3300 dev_dbg(dev, "Microphone status: %x\n", reg);
88766984
MB		 3301
3302 report = 0;
87092e3c
MB		 3303 if (reg & WM8994_MIC1_DET_STS) {
3304 if (priv->micdet[0].detecting)
3305 report = SND_JACK_HEADSET;
3306 }
3307 if (reg & WM8994_MIC1_SHRT_STS) {
3308 if (priv->micdet[0].detecting)
3309 report = SND_JACK_HEADPHONE;
3310 else
3311 report |= SND_JACK_BTN_0;
3312 }
3313 if (report)
3314 priv->micdet[0].detecting = false;
3315 else
3316 priv->micdet[0].detecting = true;
3317
88766984 3318 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3319 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3320
3321 report = 0;
87092e3c
MB		 3322 if (reg & WM8994_MIC2_DET_STS) {
3323 if (priv->micdet[1].detecting)
3324 report = SND_JACK_HEADSET;
3325 }
3326 if (reg & WM8994_MIC2_SHRT_STS) {
3327 if (priv->micdet[1].detecting)
3328 report = SND_JACK_HEADPHONE;
3329 else
3330 report |= SND_JACK_BTN_0;
3331 }
3332 if (report)
3333 priv->micdet[1].detecting = false;
3334 else
3335 priv->micdet[1].detecting = true;
3336
88766984 3337 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3338 SND_JACK_HEADSET | SND_JACK_BTN_0);
e9b54de4
MB		 3339}
3340
3341static irqreturn_t wm8994_mic_irq(int irq, void *data)
3342{
3343 struct wm8994_priv *priv = data;
3344 struct snd_soc_codec *codec = priv->codec;
3345
3346#ifndef CONFIG_SND_SOC_WM8994_MODULE
3347 trace_snd_soc_jack_irq(dev_name(codec->dev));
3348#endif
3349
3350 pm_wakeup_event(codec->dev, 300);
3351
3352 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
88766984
MB		 3353
3354 return IRQ_HANDLED;
3355}
3356
821edd2f
MB		 3357/* Default microphone detection handler for WM8958 - the user can
3358 * override this if they wish.
3359 */
3360static void wm8958_default_micdet(u16 status, void *data)
3361{
3362 struct snd_soc_codec *codec = data;
3363 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3364 int report;
821edd2f 3365
a1691343
MB		 3366 dev_dbg(codec->dev, "MICDET %x\n", status);
3367
af6b6fe4 3368 /* Either nothing present or just starting detection */
b00adf76 3369 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3370 if (!wm8994->jackdet) {
3371 /* If nothing present then clear our statuses */
3372 dev_dbg(codec->dev, "Detected open circuit\n");
3373 wm8994->jack_mic = false;
3374 wm8994->mic_detecting = true;
b00adf76 3375
af6b6fe4 3376 wm8958_micd_set_rate(codec);
b00adf76 3377
af6b6fe4
MB		 3378 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3379 wm8994->btn_mask |
3380 SND_JACK_HEADSET);
3381 }
b00adf76
MB		 3382 return;
3383 }
821edd2f 3384
b00adf76
MB		 3385 /* If the measurement is showing a high impedence we've got a
3386 * microphone.
3387 */
157a75e6 3388 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3389 dev_dbg(codec->dev, "Detected microphone\n");
3390
157a75e6 3391 wm8994->mic_detecting = false;
b00adf76
MB		 3392 wm8994->jack_mic = true;
3393
3394 wm8958_micd_set_rate(codec);
3395
3396 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3397 SND_JACK_HEADSET);
3398 }
821edd2f 3399
b00adf76 3400
7c08b51f 3401 if (wm8994->mic_detecting && status & 0xfc) {
b00adf76 3402 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3403 wm8994->mic_detecting = false;
b00adf76
MB		 3404
3405 wm8958_micd_set_rate(codec);
3406
af6b6fe4
MB		 3407 /* If we have jackdet that will detect removal */
3408 if (wm8994->jackdet) {
c986564b
MB		 3409 mutex_lock(&wm8994->accdet_lock);
3410
af6b6fe4
MB		 3411 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3412 WM8958_MICD_ENA, 0);
3413
c986564b
MB		 3414 wm1811_jackdet_set_mode(codec,
3415 WM1811_JACKDET_MODE_JACK);
3416
3417 mutex_unlock(&wm8994->accdet_lock);
3418
ecd1732f 3419 if (wm8994->pdata->jd_ext_cap)
07fb9d9e
MB		 3420 snd_soc_dapm_disable_pin(&codec->dapm,
3421 "MICBIAS2");
af6b6fe4 3422 }
ecd1732f
MB		 3423
3424 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3425 SND_JACK_HEADSET);
b00adf76
MB		 3426 }
3427
3428 /* Report short circuit as a button */
3429 if (wm8994->jack_mic) {
4585790d 3430 report = 0;
b00adf76 3431 if (status & 0x4)
4585790d
MB		 3432 report |= SND_JACK_BTN_0;
3433
3434 if (status & 0x8)
3435 report |= SND_JACK_BTN_1;
3436
3437 if (status & 0x10)
3438 report |= SND_JACK_BTN_2;
3439
3440 if (status & 0x20)
3441 report |= SND_JACK_BTN_3;
3442
3443 if (status & 0x40)
3444 report |= SND_JACK_BTN_4;
3445
3446 if (status & 0x80)
3447 report |= SND_JACK_BTN_5;
3448
3449 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3450 wm8994->btn_mask);
b00adf76 3451 }
821edd2f
MB		 3452}
3453
af6b6fe4
MB		 3454static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3455{
3456 struct wm8994_priv *wm8994 = data;
3457 struct snd_soc_codec *codec = wm8994->codec;
3458 int reg;
c986564b 3459 bool present;
af6b6fe4
MB		 3460
3461 mutex_lock(&wm8994->accdet_lock);
3462
3463 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3464 if (reg < 0) {
3465 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3466 mutex_unlock(&wm8994->accdet_lock);
3467 return IRQ_NONE;
3468 }
3469
3470 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3471
c986564b 3472 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3473
c986564b
MB		 3474 if (present) {
3475 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3476
e9d9a968
MB		 3477 wm8958_micd_set_rate(codec);
3478
55a27786
MB		 3479 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3480 WM8958_MICB2_DISCH, 0);
3481
378ec0ca
MB		 3482 /* Disable debounce while inserted */
3483 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3484 WM1811_JACKDET_DB, 0);
3485
af6b6fe4
MB		 3486 /*
3487 * Start off measument of microphone impedence to find
3488 * out what's actually there.
3489 */
3490 wm8994->mic_detecting = true;
3491 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
b9e67e5e 3492
af6b6fe4
MB		 3493 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3494 WM8958_MICD_ENA, WM8958_MICD_ENA);
3495 } else {
3496 dev_dbg(codec->dev, "Jack not detected\n");
3497
55a27786
MB		 3498 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3499 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3500
378ec0ca
MB		 3501 /* Enable debounce while removed */
3502 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3503 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3504
af6b6fe4
MB		 3505 wm8994->mic_detecting = false;
3506 wm8994->jack_mic = false;
3507 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3508 WM8958_MICD_ENA, 0);
3509 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3510 }
3511
3512 mutex_unlock(&wm8994->accdet_lock);
3513
c986564b
MB		 3514 /* If required for an external cap force MICBIAS on */
3515 if (wm8994->pdata->jd_ext_cap) {
c986564b
MB		 3516 if (present)
3517 snd_soc_dapm_force_enable_pin(&codec->dapm,
3518 "MICBIAS2");
3519 else
3520 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3521 }
3522
3523 if (present)
3524 snd_soc_jack_report(wm8994->micdet[0].jack,
3525 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3526 else
3527 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3528 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3529 wm8994->btn_mask);
3530
af6b6fe4
MB		 3531 return IRQ_HANDLED;
3532}
3533
821edd2f
MB		 3534/**
3535 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3536 *
3537 * @codec: WM8958 codec
3538 * @jack: jack to report detection events on
3539 *
3540 * Enable microphone detection functionality for the WM8958. By
3541 * default simple detection which supports the detection of up to 6
3542 * buttons plus video and microphone functionality is supported.
3543 *
3544 * The WM8958 has an advanced jack detection facility which is able to
3545 * support complex accessory detection, especially when used in
3546 * conjunction with external circuitry. In order to provide maximum
3547 * flexiblity a callback is provided which allows a completely custom
3548 * detection algorithm.
3549 */
3550int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3551 wm8958_micdet_cb cb, void *cb_data)
3552{
3553 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3554 struct wm8994 *control = wm8994->wm8994;
4585790d 3555 u16 micd_lvl_sel;
821edd2f 3556
81204c84
MB		 3557 switch (control->type) {
3558 case WM1811:
3559 case WM8958:
3560 break;
3561 default:
821edd2f 3562 return -EINVAL;
81204c84 3563 }
821edd2f
MB		 3564
3565 if (jack) {
3566 if (!cb) {
3567 dev_dbg(codec->dev, "Using default micdet callback\n");
3568 cb = wm8958_default_micdet;
3569 cb_data = codec;
3570 }
3571
4cdf5e49 3572 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3573 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3574
821edd2f
MB		 3575 wm8994->micdet[0].jack = jack;
3576 wm8994->jack_cb = cb;
3577 wm8994->jack_cb_data = cb_data;
3578
157a75e6 3579 wm8994->mic_detecting = true;
b00adf76
MB		 3580 wm8994->jack_mic = false;
3581
3582 wm8958_micd_set_rate(codec);
3583
4585790d
MB		 3584 /* Detect microphones and short circuits by default */
3585 if (wm8994->pdata->micd_lvl_sel)
3586 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3587 else
3588 micd_lvl_sel = 0x41;
3589
3590 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3591 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3592 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3593
b00adf76 3594 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3595 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3596
af6b6fe4
MB		 3597 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3598
3599 /*
3600 * If we can use jack detection start off with that,
3601 * otherwise jump straight to microphone detection.
3602 */
3603 if (wm8994->jackdet) {
55a27786
MB		 3604 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3605 WM8958_MICB2_DISCH,
3606 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3607 snd_soc_update_bits(codec, WM8994_LDO_1,
3608 WM8994_LDO1_DISCH, 0);
3609 wm1811_jackdet_set_mode(codec,
3610 WM1811_JACKDET_MODE_JACK);
3611 } else {
3612 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3613 WM8958_MICD_ENA, WM8958_MICD_ENA);
3614 }
3615
821edd2f
MB		 3616 } else {
3617 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3618 WM8958_MICD_ENA, 0);
afaf1591 3619 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3620 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3621 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3622 }
3623
3624 return 0;
3625}
3626EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3627
3628static irqreturn_t wm8958_mic_irq(int irq, void *data)
3629{
3630 struct wm8994_priv *wm8994 = data;
3631 struct snd_soc_codec *codec = wm8994->codec;
19940b3d 3632 int reg, count;
821edd2f 3633
af6b6fe4
MB		 3634 /*
3635 * Jack detection may have detected a removal simulataneously
3636 * with an update of the MICDET status; if so it will have
3637 * stopped detection and we can ignore this interrupt.
3638 */
c986564b 3639 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3640 return IRQ_HANDLED;
af6b6fe4 3641
19940b3d
MB		 3642 /* We may occasionally read a detection without an impedence
3643 * range being provided - if that happens loop again.
3644 */
3645 count = 10;
3646 do {
3647 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3648 if (reg < 0) {
3649 dev_err(codec->dev,
3650 "Failed to read mic detect status: %d\n",
3651 reg);
3652 return IRQ_NONE;
3653 }
821edd2f 3654
19940b3d
MB		 3655 if (!(reg & WM8958_MICD_VALID)) {
3656 dev_dbg(codec->dev, "Mic detect data not valid\n");
3657 goto out;
3658 }
3659
3660 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3661 break;
3662
3663 msleep(1);
3664 } while (count--);
3665
3666 if (count == 0)
3667 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3668
7116f452 3669#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3670 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3671#endif
2bbb5d66 3672
821edd2f
MB		 3673 if (wm8994->jack_cb)
3674 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3675 else
3676 dev_warn(codec->dev, "Accessory detection with no callback\n");
3677
3678out:
3679 return IRQ_HANDLED;
3680}
3681
3b1af3f8
MB		 3682static irqreturn_t wm8994_fifo_error(int irq, void *data)
3683{
3684 struct snd_soc_codec *codec = data;
3685
3686 dev_err(codec->dev, "FIFO error\n");
3687
3688 return IRQ_HANDLED;
3689}
3690
f0b182b0
MB		 3691static irqreturn_t wm8994_temp_warn(int irq, void *data)
3692{
3693 struct snd_soc_codec *codec = data;
3694
3695 dev_err(codec->dev, "Thermal warning\n");
3696
3697 return IRQ_HANDLED;
3698}
3699
3700static irqreturn_t wm8994_temp_shut(int irq, void *data)
3701{
3702 struct snd_soc_codec *codec = data;
3703
3704 dev_crit(codec->dev, "Thermal shutdown\n");
3705
3706 return IRQ_HANDLED;
3707}
3708
f0fba2ad 3709static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3710{
d9a7666f 3711 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3712 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3713 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3714 unsigned int reg;
ec62dbd7 3715 int ret, i;
9e6e96a1 3716
2bc16ed8 3717 wm8994->codec = codec;
d9a7666f 3718 codec->control_data = control->regmap;
9e6e96a1 3719
d9a7666f 3720 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3721
f0fba2ad 3722 wm8994->codec = codec;
9e6e96a1 3723
af6b6fe4 3724 mutex_init(&wm8994->accdet_lock);
e9b54de4 3725 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
af6b6fe4 3726
c7ebf932
MB		 3727 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3728 init_completion(&wm8994->fll_locked[i]);
3729
9b7c525d
MB		 3730 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3731 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3732 else if (wm8994->pdata && wm8994->pdata->irq_base)
3733 wm8994->micdet_irq = wm8994->pdata->irq_base +
3734 WM8994_IRQ_MIC1_DET;
3735
39fb51a1 3736 pm_runtime_enable(codec->dev);
5fab5174 3737 pm_runtime_idle(codec->dev);
39fb51a1 3738
f959dee9
MB		 3739 /* By default use idle_bias_off, will override for WM8994 */
3740 codec->dapm.idle_bias_off = 1;
3741
9e6e96a1 3742 /* Set revision-specific configuration */
b6b05691 3743 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3744 switch (control->type) {
3745 case WM8994:
f959dee9
MB		 3746 /* Single ended line outputs should have VMID on. */
3747 if (!wm8994->pdata->lineout1_diff ||
3748 !wm8994->pdata->lineout2_diff)
3749 codec->dapm.idle_bias_off = 0;
3750
3a423157
MB		 3751 switch (wm8994->revision) {
3752 case 2:
3753 case 3:
4537c4e7
MB		 3754 wm8994->hubs.dcs_codes_l = -5;
3755 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3756 wm8994->hubs.hp_startup_mode = 1;
3757 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3758 wm8994->hubs.series_startup = 1;
3a423157
MB		 3759 break;
3760 default:
79ef0abc 3761 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3762 break;
3763 }
280ec8b7 3764 break;
3a423157
MB		 3765
3766 case WM8958:
8437f700 3767 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3768 wm8994->hubs.hp_startup_mode = 1;
20dc24a9
MB		 3769
3770 switch (wm8994->revision) {
3771 case 0:
3772 break;
3773 default:
3774 wm8994->fll_byp = true;
3775 break;
3776 }
9e6e96a1 3777 break;
3a423157 3778
81204c84
MB		 3779 case WM1811:
3780 wm8994->hubs.dcs_readback_mode = 2;
3781 wm8994->hubs.no_series_update = 1;
29fdc360 3782 wm8994->hubs.hp_startup_mode = 1;
af31a227 3783 wm8994->hubs.no_cache_dac_hp_direct = true;
20dc24a9 3784 wm8994->fll_byp = true;
81204c84
MB		 3785
3786 switch (wm8994->revision) {
3787 case 0:
3788 case 1:
fc8e6e86
MB		 3789 case 2:
3790 case 3:
6473a148 3791 wm8994->hubs.dcs_codes_l = -9;
e1660585 3792 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB		 3793 break;
3794 default:
3795 break;
3796 }
3797
3798 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3799 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3800 break;
3801
9e6e96a1
MB		 3802 default:
3803 break;
3804 }
9e6e96a1 3805
2a8a856d 3806 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3807 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3808 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3809 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3810 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3811 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3812
2a8a856d 3813 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3814 wm_hubs_dcs_done, "DC servo done",
3815 &wm8994->hubs);
3816 if (ret == 0)
3817 wm8994->hubs.dcs_done_irq = true;
3818
3a423157
MB		 3819 switch (control->type) {
3820 case WM8994:
9b7c525d
MB		 3821 if (wm8994->micdet_irq) {
3822 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3823 wm8994_mic_irq,
3824 IRQF_TRIGGER_RISING,
3825 "Mic1 detect",
3826 wm8994);
3827 if (ret != 0)
3828 dev_warn(codec->dev,
3829 "Failed to request Mic1 detect IRQ: %d\n",
3830 ret);
3831 }
3a423157 3832
2a8a856d 3833 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3834 WM8994_IRQ_MIC1_SHRT,
3835 wm8994_mic_irq, "Mic 1 short",
3836 wm8994);
3837 if (ret != 0)
3838 dev_warn(codec->dev,
3839 "Failed to request Mic1 short IRQ: %d\n",
3840 ret);
3841
2a8a856d 3842 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3843 WM8994_IRQ_MIC2_DET,
3844 wm8994_mic_irq, "Mic 2 detect",
3845 wm8994);
3846 if (ret != 0)
3847 dev_warn(codec->dev,
3848 "Failed to request Mic2 detect IRQ: %d\n",
3849 ret);
3850
2a8a856d 3851 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3852 WM8994_IRQ_MIC2_SHRT,
3853 wm8994_mic_irq, "Mic 2 short",
3854 wm8994);
3855 if (ret != 0)
3856 dev_warn(codec->dev,
3857 "Failed to request Mic2 short IRQ: %d\n",
3858 ret);
3859 break;
821edd2f
MB		 3860
3861 case WM8958:
81204c84 3862 case WM1811:
9b7c525d
MB		 3863 if (wm8994->micdet_irq) {
3864 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3865 wm8958_mic_irq,
3866 IRQF_TRIGGER_RISING,
3867 "Mic detect",
3868 wm8994);
3869 if (ret != 0)
3870 dev_warn(codec->dev,
3871 "Failed to request Mic detect IRQ: %d\n",
3872 ret);
3873 }
3a423157 3874 }
88766984 3875
af6b6fe4
MB		 3876 switch (control->type) {
3877 case WM1811:
3878 if (wm8994->revision > 1) {
3879 ret = wm8994_request_irq(wm8994->wm8994,
3880 WM8994_IRQ_GPIO(6),
3881 wm1811_jackdet_irq, "JACKDET",
3882 wm8994);
3883 if (ret == 0)
3884 wm8994->jackdet = true;
3885 }
3886 break;
3887 default:
3888 break;
3889 }
3890
c7ebf932
MB		 3891 wm8994->fll_locked_irq = true;
3892 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3893 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3894 WM8994_IRQ_FLL1_LOCK + i,
3895 wm8994_fll_locked_irq, "FLL lock",
3896 &wm8994->fll_locked[i]);
3897 if (ret != 0)
3898 wm8994->fll_locked_irq = false;
3899 }
3900
27060b3c
MB		 3901 /* Make sure we can read from the GPIOs if they're inputs */
3902 pm_runtime_get_sync(codec->dev);
3903
9e6e96a1
MB		 3904 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3905 * configured on init - if a system wants to do this dynamically
3906 * at runtime we can deal with that then.
3907 */
d9a7666f 3908 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3909 if (ret < 0) {
3910 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3911 goto err_irq;
9e6e96a1 3912 }
d9a7666f 3913 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3914 wm8994->lrclk_shared[0] = 1;
3915 wm8994_dai[0].symmetric_rates = 1;
3916 } else {
3917 wm8994->lrclk_shared[0] = 0;
3918 }
3919
d9a7666f 3920 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 3921 if (ret < 0) {
3922 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3923 goto err_irq;
9e6e96a1 3924 }
d9a7666f 3925 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3926 wm8994->lrclk_shared[1] = 1;
3927 wm8994_dai[1].symmetric_rates = 1;
3928 } else {
3929 wm8994->lrclk_shared[1] = 0;
3930 }
3931
27060b3c
MB		 3932 pm_runtime_put(codec->dev);
3933
bfd37bb5
MB		 3934 /* Latch volume update bits */
3935 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
3936 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
3937 wm8994_vu_bits[i].mask,
3938 wm8994_vu_bits[i].mask);
9e6e96a1
MB		 3939
3940 /* Set the low bit of the 3D stereo depth so TLV matches */
3941 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3942 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3943 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3944 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3945 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3946 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3947 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3948 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3949 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3950
5b739670
MB		 3951 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3952 * use this; it only affects behaviour on idle TDM clock
3953 * cycles. */
3954 switch (control->type) {
3955 case WM8994:
3956 case WM8958:
3957 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3958 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3959 break;
3960 default:
3961 break;
3962 }
d1ce6b20 3963
500fa30e
MB		 3964 /* Put MICBIAS into bypass mode by default on newer devices */
3965 switch (control->type) {
3966 case WM8958:
3967 case WM1811:
3968 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3969 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3970 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3971 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3972 break;
3973 default:
3974 break;
3975 }
3976
c340304d
MB		 3977 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
3978 wm_hubs_update_class_w(codec);
9e6e96a1 3979
f0fba2ad 3980 wm8994_handle_pdata(wm8994);
9e6e96a1 3981
f0fba2ad 3982 wm_hubs_add_analogue_controls(codec);
022658be 3983 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 3984 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3985 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3986 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3987
3988 switch (control->type) {
3989 case WM8994:
3990 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3991 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3992 if (wm8994->revision < 4) {
173efa09
DP		 3993 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3994 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3995 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3996 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3997 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3998 ARRAY_SIZE(wm8994_dac_revd_widgets));
3999 } else {
173efa09
DP		 4000 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4001 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 4002 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4003 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 4004 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4005 ARRAY_SIZE(wm8994_dac_widgets));
4006 }
c4431df0
MB		 4007 break;
4008 case WM8958:
022658be 4009 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 4010 ARRAY_SIZE(wm8958_snd_controls));
4011 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4012 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 4013 if (wm8994->revision < 1) {
4014 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4015 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4016 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4017 ARRAY_SIZE(wm8994_adc_revd_widgets));
4018 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4019 ARRAY_SIZE(wm8994_dac_revd_widgets));
4020 } else {
4021 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4022 ARRAY_SIZE(wm8994_lateclk_widgets));
4023 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4024 ARRAY_SIZE(wm8994_adc_widgets));
4025 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4026 ARRAY_SIZE(wm8994_dac_widgets));
4027 }
c4431df0 4028 break;
81204c84
MB		 4029
4030 case WM1811:
022658be 4031 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 4032 ARRAY_SIZE(wm8958_snd_controls));
4033 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4034 ARRAY_SIZE(wm8958_dapm_widgets));
4035 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4036 ARRAY_SIZE(wm8994_lateclk_widgets));
4037 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4038 ARRAY_SIZE(wm8994_adc_widgets));
4039 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4040 ARRAY_SIZE(wm8994_dac_widgets));
4041 break;
c4431df0 4042 }
c4431df0 4043
f0fba2ad 4044 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 4045 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 4046
c4431df0
MB		 4047 switch (control->type) {
4048 case WM8994:
4049 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4050 ARRAY_SIZE(wm8994_intercon));
6ed8f148 4051
173efa09 4052 if (wm8994->revision < 4) {
6ed8f148
MB		 4053 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4054 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 4055 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4056 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4057 } else {
4058 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4059 ARRAY_SIZE(wm8994_lateclk_intercon));
4060 }
c4431df0
MB		 4061 break;
4062 case WM8958:
780e2806
MB		 4063 if (wm8994->revision < 1) {
4064 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4065 ARRAY_SIZE(wm8994_revd_intercon));
4066 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4067 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4068 } else {
4069 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4070 ARRAY_SIZE(wm8994_lateclk_intercon));
4071 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4072 ARRAY_SIZE(wm8958_intercon));
4073 }
f701a2e5
MB		 4074
4075 wm8958_dsp2_init(codec);
c4431df0 4076 break;
81204c84
MB		 4077 case WM1811:
4078 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4079 ARRAY_SIZE(wm8994_lateclk_intercon));
4080 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4081 ARRAY_SIZE(wm8958_intercon));
4082 break;
c4431df0
MB		 4083 }
4084
9e6e96a1
MB		 4085 return 0;
4086
88766984 4087err_irq:
af6b6fe4
MB		 4088 if (wm8994->jackdet)
4089 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 4090 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4091 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4092 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 4093 if (wm8994->micdet_irq)
4094 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 4095 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4096 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 4097 &wm8994->fll_locked[i]);
2a8a856d 4098 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4099 &wm8994->hubs);
2a8a856d
MB		 4100 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4101 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4102 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 4103
9e6e96a1
MB		 4104 return ret;
4105}
4106
34ff0f95 4107static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 4108{
f0fba2ad 4109 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 4110 struct wm8994 *control = wm8994->wm8994;
c7ebf932 4111 int i;
9e6e96a1
MB		 4112
4113 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 4114
39fb51a1
MB		 4115 pm_runtime_disable(codec->dev);
4116
c7ebf932 4117 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4118 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 4119 &wm8994->fll_locked[i]);
4120
2a8a856d 4121 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4122 &wm8994->hubs);
2a8a856d
MB		 4123 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4124 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4125 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 4126
af6b6fe4
MB		 4127 if (wm8994->jackdet)
4128 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4129
3a423157
MB		 4130 switch (control->type) {
4131 case WM8994:
9b7c525d
MB		 4132 if (wm8994->micdet_irq)
4133 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 4134 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 4135 wm8994);
2a8a856d 4136 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 4137 wm8994);
2a8a856d 4138 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 4139 wm8994);
4140 break;
821edd2f 4141
81204c84 4142 case WM1811:
821edd2f 4143 case WM8958:
9b7c525d
MB		 4144 if (wm8994->micdet_irq)
4145 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4146 break;
3a423157 4147 }
34ff0f95
JJ		 4148 release_firmware(wm8994->mbc);
4149 release_firmware(wm8994->mbc_vss);
4150 release_firmware(wm8994->enh_eq);
24fb2b11 4151 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 4152 return 0;
4153}
4154
f0fba2ad
LG		 4155static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4156 .probe = wm8994_codec_probe,
4157 .remove = wm8994_codec_remove,
4752a887
MB		 4158 .suspend = wm8994_codec_suspend,
4159 .resume = wm8994_codec_resume,
f0fba2ad
LG		 4160 .set_bias_level = wm8994_set_bias_level,
4161};
4162
4163static int __devinit wm8994_probe(struct platform_device *pdev)
4164{
2bc16ed8
MB		 4165 struct wm8994_priv *wm8994;
4166
4167 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4168 GFP_KERNEL);
4169 if (wm8994 == NULL)
4170 return -ENOMEM;
4171 platform_set_drvdata(pdev, wm8994);
4172
4173 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4174 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4175
f0fba2ad
LG		 4176 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4177 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4178}
4179
4180static int __devexit wm8994_remove(struct platform_device *pdev)
4181{
4182 snd_soc_unregister_codec(&pdev->dev);
4183 return 0;
4184}
4185
4752a887
MB		 4186#ifdef CONFIG_PM_SLEEP
4187static int wm8994_suspend(struct device *dev)
4188{
4189 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4190
4191 /* Drop down to power saving mode when system is suspended */
4192 if (wm8994->jackdet && !wm8994->active_refcount)
4193 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4194 WM1811_JACKDET_MODE_MASK,
4195 wm8994->jackdet_mode);
4196
4197 return 0;
4198}
4199
4200static int wm8994_resume(struct device *dev)
4201{
4202 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4203
4204 if (wm8994->jackdet && wm8994->jack_cb)
4205 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4206 WM1811_JACKDET_MODE_MASK,
4207 WM1811_JACKDET_MODE_AUDIO);
4208
4209 return 0;
4210}
4211#endif
4212
4213static const struct dev_pm_ops wm8994_pm_ops = {
4214 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4215};
4216
9e6e96a1
MB		 4217static struct platform_driver wm8994_codec_driver = {
4218 .driver = {
4752a887
MB		 4219 .name = "wm8994-codec",
4220 .owner = THIS_MODULE,
4221 .pm = &wm8994_pm_ops,
4222 },
f0fba2ad
LG		 4223 .probe = wm8994_probe,
4224 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 4225};
4226
5bbcc3c0 4227module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4228
4229MODULE_DESCRIPTION("ASoC WM8994 driver");
4230MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4231MODULE_LICENSE("GPL");
4232MODULE_ALIAS("platform:wm8994-codec");
kernel source for telekom puls (alcatel/mediatek)