projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-2.6.37' into HEAD
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8993.c
CommitLineData
942c435b
MB		 1/*
2 * wm8993.c -- WM8993 ALSA SoC audio driver
3 *
be587ef4 4 * Copyright 2009, 2010 Wolfson Microelectronics plc
942c435b
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
b37e399b 19#include <linux/regulator/consumer.h>
942c435b 20#include <linux/spi/spi.h>
5a0e3ad6 21#include <linux/slab.h>
942c435b
MB		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/tlv.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/wm8993.h>
30
31#include "wm8993.h"
a2342ae3 32#include "wm_hubs.h"
942c435b 33
b37e399b
MB		 34#define WM8993_NUM_SUPPLIES 6
35static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
36 "DCVDD",
37 "DBVDD",
38 "AVDD1",
39 "AVDD2",
40 "CPVDD",
41 "SPKVDD",
42};
43
942c435b
MB		 44static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = {
45 0x8993, /* R0 - Software Reset */
46 0x0000, /* R1 - Power Management (1) */
47 0x6000, /* R2 - Power Management (2) */
48 0x0000, /* R3 - Power Management (3) */
49 0x4050, /* R4 - Audio Interface (1) */
50 0x4000, /* R5 - Audio Interface (2) */
51 0x01C8, /* R6 - Clocking 1 */
52 0x0000, /* R7 - Clocking 2 */
53 0x0000, /* R8 - Audio Interface (3) */
54 0x0040, /* R9 - Audio Interface (4) */
55 0x0004, /* R10 - DAC CTRL */
56 0x00C0, /* R11 - Left DAC Digital Volume */
57 0x00C0, /* R12 - Right DAC Digital Volume */
58 0x0000, /* R13 - Digital Side Tone */
59 0x0300, /* R14 - ADC CTRL */
60 0x00C0, /* R15 - Left ADC Digital Volume */
61 0x00C0, /* R16 - Right ADC Digital Volume */
62 0x0000, /* R17 */
63 0x0000, /* R18 - GPIO CTRL 1 */
64 0x0010, /* R19 - GPIO1 */
65 0x0000, /* R20 - IRQ_DEBOUNCE */
66 0x0000, /* R21 */
67 0x8000, /* R22 - GPIOCTRL 2 */
68 0x0800, /* R23 - GPIO_POL */
69 0x008B, /* R24 - Left Line Input 1&2 Volume */
70 0x008B, /* R25 - Left Line Input 3&4 Volume */
71 0x008B, /* R26 - Right Line Input 1&2 Volume */
72 0x008B, /* R27 - Right Line Input 3&4 Volume */
73 0x006D, /* R28 - Left Output Volume */
74 0x006D, /* R29 - Right Output Volume */
75 0x0066, /* R30 - Line Outputs Volume */
76 0x0020, /* R31 - HPOUT2 Volume */
77 0x0079, /* R32 - Left OPGA Volume */
78 0x0079, /* R33 - Right OPGA Volume */
79 0x0003, /* R34 - SPKMIXL Attenuation */
80 0x0003, /* R35 - SPKMIXR Attenuation */
81 0x0011, /* R36 - SPKOUT Mixers */
82 0x0100, /* R37 - SPKOUT Boost */
83 0x0079, /* R38 - Speaker Volume Left */
84 0x0079, /* R39 - Speaker Volume Right */
85 0x0000, /* R40 - Input Mixer2 */
86 0x0000, /* R41 - Input Mixer3 */
87 0x0000, /* R42 - Input Mixer4 */
88 0x0000, /* R43 - Input Mixer5 */
89 0x0000, /* R44 - Input Mixer6 */
90 0x0000, /* R45 - Output Mixer1 */
91 0x0000, /* R46 - Output Mixer2 */
92 0x0000, /* R47 - Output Mixer3 */
93 0x0000, /* R48 - Output Mixer4 */
94 0x0000, /* R49 - Output Mixer5 */
95 0x0000, /* R50 - Output Mixer6 */
96 0x0000, /* R51 - HPOUT2 Mixer */
97 0x0000, /* R52 - Line Mixer1 */
98 0x0000, /* R53 - Line Mixer2 */
99 0x0000, /* R54 - Speaker Mixer */
100 0x0000, /* R55 - Additional Control */
101 0x0000, /* R56 - AntiPOP1 */
102 0x0000, /* R57 - AntiPOP2 */
103 0x0000, /* R58 - MICBIAS */
104 0x0000, /* R59 */
105 0x0000, /* R60 - FLL Control 1 */
106 0x0000, /* R61 - FLL Control 2 */
107 0x0000, /* R62 - FLL Control 3 */
108 0x2EE0, /* R63 - FLL Control 4 */
109 0x0002, /* R64 - FLL Control 5 */
110 0x2287, /* R65 - Clocking 3 */
111 0x025F, /* R66 - Clocking 4 */
112 0x0000, /* R67 - MW Slave Control */
113 0x0000, /* R68 */
114 0x0002, /* R69 - Bus Control 1 */
115 0x0000, /* R70 - Write Sequencer 0 */
116 0x0000, /* R71 - Write Sequencer 1 */
117 0x0000, /* R72 - Write Sequencer 2 */
118 0x0000, /* R73 - Write Sequencer 3 */
119 0x0000, /* R74 - Write Sequencer 4 */
120 0x0000, /* R75 - Write Sequencer 5 */
121 0x1F25, /* R76 - Charge Pump 1 */
122 0x0000, /* R77 */
123 0x0000, /* R78 */
124 0x0000, /* R79 */
125 0x0000, /* R80 */
126 0x0000, /* R81 - Class W 0 */
127 0x0000, /* R82 */
128 0x0000, /* R83 */
129 0x0000, /* R84 - DC Servo 0 */
130 0x054A, /* R85 - DC Servo 1 */
131 0x0000, /* R86 */
132 0x0000, /* R87 - DC Servo 3 */
133 0x0000, /* R88 - DC Servo Readback 0 */
134 0x0000, /* R89 - DC Servo Readback 1 */
135 0x0000, /* R90 - DC Servo Readback 2 */
136 0x0000, /* R91 */
137 0x0000, /* R92 */
138 0x0000, /* R93 */
139 0x0000, /* R94 */
140 0x0000, /* R95 */
141 0x0100, /* R96 - Analogue HP 0 */
142 0x0000, /* R97 */
143 0x0000, /* R98 - EQ1 */
144 0x000C, /* R99 - EQ2 */
145 0x000C, /* R100 - EQ3 */
146 0x000C, /* R101 - EQ4 */
147 0x000C, /* R102 - EQ5 */
148 0x000C, /* R103 - EQ6 */
149 0x0FCA, /* R104 - EQ7 */
150 0x0400, /* R105 - EQ8 */
151 0x00D8, /* R106 - EQ9 */
152 0x1EB5, /* R107 - EQ10 */
153 0xF145, /* R108 - EQ11 */
154 0x0B75, /* R109 - EQ12 */
155 0x01C5, /* R110 - EQ13 */
156 0x1C58, /* R111 - EQ14 */
157 0xF373, /* R112 - EQ15 */
158 0x0A54, /* R113 - EQ16 */
159 0x0558, /* R114 - EQ17 */
160 0x168E, /* R115 - EQ18 */
161 0xF829, /* R116 - EQ19 */
162 0x07AD, /* R117 - EQ20 */
163 0x1103, /* R118 - EQ21 */
164 0x0564, /* R119 - EQ22 */
165 0x0559, /* R120 - EQ23 */
166 0x4000, /* R121 - EQ24 */
167 0x0000, /* R122 - Digital Pulls */
168 0x0F08, /* R123 - DRC Control 1 */
169 0x0000, /* R124 - DRC Control 2 */
170 0x0080, /* R125 - DRC Control 3 */
171 0x0000, /* R126 - DRC Control 4 */
172};
173
174static struct {
175 int ratio;
176 int clk_sys_rate;
177} clk_sys_rates[] = {
178 { 64, 0 },
179 { 128, 1 },
180 { 192, 2 },
181 { 256, 3 },
182 { 384, 4 },
183 { 512, 5 },
184 { 768, 6 },
185 { 1024, 7 },
186 { 1408, 8 },
187 { 1536, 9 },
188};
189
190static struct {
191 int rate;
192 int sample_rate;
193} sample_rates[] = {
194 { 8000, 0 },
195 { 11025, 1 },
196 { 12000, 1 },
197 { 16000, 2 },
198 { 22050, 3 },
199 { 24000, 3 },
200 { 32000, 4 },
201 { 44100, 5 },
202 { 48000, 5 },
203};
204
205static struct {
206 int div; /* *10 due to .5s */
207 int bclk_div;
208} bclk_divs[] = {
209 { 10, 0 },
210 { 15, 1 },
211 { 20, 2 },
212 { 30, 3 },
213 { 40, 4 },
214 { 55, 5 },
215 { 60, 6 },
216 { 80, 7 },
217 { 110, 8 },
218 { 120, 9 },
219 { 160, 10 },
220 { 220, 11 },
221 { 240, 12 },
222 { 320, 13 },
223 { 440, 14 },
224 { 480, 15 },
225};
226
227struct wm8993_priv {
3ed7074c 228 struct wm_hubs_data hubs_data;
942c435b 229 u16 reg_cache[WM8993_REGISTER_COUNT];
b37e399b 230 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
942c435b 231 struct wm8993_platform_data pdata;
f0fba2ad 232 enum snd_soc_control_type control_type;
942c435b
MB		 233 int master;
234 int sysclk_source;
d3c9e9a1
MB		 235 int tdm_slots;
236 int tdm_width;
942c435b
MB		 237 unsigned int mclk_rate;
238 unsigned int sysclk_rate;
239 unsigned int fs;
240 unsigned int bclk;
241 int class_w_users;
242 unsigned int fll_fref;
243 unsigned int fll_fout;
53242c68 244 int fll_src;
942c435b
MB		 245};
246
942c435b
MB		 247static int wm8993_volatile(unsigned int reg)
248{
249 switch (reg) {
250 case WM8993_SOFTWARE_RESET:
251 case WM8993_DC_SERVO_0:
252 case WM8993_DC_SERVO_READBACK_0:
253 case WM8993_DC_SERVO_READBACK_1:
254 case WM8993_DC_SERVO_READBACK_2:
255 return 1;
256 default:
257 return 0;
258 }
259}
260
942c435b
MB		 261struct _fll_div {
262 u16 fll_fratio;
263 u16 fll_outdiv;
264 u16 fll_clk_ref_div;
265 u16 n;
266 u16 k;
267};
268
269/* The size in bits of the FLL divide multiplied by 10
270 * to allow rounding later */
271#define FIXED_FLL_SIZE ((1 << 16) * 10)
272
273static struct {
274 unsigned int min;
275 unsigned int max;
276 u16 fll_fratio;
277 int ratio;
278} fll_fratios[] = {
279 { 0, 64000, 4, 16 },
280 { 64000, 128000, 3, 8 },
281 { 128000, 256000, 2, 4 },
282 { 256000, 1000000, 1, 2 },
283 { 1000000, 13500000, 0, 1 },
284};
285
286static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
287 unsigned int Fout)
288{
289 u64 Kpart;
290 unsigned int K, Ndiv, Nmod, target;
291 unsigned int div;
292 int i;
293
294 /* Fref must be <=13.5MHz */
295 div = 1;
0c11f655 296 fll_div->fll_clk_ref_div = 0;
942c435b
MB		 297 while ((Fref / div) > 13500000) {
298 div *= 2;
0c11f655 299 fll_div->fll_clk_ref_div++;
942c435b
MB		 300
301 if (div > 8) {
302 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
303 Fref);
304 return -EINVAL;
305 }
306 }
307
308 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
309
310 /* Apply the division for our remaining calculations */
311 Fref /= div;
312
313 /* Fvco should be 90-100MHz; don't check the upper bound */
314 div = 0;
315 target = Fout * 2;
316 while (target < 90000000) {
317 div++;
318 target *= 2;
319 if (div > 7) {
320 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
321 Fout);
322 return -EINVAL;
323 }
324 }
325 fll_div->fll_outdiv = div;
326
327 pr_debug("Fvco=%dHz\n", target);
328
329 /* Find an appropraite FLL_FRATIO and factor it out of the target */
330 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
331 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
332 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
333 target /= fll_fratios[i].ratio;
334 break;
335 }
336 }
337 if (i == ARRAY_SIZE(fll_fratios)) {
338 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
339 return -EINVAL;
340 }
341
342 /* Now, calculate N.K */
343 Ndiv = target / Fref;
344
345 fll_div->n = Ndiv;
346 Nmod = target % Fref;
347 pr_debug("Nmod=%d\n", Nmod);
348
349 /* Calculate fractional part - scale up so we can round. */
350 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
351
352 do_div(Kpart, Fref);
353
354 K = Kpart & 0xFFFFFFFF;
355
356 if ((K % 10) >= 5)
357 K += 5;
358
359 /* Move down to proper range now rounding is done */
360 fll_div->k = K / 10;
361
362 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
363 fll_div->n, fll_div->k,
364 fll_div->fll_fratio, fll_div->fll_outdiv,
365 fll_div->fll_clk_ref_div);
366
367 return 0;
368}
369
f0fba2ad 370static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
942c435b
MB		 371 unsigned int Fref, unsigned int Fout)
372{
b2c812e2 373 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
942c435b
MB		 374 u16 reg1, reg4, reg5;
375 struct _fll_div fll_div;
376 int ret;
377
378 /* Any change? */
379 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
380 return 0;
381
382 /* Disable the FLL */
383 if (Fout == 0) {
384 dev_dbg(codec->dev, "FLL disabled\n");
385 wm8993->fll_fref = 0;
386 wm8993->fll_fout = 0;
387
3bf6e421 388 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
942c435b 389 reg1 &= ~WM8993_FLL_ENA;
3bf6e421 390 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
942c435b
MB		 391
392 return 0;
393 }
394
395 ret = fll_factors(&fll_div, Fref, Fout);
396 if (ret != 0)
397 return ret;
398
3bf6e421 399 reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5);
942c435b
MB		 400 reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
401
402 switch (fll_id) {
403 case WM8993_FLL_MCLK:
404 break;
405
406 case WM8993_FLL_LRCLK:
407 reg5 |= 1;
408 break;
409
410 case WM8993_FLL_BCLK:
411 reg5 |= 2;
412 break;
413
414 default:
415 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
416 return -EINVAL;
417 }
418
419 /* Any FLL configuration change requires that the FLL be
420 * disabled first. */
3bf6e421 421 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
942c435b 422 reg1 &= ~WM8993_FLL_ENA;
3bf6e421 423 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
942c435b
MB		 424
425 /* Apply the configuration */
426 if (fll_div.k)
427 reg1 |= WM8993_FLL_FRAC_MASK;
428 else
429 reg1 &= ~WM8993_FLL_FRAC_MASK;
3bf6e421 430 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
942c435b 431
3bf6e421
MB		 432 snd_soc_write(codec, WM8993_FLL_CONTROL_2,
433 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
434 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
435 snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
942c435b 436
3bf6e421 437 reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4);
942c435b
MB		 438 reg4 &= ~WM8993_FLL_N_MASK;
439 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
3bf6e421 440 snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4);
942c435b
MB		 441
442 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
443 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
3bf6e421 444 snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5);
942c435b
MB		 445
446 /* Enable the FLL */
3bf6e421 447 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
942c435b
MB		 448
449 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
450
451 wm8993->fll_fref = Fref;
452 wm8993->fll_fout = Fout;
53242c68 453 wm8993->fll_src = source;
942c435b
MB		 454
455 return 0;
456}
457
f0fba2ad
LG		 458static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
459 unsigned int Fref, unsigned int Fout)
460{
461 return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout);
462}
463
942c435b
MB		 464static int configure_clock(struct snd_soc_codec *codec)
465{
b2c812e2 466 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
942c435b
MB		 467 unsigned int reg;
468
469 /* This should be done on init() for bypass paths */
470 switch (wm8993->sysclk_source) {
471 case WM8993_SYSCLK_MCLK:
472 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
473
3bf6e421 474 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
0182dcc5 475 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
942c435b
MB		 476 if (wm8993->mclk_rate > 13500000) {
477 reg |= WM8993_MCLK_DIV;
478 wm8993->sysclk_rate = wm8993->mclk_rate / 2;
479 } else {
480 reg &= ~WM8993_MCLK_DIV;
481 wm8993->sysclk_rate = wm8993->mclk_rate;
482 }
3bf6e421 483 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
942c435b
MB		 484 break;
485
486 case WM8993_SYSCLK_FLL:
487 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
488 wm8993->fll_fout);
489
3bf6e421 490 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
942c435b
MB		 491 reg |= WM8993_SYSCLK_SRC;
492 if (wm8993->fll_fout > 13500000) {
493 reg |= WM8993_MCLK_DIV;
494 wm8993->sysclk_rate = wm8993->fll_fout / 2;
495 } else {
496 reg &= ~WM8993_MCLK_DIV;
497 wm8993->sysclk_rate = wm8993->fll_fout;
498 }
3bf6e421 499 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
942c435b
MB		 500 break;
501
502 default:
503 dev_err(codec->dev, "System clock not configured\n");
504 return -EINVAL;
505 }
506
507 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
508
509 return 0;
510}
511
942c435b
MB		 512static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
513static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
514static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
515static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
516static const unsigned int drc_max_tlv[] = {
517 TLV_DB_RANGE_HEAD(4),
518 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
519 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
520};
521static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
522static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
523static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
524static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
525static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
942c435b
MB		 526
527static const char *dac_deemph_text[] = {
528 "None",
529 "32kHz",
530 "44.1kHz",
531 "48kHz",
532};
533
534static const struct soc_enum dac_deemph =
535 SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
536
537static const char *adc_hpf_text[] = {
538 "Hi-Fi",
539 "Voice 1",
540 "Voice 2",
541 "Voice 3",
542};
543
544static const struct soc_enum adc_hpf =
545 SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
546
547static const char *drc_path_text[] = {
548 "ADC",
549 "DAC"
550};
551
552static const struct soc_enum drc_path =
553 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
554
555static const char *drc_r0_text[] = {
556 "1",
557 "1/2",
558 "1/4",
559 "1/8",
560 "1/16",
561 "0",
562};
563
564static const struct soc_enum drc_r0 =
565 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
566
567static const char *drc_r1_text[] = {
568 "1",
569 "1/2",
570 "1/4",
571 "1/8",
572 "0",
573};
574
575static const struct soc_enum drc_r1 =
576 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
577
578static const char *drc_attack_text[] = {
579 "Reserved",
580 "181us",
581 "363us",
582 "726us",
583 "1.45ms",
584 "2.9ms",
585 "5.8ms",
586 "11.6ms",
587 "23.2ms",
588 "46.4ms",
589 "92.8ms",
590 "185.6ms",
591};
592
593static const struct soc_enum drc_attack =
594 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
595
596static const char *drc_decay_text[] = {
597 "186ms",
598 "372ms",
599 "743ms",
600 "1.49s",
601 "2.97ms",
602 "5.94ms",
603 "11.89ms",
604 "23.78ms",
605 "47.56ms",
606};
607
608static const struct soc_enum drc_decay =
609 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
610
611static const char *drc_ff_text[] = {
612 "5 samples",
613 "9 samples",
614};
615
616static const struct soc_enum drc_ff =
617 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
618
619static const char *drc_qr_rate_text[] = {
620 "0.725ms",
621 "1.45ms",
622 "5.8ms",
623};
624
625static const struct soc_enum drc_qr_rate =
626 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
627
628static const char *drc_smooth_text[] = {
629 "Low",
630 "Medium",
631 "High",
632};
633
634static const struct soc_enum drc_smooth =
635 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
636
942c435b 637static const struct snd_kcontrol_new wm8993_snd_controls[] = {
942c435b
MB		 638SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
639 5, 9, 12, 0, sidetone_tlv),
640
641SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
642SOC_ENUM("DRC Path", drc_path),
af901ca1 643SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
942c435b
MB		 644 2, 60, 1, drc_comp_threash),
645SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
646 11, 30, 1, drc_comp_amp),
647SOC_ENUM("DRC R0", drc_r0),
648SOC_ENUM("DRC R1", drc_r1),
649SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
650 drc_min_tlv),
651SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
652 drc_max_tlv),
653SOC_ENUM("DRC Attack Rate", drc_attack),
654SOC_ENUM("DRC Decay Rate", drc_decay),
655SOC_ENUM("DRC FF Delay", drc_ff),
656SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
657SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
658SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
659 drc_qr_tlv),
660SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
661SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
662SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
af901ca1 663SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
942c435b
MB		 664SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
665 drc_startup_tlv),
666
667SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
668
669SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
670 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
671SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
672SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
673
674SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
675 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
676SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
677 dac_boost_tlv),
678SOC_ENUM("DAC Deemphasis", dac_deemph),
679
942c435b 680SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
a2342ae3 681 2, 1, 1, wm_hubs_spkmix_tlv),
942c435b 682
a2342ae3
MB		 683SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
684 2, 1, 1, wm_hubs_spkmix_tlv),
942c435b
MB		 685};
686
687static const struct snd_kcontrol_new wm8993_eq_controls[] = {
688SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
689SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
690SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
691SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
692SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
693};
694
942c435b
MB		 695static int clk_sys_event(struct snd_soc_dapm_widget *w,
696 struct snd_kcontrol *kcontrol, int event)
697{
698 struct snd_soc_codec *codec = w->codec;
699
700 switch (event) {
701 case SND_SOC_DAPM_PRE_PMU:
702 return configure_clock(codec);
703
704 case SND_SOC_DAPM_POST_PMD:
705 break;
706 }
707
708 return 0;
709}
710
711/*
712 * When used with DAC outputs only the WM8993 charge pump supports
713 * operation in class W mode, providing very low power consumption
714 * when used with digital sources. Enable and disable this mode
715 * automatically depending on the mixer configuration.
716 *
717 * Currently the only supported paths are the direct DAC->headphone
718 * paths (which provide minimum power consumption anyway).
719 */
a2342ae3
MB		 720static int class_w_put(struct snd_kcontrol *kcontrol,
721 struct snd_ctl_elem_value *ucontrol)
942c435b
MB		 722{
723 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
724 struct snd_soc_codec *codec = widget->codec;
b2c812e2 725 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
942c435b
MB		 726 int ret;
727
728 /* Turn it off if we're using the main output mixer */
729 if (ucontrol->value.integer.value[0] == 0) {
730 if (wm8993->class_w_users == 0) {
731 dev_dbg(codec->dev, "Disabling Class W\n");
732 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
733 WM8993_CP_DYN_FREQ |
734 WM8993_CP_DYN_V,
735 0);
736 }
737 wm8993->class_w_users++;
fec6dd83 738 wm8993->hubs_data.class_w = true;
942c435b
MB		 739 }
740
741 /* Implement the change */
742 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
743
744 /* Enable it if we're using the direct DAC path */
745 if (ucontrol->value.integer.value[0] == 1) {
746 if (wm8993->class_w_users == 1) {
747 dev_dbg(codec->dev, "Enabling Class W\n");
748 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
749 WM8993_CP_DYN_FREQ |
750 WM8993_CP_DYN_V,
751 WM8993_CP_DYN_FREQ |
752 WM8993_CP_DYN_V);
753 }
754 wm8993->class_w_users--;
fec6dd83 755 wm8993->hubs_data.class_w = false;
942c435b
MB		 756 }
757
758 dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
759 wm8993->class_w_users);
760
761 return ret;
762}
763
764#define SOC_DAPM_ENUM_W(xname, xenum) \
765{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
766 .info = snd_soc_info_enum_double, \
767 .get = snd_soc_dapm_get_enum_double, \
a2342ae3 768 .put = class_w_put, \
942c435b
MB		 769 .private_value = (unsigned long)&xenum }
770
942c435b
MB		 771static const char *hp_mux_text[] = {
772 "Mixer",
773 "DAC",
774};
775
776static const struct soc_enum hpl_enum =
777 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
778
779static const struct snd_kcontrol_new hpl_mux =
780 SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
781
782static const struct soc_enum hpr_enum =
783 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
784
785static const struct snd_kcontrol_new hpr_mux =
786 SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
787
a2342ae3
MB		 788static const struct snd_kcontrol_new left_speaker_mixer[] = {
789SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
790SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
791SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
792SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
942c435b
MB		 793};
794
a2342ae3
MB		 795static const struct snd_kcontrol_new right_speaker_mixer[] = {
796SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
797SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
798SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
799SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
942c435b
MB		 800};
801
59ae07a5
MB		 802static const char *aif_text[] = {
803 "Left", "Right"
804};
805
806static const struct soc_enum aifoutl_enum =
807 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text);
808
809static const struct snd_kcontrol_new aifoutl_mux =
810 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
811
812static const struct soc_enum aifoutr_enum =
813 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text);
814
815static const struct snd_kcontrol_new aifoutr_mux =
816 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
817
818static const struct soc_enum aifinl_enum =
819 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text);
820
821static const struct snd_kcontrol_new aifinl_mux =
822 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
823
824static const struct soc_enum aifinr_enum =
825 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text);
826
827static const struct snd_kcontrol_new aifinr_mux =
828 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
829
830static const char *sidetone_text[] = {
831 "None", "Left", "Right"
832};
833
834static const struct soc_enum sidetonel_enum =
835 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text);
836
837static const struct snd_kcontrol_new sidetonel_mux =
838 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
839
840static const struct soc_enum sidetoner_enum =
841 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text);
842
843static const struct snd_kcontrol_new sidetoner_mux =
844 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
845
942c435b 846static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
942c435b
MB		 847SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
848 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
849SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
850SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
851
59ae07a5
MB		 852SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
853SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
854
855SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
856SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
857
858SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
859SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
942c435b 860
59ae07a5
MB		 861SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
862SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
942c435b 863
59ae07a5
MB		 864SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
865SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
866
867SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
868SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
869
870SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
871SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
942c435b 872
a2342ae3
MB		 873SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
874SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
942c435b
MB		 875
876SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
877 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
878SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
879 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
880
942c435b
MB		 881};
882
883static const struct snd_soc_dapm_route routes[] = {
942c435b
MB		 884 { "ADCL", NULL, "CLK_SYS" },
885 { "ADCL", NULL, "CLK_DSP" },
942c435b
MB		 886 { "ADCR", NULL, "CLK_SYS" },
887 { "ADCR", NULL, "CLK_DSP" },
888
59ae07a5
MB		 889 { "AIFOUTL Mux", "Left", "ADCL" },
890 { "AIFOUTL Mux", "Right", "ADCR" },
891 { "AIFOUTR Mux", "Left", "ADCL" },
892 { "AIFOUTR Mux", "Right", "ADCR" },
893
894 { "AIFOUTL", NULL, "AIFOUTL Mux" },
895 { "AIFOUTR", NULL, "AIFOUTR Mux" },
896
897 { "DACL Mux", "Left", "AIFINL" },
898 { "DACL Mux", "Right", "AIFINR" },
899 { "DACR Mux", "Left", "AIFINL" },
900 { "DACR Mux", "Right", "AIFINR" },
901
902 { "DACL Sidetone", "Left", "ADCL" },
903 { "DACL Sidetone", "Right", "ADCR" },
904 { "DACR Sidetone", "Left", "ADCL" },
905 { "DACR Sidetone", "Right", "ADCR" },
906
942c435b
MB		 907 { "DACL", NULL, "CLK_SYS" },
908 { "DACL", NULL, "CLK_DSP" },
59ae07a5
MB		 909 { "DACL", NULL, "DACL Mux" },
910 { "DACL", NULL, "DACL Sidetone" },
942c435b
MB		 911 { "DACR", NULL, "CLK_SYS" },
912 { "DACR", NULL, "CLK_DSP" },
59ae07a5
MB		 913 { "DACR", NULL, "DACR Mux" },
914 { "DACR", NULL, "DACR Sidetone" },
942c435b 915
942c435b
MB		 916 { "Left Output Mixer", "DAC Switch", "DACL" },
917
942c435b
MB		 918 { "Right Output Mixer", "DAC Switch", "DACR" },
919
942c435b 920 { "Left Output PGA", NULL, "CLK_SYS" },
942c435b 921
942c435b 922 { "Right Output PGA", NULL, "CLK_SYS" },
942c435b 923
942c435b
MB		 924 { "SPKL", "DAC Switch", "DACL" },
925 { "SPKL", NULL, "CLK_SYS" },
942c435b 926
942c435b
MB		 927 { "SPKR", "DAC Switch", "DACR" },
928 { "SPKR", NULL, "CLK_SYS" },
942c435b
MB		 929
930 { "Left Headphone Mux", "DAC", "DACL" },
942c435b 931 { "Right Headphone Mux", "DAC", "DACR" },
942c435b
MB		 932};
933
cf56f627
MB		 934static void wm8993_cache_restore(struct snd_soc_codec *codec)
935{
936 u16 *cache = codec->reg_cache;
937 int i;
938
939 if (!codec->cache_sync)
940 return;
941
942 /* Reenable hardware writes */
943 codec->cache_only = 0;
944
945 /* Restore the register settings */
946 for (i = 1; i < WM8993_MAX_REGISTER; i++) {
947 if (cache[i] == wm8993_reg_defaults[i])
948 continue;
949 snd_soc_write(codec, i, cache[i]);
950 }
951
952 /* We're in sync again */
953 codec->cache_sync = 0;
954}
955
942c435b
MB		 956static int wm8993_set_bias_level(struct snd_soc_codec *codec,
957 enum snd_soc_bias_level level)
958{
b2c812e2 959 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
cf56f627 960 int ret;
942c435b
MB		 961
962 switch (level) {
963 case SND_SOC_BIAS_ON:
964 case SND_SOC_BIAS_PREPARE:
965 /* VMID=2*40k */
966 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
967 WM8993_VMID_SEL_MASK, 0x2);
968 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
969 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
970 break;
971
972 case SND_SOC_BIAS_STANDBY:
973 if (codec->bias_level == SND_SOC_BIAS_OFF) {
cf56f627
MB		 974 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
975 wm8993->supplies);
976 if (ret != 0)
977 return ret;
978
979 wm8993_cache_restore(codec);
980
3ed7074c
MB		 981 /* Tune DC servo configuration */
982 snd_soc_write(codec, 0x44, 3);
983 snd_soc_write(codec, 0x56, 3);
984 snd_soc_write(codec, 0x44, 0);
985
942c435b
MB		 986 /* Bring up VMID with fast soft start */
987 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
988 WM8993_STARTUP_BIAS_ENA |
989 WM8993_VMID_BUF_ENA |
990 WM8993_VMID_RAMP_MASK |
991 WM8993_BIAS_SRC,
992 WM8993_STARTUP_BIAS_ENA |
993 WM8993_VMID_BUF_ENA |
994 WM8993_VMID_RAMP_MASK |
995 WM8993_BIAS_SRC);
996
997 /* If either line output is single ended we
998 * need the VMID buffer */
999 if (!wm8993->pdata.lineout1_diff ||
1000 !wm8993->pdata.lineout2_diff)
1001 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1002 WM8993_LINEOUT_VMID_BUF_ENA,
1003 WM8993_LINEOUT_VMID_BUF_ENA);
1004
1005 /* VMID=2*40k */
1006 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1007 WM8993_VMID_SEL_MASK |
1008 WM8993_BIAS_ENA,
1009 WM8993_BIAS_ENA | 0x2);
1010 msleep(32);
1011
1012 /* Switch to normal bias */
1013 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1014 WM8993_BIAS_SRC |
1015 WM8993_STARTUP_BIAS_ENA, 0);
1016 }
1017
1018 /* VMID=2*240k */
1019 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1020 WM8993_VMID_SEL_MASK, 0x4);
1021
1022 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1023 WM8993_TSHUT_ENA, 0);
1024 break;
1025
1026 case SND_SOC_BIAS_OFF:
1027 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1028 WM8993_LINEOUT_VMID_BUF_ENA, 0);
1029
1030 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1031 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1032 0);
cf56f627
MB		 1033
1034#ifdef CONFIG_REGULATOR
1035 /* Post 2.6.34 we will be able to get a callback when
1036 * the regulators are disabled which we can use but
1037 * for now just assume that the power will be cut if
1038 * the regulator API is in use.
1039 */
1040 codec->cache_sync = 1;
1041#endif
1042
1043 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
1044 wm8993->supplies);
942c435b
MB		 1045 break;
1046 }
1047
1048 codec->bias_level = level;
1049
1050 return 0;
1051}
1052
1053static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1054 int clk_id, unsigned int freq, int dir)
1055{
1056 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1057 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
942c435b
MB		 1058
1059 switch (clk_id) {
1060 case WM8993_SYSCLK_MCLK:
1061 wm8993->mclk_rate = freq;
1062 case WM8993_SYSCLK_FLL:
1063 wm8993->sysclk_source = clk_id;
1064 break;
1065
1066 default:
1067 return -EINVAL;
1068 }
1069
1070 return 0;
1071}
1072
1073static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1074 unsigned int fmt)
1075{
1076 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1077 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
3bf6e421
MB		 1078 unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1079 unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
942c435b
MB		 1080
1081 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1082 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1083 aif4 &= ~WM8993_LRCLK_DIR;
1084
1085 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1086 case SND_SOC_DAIFMT_CBS_CFS:
1087 wm8993->master = 0;
1088 break;
1089 case SND_SOC_DAIFMT_CBS_CFM:
1090 aif4 |= WM8993_LRCLK_DIR;
1091 wm8993->master = 1;
1092 break;
1093 case SND_SOC_DAIFMT_CBM_CFS:
1094 aif1 |= WM8993_BCLK_DIR;
1095 wm8993->master = 1;
1096 break;
1097 case SND_SOC_DAIFMT_CBM_CFM:
1098 aif1 |= WM8993_BCLK_DIR;
1099 aif4 |= WM8993_LRCLK_DIR;
1100 wm8993->master = 1;
1101 break;
1102 default:
1103 return -EINVAL;
1104 }
1105
1106 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1107 case SND_SOC_DAIFMT_DSP_B:
1108 aif1 |= WM8993_AIF_LRCLK_INV;
1109 case SND_SOC_DAIFMT_DSP_A:
1110 aif1 |= 0x18;
1111 break;
1112 case SND_SOC_DAIFMT_I2S:
1113 aif1 |= 0x10;
1114 break;
1115 case SND_SOC_DAIFMT_RIGHT_J:
1116 break;
1117 case SND_SOC_DAIFMT_LEFT_J:
1118 aif1 |= 0x8;
1119 break;
1120 default:
1121 return -EINVAL;
1122 }
1123
1124 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1125 case SND_SOC_DAIFMT_DSP_A:
1126 case SND_SOC_DAIFMT_DSP_B:
1127 /* frame inversion not valid for DSP modes */
1128 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1129 case SND_SOC_DAIFMT_NB_NF:
1130 break;
1131 case SND_SOC_DAIFMT_IB_NF:
1132 aif1 |= WM8993_AIF_BCLK_INV;
1133 break;
1134 default:
1135 return -EINVAL;
1136 }
1137 break;
1138
1139 case SND_SOC_DAIFMT_I2S:
1140 case SND_SOC_DAIFMT_RIGHT_J:
1141 case SND_SOC_DAIFMT_LEFT_J:
1142 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1143 case SND_SOC_DAIFMT_NB_NF:
1144 break;
1145 case SND_SOC_DAIFMT_IB_IF:
1146 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1147 break;
1148 case SND_SOC_DAIFMT_IB_NF:
1149 aif1 |= WM8993_AIF_BCLK_INV;
1150 break;
1151 case SND_SOC_DAIFMT_NB_IF:
1152 aif1 |= WM8993_AIF_LRCLK_INV;
1153 break;
1154 default:
1155 return -EINVAL;
1156 }
1157 break;
1158 default:
1159 return -EINVAL;
1160 }
1161
3bf6e421
MB		 1162 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1163 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
942c435b
MB		 1164
1165 return 0;
1166}
1167
1168static int wm8993_hw_params(struct snd_pcm_substream *substream,
1169 struct snd_pcm_hw_params *params,
1170 struct snd_soc_dai *dai)
1171{
1172 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1173 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
942c435b
MB		 1174 int ret, i, best, best_val, cur_val;
1175 unsigned int clocking1, clocking3, aif1, aif4;
1176
3bf6e421 1177 clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1);
942c435b
MB		 1178 clocking1 &= ~WM8993_BCLK_DIV_MASK;
1179
3bf6e421 1180 clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3);
942c435b
MB		 1181 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1182
3bf6e421 1183 aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
942c435b
MB		 1184 aif1 &= ~WM8993_AIF_WL_MASK;
1185
3bf6e421 1186 aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
942c435b
MB		 1187 aif4 &= ~WM8993_LRCLK_RATE_MASK;
1188
1189 /* What BCLK do we need? */
1190 wm8993->fs = params_rate(params);
1191 wm8993->bclk = 2 * wm8993->fs;
d3c9e9a1
MB		 1192 if (wm8993->tdm_slots) {
1193 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1194 wm8993->tdm_slots, wm8993->tdm_width);
1195 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1196 } else {
1197 switch (params_format(params)) {
1198 case SNDRV_PCM_FORMAT_S16_LE:
1199 wm8993->bclk *= 16;
1200 break;
1201 case SNDRV_PCM_FORMAT_S20_3LE:
1202 wm8993->bclk *= 20;
1203 aif1 |= 0x8;
1204 break;
1205 case SNDRV_PCM_FORMAT_S24_LE:
1206 wm8993->bclk *= 24;
1207 aif1 |= 0x10;
1208 break;
1209 case SNDRV_PCM_FORMAT_S32_LE:
1210 wm8993->bclk *= 32;
1211 aif1 |= 0x18;
1212 break;
1213 default:
1214 return -EINVAL;
1215 }
942c435b
MB		 1216 }
1217
1218 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1219
1220 ret = configure_clock(codec);
1221 if (ret != 0)
1222 return ret;
1223
1224 /* Select nearest CLK_SYS_RATE */
1225 best = 0;
1226 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1227 - wm8993->fs);
1228 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1229 cur_val = abs((wm8993->sysclk_rate /
1230 clk_sys_rates[i].ratio) - wm8993->fs);;
1231 if (cur_val < best_val) {
1232 best = i;
1233 best_val = cur_val;
1234 }
1235 }
1236 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1237 clk_sys_rates[best].ratio);
1238 clocking3 |= (clk_sys_rates[best].clk_sys_rate
1239 << WM8993_CLK_SYS_RATE_SHIFT);
1240
1241 /* SAMPLE_RATE */
1242 best = 0;
1243 best_val = abs(wm8993->fs - sample_rates[0].rate);
1244 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1245 /* Closest match */
1246 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1247 if (cur_val < best_val) {
1248 best = i;
1249 best_val = cur_val;
1250 }
1251 }
1252 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1253 sample_rates[best].rate);
e465d544
MB		 1254 clocking3 |= (sample_rates[best].sample_rate
1255 << WM8993_SAMPLE_RATE_SHIFT);
942c435b
MB		 1256
1257 /* BCLK_DIV */
1258 best = 0;
1259 best_val = INT_MAX;
1260 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1261 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1262 - wm8993->bclk;
1263 if (cur_val < 0) /* Table is sorted */
1264 break;
1265 if (cur_val < best_val) {
1266 best = i;
1267 best_val = cur_val;
1268 }
1269 }
1270 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1271 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1272 bclk_divs[best].div, wm8993->bclk);
1273 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1274
1275 /* LRCLK is a simple fraction of BCLK */
1276 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1277 aif4 |= wm8993->bclk / wm8993->fs;
1278
3bf6e421
MB		 1279 snd_soc_write(codec, WM8993_CLOCKING_1, clocking1);
1280 snd_soc_write(codec, WM8993_CLOCKING_3, clocking3);
1281 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1282 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
942c435b
MB		 1283
1284 /* ReTune Mobile? */
1285 if (wm8993->pdata.num_retune_configs) {
3bf6e421 1286 u16 eq1 = snd_soc_read(codec, WM8993_EQ1);
942c435b
MB		 1287 struct wm8993_retune_mobile_setting *s;
1288
1289 best = 0;
1290 best_val = abs(wm8993->pdata.retune_configs[0].rate
1291 - wm8993->fs);
1292 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1293 cur_val = abs(wm8993->pdata.retune_configs[i].rate
1294 - wm8993->fs);
1295 if (cur_val < best_val) {
1296 best_val = cur_val;
1297 best = i;
1298 }
1299 }
1300 s = &wm8993->pdata.retune_configs[best];
1301
1302 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1303 s->name, s->rate);
1304
1305 /* Disable EQ while we reconfigure */
1306 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1307
1308 for (i = 1; i < ARRAY_SIZE(s->config); i++)
3bf6e421 1309 snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]);
942c435b
MB		 1310
1311 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1312 }
1313
1314 return 0;
1315}
1316
1317static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1318{
1319 struct snd_soc_codec *codec = codec_dai->codec;
1320 unsigned int reg;
1321
3bf6e421 1322 reg = snd_soc_read(codec, WM8993_DAC_CTRL);
942c435b
MB		 1323
1324 if (mute)
1325 reg |= WM8993_DAC_MUTE;
1326 else
1327 reg &= ~WM8993_DAC_MUTE;
1328
3bf6e421 1329 snd_soc_write(codec, WM8993_DAC_CTRL, reg);
942c435b
MB		 1330
1331 return 0;
1332}
1333
d3c9e9a1
MB		 1334static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1335 unsigned int rx_mask, int slots, int slot_width)
1336{
1337 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1338 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
d3c9e9a1
MB		 1339 int aif1 = 0;
1340 int aif2 = 0;
1341
1342 /* Don't need to validate anything if we're turning off TDM */
1343 if (slots == 0) {
1344 wm8993->tdm_slots = 0;
1345 goto out;
1346 }
1347
1348 /* Note that we allow configurations we can't handle ourselves -
1349 * for example, we can generate clocks for slots 2 and up even if
1350 * we can't use those slots ourselves.
1351 */
1352 aif1 |= WM8993_AIFADC_TDM;
1353 aif2 |= WM8993_AIFDAC_TDM;
1354
1355 switch (rx_mask) {
1356 case 3:
1357 break;
1358 case 0xc:
1359 aif1 |= WM8993_AIFADC_TDM_CHAN;
1360 break;
1361 default:
1362 return -EINVAL;
1363 }
1364
1365
1366 switch (tx_mask) {
1367 case 3:
1368 break;
1369 case 0xc:
1370 aif2 |= WM8993_AIFDAC_TDM_CHAN;
1371 break;
1372 default:
1373 return -EINVAL;
1374 }
1375
1376out:
1377 wm8993->tdm_width = slot_width;
1378 wm8993->tdm_slots = slots / 2;
1379
1380 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1,
1381 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1382 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2,
1383 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1384
1385 return 0;
1386}
1387
942c435b
MB		 1388static struct snd_soc_dai_ops wm8993_ops = {
1389 .set_sysclk = wm8993_set_sysclk,
1390 .set_fmt = wm8993_set_dai_fmt,
1391 .hw_params = wm8993_hw_params,
1392 .digital_mute = wm8993_digital_mute,
1393 .set_pll = wm8993_set_fll,
d3c9e9a1 1394 .set_tdm_slot = wm8993_set_tdm_slot,
942c435b
MB		 1395};
1396
1397#define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1398
1399#define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1400 SNDRV_PCM_FMTBIT_S20_3LE |\
1401 SNDRV_PCM_FMTBIT_S24_LE |\
1402 SNDRV_PCM_FMTBIT_S32_LE)
1403
f0fba2ad
LG		 1404static struct snd_soc_dai_driver wm8993_dai = {
1405 .name = "wm8993-hifi",
942c435b
MB		 1406 .playback = {
1407 .stream_name = "Playback",
1408 .channels_min = 1,
1409 .channels_max = 2,
1410 .rates = WM8993_RATES,
1411 .formats = WM8993_FORMATS,
1412 },
1413 .capture = {
1414 .stream_name = "Capture",
1415 .channels_min = 1,
1416 .channels_max = 2,
1417 .rates = WM8993_RATES,
1418 .formats = WM8993_FORMATS,
1419 },
1420 .ops = &wm8993_ops,
1421 .symmetric_rates = 1,
1422};
942c435b 1423
f0fba2ad 1424static int wm8993_probe(struct snd_soc_codec *codec)
942c435b 1425{
f0fba2ad
LG		 1426 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1427 int ret, i, val;
1428
f0fba2ad
LG		 1429 wm8993->hubs_data.hp_startup_mode = 1;
1430 wm8993->hubs_data.dcs_codes = -2;
1431
1432 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1433 if (ret != 0) {
1434 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1435 return ret;
1436 }
1437
1438 for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1439 wm8993->supplies[i].supply = wm8993_supply_names[i];
942c435b 1440
f0fba2ad
LG		 1441 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8993->supplies),
1442 wm8993->supplies);
1443 if (ret != 0) {
1444 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1445 return ret;
942c435b
MB		 1446 }
1447
f0fba2ad
LG		 1448 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1449 wm8993->supplies);
1450 if (ret != 0) {
1451 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1452 goto err_get;
1453 }
942c435b 1454
f0fba2ad
LG		 1455 val = snd_soc_read(codec, WM8993_SOFTWARE_RESET);
1456 if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
1457 dev_err(codec->dev, "Invalid ID register value %x\n", val);
1458 ret = -EINVAL;
1459 goto err_enable;
942c435b
MB		 1460 }
1461
f0fba2ad
LG		 1462 ret = snd_soc_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
1463 if (ret != 0)
1464 goto err_enable;
1465
1466 codec->cache_only = 1;
1467
1468 /* By default we're using the output mixers */
1469 wm8993->class_w_users = 2;
1470
1471 /* Latch volume update bits and default ZC on */
1472 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1473 WM8993_DAC_VU, WM8993_DAC_VU);
1474 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1475 WM8993_ADC_VU, WM8993_ADC_VU);
1476
1477 /* Manualy manage the HPOUT sequencing for independent stereo
1478 * control. */
1479 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
1480 WM8993_HPOUT1_AUTO_PU, 0);
1481
1482 /* Use automatic clock configuration */
1483 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1484
1485 wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
1486 wm8993->pdata.lineout2_diff,
1487 wm8993->pdata.lineout1fb,
1488 wm8993->pdata.lineout2fb,
1489 wm8993->pdata.jd_scthr,
1490 wm8993->pdata.jd_thr,
1491 wm8993->pdata.micbias1_lvl,
1492 wm8993->pdata.micbias2_lvl);
1493
1494 ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1495 if (ret != 0)
1496 goto err_enable;
1497
942c435b
MB		 1498 snd_soc_add_controls(codec, wm8993_snd_controls,
1499 ARRAY_SIZE(wm8993_snd_controls));
1500 if (wm8993->pdata.num_retune_configs != 0) {
1501 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1502 } else {
1503 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1504 snd_soc_add_controls(codec, wm8993_eq_controls,
1505 ARRAY_SIZE(wm8993_eq_controls));
1506 }
1507
1508 snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets,
1509 ARRAY_SIZE(wm8993_dapm_widgets));
a2342ae3 1510 wm_hubs_add_analogue_controls(codec);
942c435b
MB		 1511
1512 snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
a2342ae3
MB		 1513 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1514 wm8993->pdata.lineout2_diff);
942c435b 1515
f0fba2ad 1516 return 0;
942c435b 1517
f0fba2ad
LG		 1518err_enable:
1519 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1520err_get:
1521 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
942c435b
MB		 1522 return ret;
1523}
1524
f0fba2ad 1525static int wm8993_remove(struct snd_soc_codec *codec)
942c435b 1526{
f0fba2ad 1527 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
942c435b 1528
f0fba2ad
LG		 1529 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1530 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
942c435b
MB		 1531 return 0;
1532}
1533
53242c68 1534#ifdef CONFIG_PM
f0fba2ad 1535static int wm8993_suspend(struct snd_soc_codec *codec, pm_message_t state)
53242c68 1536{
b2c812e2 1537 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
53242c68
MB		 1538 int fll_fout = wm8993->fll_fout;
1539 int fll_fref = wm8993->fll_fref;
1540 int ret;
1541
1542 /* Stop the FLL in an orderly fashion */
f0fba2ad 1543 ret = _wm8993_set_fll(codec, 0, 0, 0, 0);
53242c68 1544 if (ret != 0) {
f0fba2ad 1545 dev_err(codec->dev, "Failed to stop FLL\n");
53242c68
MB		 1546 return ret;
1547 }
1548
1549 wm8993->fll_fout = fll_fout;
1550 wm8993->fll_fref = fll_fref;
1551
1552 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1553
1554 return 0;
1555}
1556
f0fba2ad 1557static int wm8993_resume(struct snd_soc_codec *codec)
53242c68 1558{
b2c812e2 1559 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
cf56f627 1560 int ret;
53242c68
MB		 1561
1562 wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1563
1564 /* Restart the FLL? */
1565 if (wm8993->fll_fout) {
1566 int fll_fout = wm8993->fll_fout;
1567 int fll_fref = wm8993->fll_fref;
1568
1569 wm8993->fll_fref = 0;
1570 wm8993->fll_fout = 0;
1571
f0fba2ad 1572 ret = _wm8993_set_fll(codec, 0, wm8993->fll_src,
53242c68
MB		 1573 fll_fref, fll_fout);
1574 if (ret != 0)
1575 dev_err(codec->dev, "Failed to restart FLL\n");
1576 }
1577
1578 return 0;
1579}
1580#else
1581#define wm8993_suspend NULL
1582#define wm8993_resume NULL
1583#endif
1584
f0fba2ad 1585static struct snd_soc_codec_driver soc_codec_dev_wm8993 = {
942c435b
MB		 1586 .probe = wm8993_probe,
1587 .remove = wm8993_remove,
53242c68
MB		 1588 .suspend = wm8993_suspend,
1589 .resume = wm8993_resume,
f0fba2ad 1590 .set_bias_level = wm8993_set_bias_level,
e5eec34c 1591 .reg_cache_size = ARRAY_SIZE(wm8993_reg_defaults),
f0fba2ad
LG		 1592 .reg_word_size = sizeof(u16),
1593 .reg_cache_default = wm8993_reg_defaults,
1594 .volatile_register = wm8993_volatile,
942c435b 1595};
942c435b 1596
f0fba2ad
LG		 1597#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1598static __devinit int wm8993_i2c_probe(struct i2c_client *i2c,
1599 const struct i2c_device_id *id)
942c435b
MB		 1600{
1601 struct wm8993_priv *wm8993;
942c435b 1602 int ret;
942c435b
MB		 1603
1604 wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL);
1605 if (wm8993 == NULL)
1606 return -ENOMEM;
1607
942c435b 1608 i2c_set_clientdata(i2c, wm8993);
942c435b 1609
f0fba2ad
LG		 1610 ret = snd_soc_register_codec(&i2c->dev,
1611 &soc_codec_dev_wm8993, &wm8993_dai, 1);
1612 if (ret < 0)
1613 kfree(wm8993);
942c435b
MB		 1614 return ret;
1615}
1616
f0fba2ad 1617static __devexit int wm8993_i2c_remove(struct i2c_client *client)
942c435b 1618{
f0fba2ad
LG		 1619 snd_soc_unregister_codec(&client->dev);
1620 kfree(i2c_get_clientdata(client));
942c435b
MB		 1621 return 0;
1622}
1623
1624static const struct i2c_device_id wm8993_i2c_id[] = {
1625 { "wm8993", 0 },
1626 { }
1627};
1628MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1629
1630static struct i2c_driver wm8993_i2c_driver = {
1631 .driver = {
f0fba2ad 1632 .name = "wm8993-codec",
942c435b
MB		 1633 .owner = THIS_MODULE,
1634 },
f0fba2ad
LG		 1635 .probe = wm8993_i2c_probe,
1636 .remove = __devexit_p(wm8993_i2c_remove),
942c435b
MB		 1637 .id_table = wm8993_i2c_id,
1638};
f0fba2ad 1639#endif
942c435b
MB		 1640
1641static int __init wm8993_modinit(void)
1642{
f0fba2ad
LG		 1643 int ret = 0;
1644#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
942c435b 1645 ret = i2c_add_driver(&wm8993_i2c_driver);
f0fba2ad
LG		 1646 if (ret != 0) {
1647 pr_err("WM8993: Unable to register I2C driver: %d\n",
1648 ret);
1649 }
1650#endif
942c435b
MB		 1651 return ret;
1652}
1653module_init(wm8993_modinit);
1654
1655static void __exit wm8993_exit(void)
1656{
f0fba2ad 1657#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
942c435b 1658 i2c_del_driver(&wm8993_i2c_driver);
f0fba2ad 1659#endif
942c435b
MB		 1660}
1661module_exit(wm8993_exit);
1662
1663
1664MODULE_DESCRIPTION("ASoC WM8993 driver");
1665MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1666MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)