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Merge tag 'v3.10.55' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8985.c
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6d6f8b83
DP		 1/*
2 * wm8985.c -- WM8985 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * o Add OUT3/OUT4 mixer controls.
14 */
15
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/pm.h>
21#include <linux/i2c.h>
411a3450 22#include <linux/regmap.h>
6d6f8b83
DP		 23#include <linux/regulator/consumer.h>
24#include <linux/spi/spi.h>
25#include <linux/slab.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
6d6f8b83
DP		 30#include <sound/initval.h>
31#include <sound/tlv.h>
32
33#include "wm8985.h"
34
35#define WM8985_NUM_SUPPLIES 4
36static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
37 "DCVDD",
38 "DBVDD",
39 "AVDD1",
40 "AVDD2"
41};
42
411a3450
MB		 43static const struct reg_default wm8985_reg_defaults[] = {
44 { 1, 0x0000 }, /* R1 - Power management 1 */
45 { 2, 0x0000 }, /* R2 - Power management 2 */
46 { 3, 0x0000 }, /* R3 - Power management 3 */
47 { 4, 0x0050 }, /* R4 - Audio Interface */
48 { 5, 0x0000 }, /* R5 - Companding control */
49 { 6, 0x0140 }, /* R6 - Clock Gen control */
50 { 7, 0x0000 }, /* R7 - Additional control */
51 { 8, 0x0000 }, /* R8 - GPIO Control */
52 { 9, 0x0000 }, /* R9 - Jack Detect Control 1 */
53 { 10, 0x0000 }, /* R10 - DAC Control */
54 { 11, 0x00FF }, /* R11 - Left DAC digital Vol */
55 { 12, 0x00FF }, /* R12 - Right DAC digital vol */
56 { 13, 0x0000 }, /* R13 - Jack Detect Control 2 */
57 { 14, 0x0100 }, /* R14 - ADC Control */
58 { 15, 0x00FF }, /* R15 - Left ADC Digital Vol */
59 { 16, 0x00FF }, /* R16 - Right ADC Digital Vol */
60 { 18, 0x012C }, /* R18 - EQ1 - low shelf */
61 { 19, 0x002C }, /* R19 - EQ2 - peak 1 */
62 { 20, 0x002C }, /* R20 - EQ3 - peak 2 */
63 { 21, 0x002C }, /* R21 - EQ4 - peak 3 */
64 { 22, 0x002C }, /* R22 - EQ5 - high shelf */
65 { 24, 0x0032 }, /* R24 - DAC Limiter 1 */
66 { 25, 0x0000 }, /* R25 - DAC Limiter 2 */
67 { 27, 0x0000 }, /* R27 - Notch Filter 1 */
68 { 28, 0x0000 }, /* R28 - Notch Filter 2 */
69 { 29, 0x0000 }, /* R29 - Notch Filter 3 */
70 { 30, 0x0000 }, /* R30 - Notch Filter 4 */
71 { 32, 0x0038 }, /* R32 - ALC control 1 */
72 { 33, 0x000B }, /* R33 - ALC control 2 */
73 { 34, 0x0032 }, /* R34 - ALC control 3 */
74 { 35, 0x0000 }, /* R35 - Noise Gate */
75 { 36, 0x0008 }, /* R36 - PLL N */
76 { 37, 0x000C }, /* R37 - PLL K 1 */
77 { 38, 0x0093 }, /* R38 - PLL K 2 */
78 { 39, 0x00E9 }, /* R39 - PLL K 3 */
79 { 41, 0x0000 }, /* R41 - 3D control */
80 { 42, 0x0000 }, /* R42 - OUT4 to ADC */
81 { 43, 0x0000 }, /* R43 - Beep control */
82 { 44, 0x0033 }, /* R44 - Input ctrl */
83 { 45, 0x0010 }, /* R45 - Left INP PGA gain ctrl */
84 { 46, 0x0010 }, /* R46 - Right INP PGA gain ctrl */
85 { 47, 0x0100 }, /* R47 - Left ADC BOOST ctrl */
86 { 48, 0x0100 }, /* R48 - Right ADC BOOST ctrl */
87 { 49, 0x0002 }, /* R49 - Output ctrl */
88 { 50, 0x0001 }, /* R50 - Left mixer ctrl */
89 { 51, 0x0001 }, /* R51 - Right mixer ctrl */
90 { 52, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */
91 { 53, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */
92 { 54, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */
93 { 55, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */
94 { 56, 0x0001 }, /* R56 - OUT3 mixer ctrl */
95 { 57, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */
96 { 60, 0x0004 }, /* R60 - OUTPUT ctrl */
97 { 61, 0x0000 }, /* R61 - BIAS CTRL */
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DP		 98};
99
411a3450
MB		 100static bool wm8985_writeable(struct device *dev, unsigned int reg)
101{
102 switch (reg) {
103 case WM8985_SOFTWARE_RESET:
104 case WM8985_POWER_MANAGEMENT_1:
105 case WM8985_POWER_MANAGEMENT_2:
106 case WM8985_POWER_MANAGEMENT_3:
107 case WM8985_AUDIO_INTERFACE:
108 case WM8985_COMPANDING_CONTROL:
109 case WM8985_CLOCK_GEN_CONTROL:
110 case WM8985_ADDITIONAL_CONTROL:
111 case WM8985_GPIO_CONTROL:
112 case WM8985_JACK_DETECT_CONTROL_1:
113 case WM8985_DAC_CONTROL:
114 case WM8985_LEFT_DAC_DIGITAL_VOL:
115 case WM8985_RIGHT_DAC_DIGITAL_VOL:
116 case WM8985_JACK_DETECT_CONTROL_2:
117 case WM8985_ADC_CONTROL:
118 case WM8985_LEFT_ADC_DIGITAL_VOL:
119 case WM8985_RIGHT_ADC_DIGITAL_VOL:
120 case WM8985_EQ1_LOW_SHELF:
121 case WM8985_EQ2_PEAK_1:
122 case WM8985_EQ3_PEAK_2:
123 case WM8985_EQ4_PEAK_3:
124 case WM8985_EQ5_HIGH_SHELF:
125 case WM8985_DAC_LIMITER_1:
126 case WM8985_DAC_LIMITER_2:
127 case WM8985_NOTCH_FILTER_1:
128 case WM8985_NOTCH_FILTER_2:
129 case WM8985_NOTCH_FILTER_3:
130 case WM8985_NOTCH_FILTER_4:
131 case WM8985_ALC_CONTROL_1:
132 case WM8985_ALC_CONTROL_2:
133 case WM8985_ALC_CONTROL_3:
134 case WM8985_NOISE_GATE:
135 case WM8985_PLL_N:
136 case WM8985_PLL_K_1:
137 case WM8985_PLL_K_2:
138 case WM8985_PLL_K_3:
139 case WM8985_3D_CONTROL:
140 case WM8985_OUT4_TO_ADC:
141 case WM8985_BEEP_CONTROL:
142 case WM8985_INPUT_CTRL:
143 case WM8985_LEFT_INP_PGA_GAIN_CTRL:
144 case WM8985_RIGHT_INP_PGA_GAIN_CTRL:
145 case WM8985_LEFT_ADC_BOOST_CTRL:
146 case WM8985_RIGHT_ADC_BOOST_CTRL:
147 case WM8985_OUTPUT_CTRL0:
148 case WM8985_LEFT_MIXER_CTRL:
149 case WM8985_RIGHT_MIXER_CTRL:
150 case WM8985_LOUT1_HP_VOLUME_CTRL:
151 case WM8985_ROUT1_HP_VOLUME_CTRL:
152 case WM8985_LOUT2_SPK_VOLUME_CTRL:
153 case WM8985_ROUT2_SPK_VOLUME_CTRL:
154 case WM8985_OUT3_MIXER_CTRL:
155 case WM8985_OUT4_MONO_MIX_CTRL:
156 case WM8985_OUTPUT_CTRL1:
157 case WM8985_BIAS_CTRL:
158 return true;
159 default:
160 return false;
161 }
162}
163
6d6f8b83
DP		 164/*
165 * latch bit 8 of these registers to ensure instant
166 * volume updates
167 */
168static const int volume_update_regs[] = {
169 WM8985_LEFT_DAC_DIGITAL_VOL,
170 WM8985_RIGHT_DAC_DIGITAL_VOL,
171 WM8985_LEFT_ADC_DIGITAL_VOL,
172 WM8985_RIGHT_ADC_DIGITAL_VOL,
173 WM8985_LOUT2_SPK_VOLUME_CTRL,
174 WM8985_ROUT2_SPK_VOLUME_CTRL,
175 WM8985_LOUT1_HP_VOLUME_CTRL,
176 WM8985_ROUT1_HP_VOLUME_CTRL,
177 WM8985_LEFT_INP_PGA_GAIN_CTRL,
178 WM8985_RIGHT_INP_PGA_GAIN_CTRL
179};
180
181struct wm8985_priv {
411a3450 182 struct regmap *regmap;
6d6f8b83
DP		 183 struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
184 unsigned int sysclk;
185 unsigned int bclk;
186};
187
188static const struct {
189 int div;
190 int ratio;
191} fs_ratios[] = {
192 { 10, 128 },
193 { 15, 192 },
194 { 20, 256 },
195 { 30, 384 },
196 { 40, 512 },
197 { 60, 768 },
198 { 80, 1024 },
199 { 120, 1536 }
200};
201
202static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
203
204static const int bclk_divs[] = {
205 1, 2, 4, 8, 16, 32
206};
207
208static int eqmode_get(struct snd_kcontrol *kcontrol,
209 struct snd_ctl_elem_value *ucontrol);
210static int eqmode_put(struct snd_kcontrol *kcontrol,
211 struct snd_ctl_elem_value *ucontrol);
212
213static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
214static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
215static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
216static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
217static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
218static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
219static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
220static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
221static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
222static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
223static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
224static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
225static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
226static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
227
228static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
229static const SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7,
230 alc_sel_text);
231
232static const char *alc_mode_text[] = { "ALC", "Limiter" };
233static const SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8,
234 alc_mode_text);
235
236static const char *filter_mode_text[] = { "Audio", "Application" };
237static const SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
238 filter_mode_text);
239
240static const char *eq_bw_text[] = { "Narrow", "Wide" };
241static const char *eqmode_text[] = { "Capture", "Playback" };
d1454e6f
DP		 242static const SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
243
6d6f8b83
DP		 244static const char *eq1_cutoff_text[] = {
245 "80Hz", "105Hz", "135Hz", "175Hz"
246};
247static const SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
248 eq1_cutoff_text);
249static const char *eq2_cutoff_text[] = {
250 "230Hz", "300Hz", "385Hz", "500Hz"
251};
252static const SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
253static const SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5,
254 eq2_cutoff_text);
255static const char *eq3_cutoff_text[] = {
256 "650Hz", "850Hz", "1.1kHz", "1.4kHz"
257};
258static const SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
259static const SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
260 eq3_cutoff_text);
261static const char *eq4_cutoff_text[] = {
262 "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
263};
264static const SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
265static const SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5,
266 eq4_cutoff_text);
267static const char *eq5_cutoff_text[] = {
268 "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
269};
270static const SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
271 eq5_cutoff_text);
272
273static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
274static const SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
275
276static const char *depth_3d_text[] = {
277 "Off",
278 "6.67%",
279 "13.3%",
280 "20%",
281 "26.7%",
282 "33.3%",
283 "40%",
284 "46.6%",
285 "53.3%",
286 "60%",
287 "66.7%",
288 "73.3%",
289 "80%",
290 "86.7%",
291 "93.3%",
292 "100%"
293};
294static const SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0,
295 depth_3d_text);
296
297static const struct snd_kcontrol_new wm8985_snd_controls[] = {
298 SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
299 0, 1, 0),
300
301 SOC_ENUM("ALC Capture Function", alc_sel),
302 SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
303 3, 7, 0, alc_max_tlv),
304 SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
305 0, 7, 0, alc_min_tlv),
306 SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
307 0, 15, 0, alc_tar_tlv),
308 SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
309 SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
310 SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
311 SOC_ENUM("ALC Mode", alc_mode),
312 SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
313 3, 1, 0),
314 SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
315 0, 7, 1),
316
317 SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
318 WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
319 SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
320 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
321 SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
322 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
323
324 SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
325 WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
326 8, 1, 0, pga_boost_tlv),
327
328 SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
329 SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
330
331 SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
332 WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
333
334 SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
335 SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
336 SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
337 SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
338 4, 7, 1, lim_thresh_tlv),
339 SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
340 0, 12, 0, lim_boost_tlv),
341 SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
342 SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
343 SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
344
345 SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
346 WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
347 SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
348 WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
349 SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
350 WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
351
352 SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
353 WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
354 SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
355 WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
356 SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
357 WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
358
359 SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
360 SOC_ENUM("High Pass Filter Mode", filter_mode),
361 SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
362
363 SOC_DOUBLE_R_TLV("Aux Bypass Volume",
364 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
365 aux_tlv),
366
367 SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
368 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
369 bypass_tlv),
370
371 SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
372 SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
373 SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
c46d5c04 374 SOC_ENUM("EQ2 Bandwidth", eq2_bw),
6d6f8b83
DP		 375 SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
376 SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
c46d5c04 377 SOC_ENUM("EQ3 Bandwidth", eq3_bw),
6d6f8b83
DP		 378 SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
379 SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
c46d5c04 380 SOC_ENUM("EQ4 Bandwidth", eq4_bw),
6d6f8b83
DP		 381 SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
382 SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
383 SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
384 SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
385
386 SOC_ENUM("3D Depth", depth_3d),
387
388 SOC_ENUM("Speaker Mode", speaker_mode)
389};
390
391static const struct snd_kcontrol_new left_out_mixer[] = {
392 SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
393 SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
394 SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
395};
396
397static const struct snd_kcontrol_new right_out_mixer[] = {
398 SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
399 SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
400 SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
401};
402
403static const struct snd_kcontrol_new left_input_mixer[] = {
404 SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
405 SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
406 SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
407};
408
409static const struct snd_kcontrol_new right_input_mixer[] = {
410 SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
411 SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
412 SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
413};
414
415static const struct snd_kcontrol_new left_boost_mixer[] = {
416 SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
417 4, 7, 0, boost_tlv),
418 SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
419 0, 7, 0, boost_tlv)
420};
421
422static const struct snd_kcontrol_new right_boost_mixer[] = {
423 SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
424 4, 7, 0, boost_tlv),
425 SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
426 0, 7, 0, boost_tlv)
427};
428
429static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
430 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
431 0, 0),
432 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
433 1, 0),
434 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
435 0, 0),
436 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
437 1, 0),
438
439 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
440 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
441 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
442 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
443
444 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
445 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
446 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
447 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
448
449 SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
450 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
451 SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
452 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
453
454 SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
455 6, 1, NULL, 0),
456 SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
457 6, 1, NULL, 0),
458
459 SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
460 7, 0, NULL, 0),
461 SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
462 8, 0, NULL, 0),
463
464 SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
465 5, 0, NULL, 0),
466 SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
467 6, 0, NULL, 0),
468
812f8a35
MB		 469 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0,
470 NULL, 0),
6d6f8b83
DP		 471
472 SND_SOC_DAPM_INPUT("LIN"),
473 SND_SOC_DAPM_INPUT("LIP"),
474 SND_SOC_DAPM_INPUT("RIN"),
475 SND_SOC_DAPM_INPUT("RIP"),
476 SND_SOC_DAPM_INPUT("AUXL"),
477 SND_SOC_DAPM_INPUT("AUXR"),
478 SND_SOC_DAPM_INPUT("L2"),
479 SND_SOC_DAPM_INPUT("R2"),
480 SND_SOC_DAPM_OUTPUT("HPL"),
481 SND_SOC_DAPM_OUTPUT("HPR"),
482 SND_SOC_DAPM_OUTPUT("SPKL"),
483 SND_SOC_DAPM_OUTPUT("SPKR")
484};
485
eb8f7693 486static const struct snd_soc_dapm_route wm8985_dapm_routes[] = {
6d6f8b83
DP		 487 { "Right Output Mixer", "PCM Switch", "Right DAC" },
488 { "Right Output Mixer", "Aux Switch", "AUXR" },
489 { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
490
491 { "Left Output Mixer", "PCM Switch", "Left DAC" },
492 { "Left Output Mixer", "Aux Switch", "AUXL" },
493 { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
494
495 { "Right Headphone Out", NULL, "Right Output Mixer" },
496 { "HPR", NULL, "Right Headphone Out" },
497
498 { "Left Headphone Out", NULL, "Left Output Mixer" },
499 { "HPL", NULL, "Left Headphone Out" },
500
501 { "Right Speaker Out", NULL, "Right Output Mixer" },
502 { "SPKR", NULL, "Right Speaker Out" },
503
504 { "Left Speaker Out", NULL, "Left Output Mixer" },
505 { "SPKL", NULL, "Left Speaker Out" },
506
507 { "Right ADC", NULL, "Right Boost Mixer" },
508
509 { "Right Boost Mixer", "AUXR Volume", "AUXR" },
510 { "Right Boost Mixer", NULL, "Right Capture PGA" },
511 { "Right Boost Mixer", "R2 Volume", "R2" },
512
513 { "Left ADC", NULL, "Left Boost Mixer" },
514
515 { "Left Boost Mixer", "AUXL Volume", "AUXL" },
516 { "Left Boost Mixer", NULL, "Left Capture PGA" },
517 { "Left Boost Mixer", "L2 Volume", "L2" },
518
519 { "Right Capture PGA", NULL, "Right Input Mixer" },
520 { "Left Capture PGA", NULL, "Left Input Mixer" },
521
522 { "Right Input Mixer", "R2 Switch", "R2" },
523 { "Right Input Mixer", "MicN Switch", "RIN" },
524 { "Right Input Mixer", "MicP Switch", "RIP" },
525
526 { "Left Input Mixer", "L2 Switch", "L2" },
527 { "Left Input Mixer", "MicN Switch", "LIN" },
528 { "Left Input Mixer", "MicP Switch", "LIP" },
529};
530
531static int eqmode_get(struct snd_kcontrol *kcontrol,
532 struct snd_ctl_elem_value *ucontrol)
533{
534 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
535 unsigned int reg;
536
537 reg = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
538 if (reg & WM8985_EQ3DMODE)
539 ucontrol->value.integer.value[0] = 1;
540 else
541 ucontrol->value.integer.value[0] = 0;
542
543 return 0;
544}
545
546static int eqmode_put(struct snd_kcontrol *kcontrol,
547 struct snd_ctl_elem_value *ucontrol)
548{
549 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
550 unsigned int regpwr2, regpwr3;
551 unsigned int reg_eq;
552
553 if (ucontrol->value.integer.value[0] != 0
554 && ucontrol->value.integer.value[0] != 1)
555 return -EINVAL;
556
557 reg_eq = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
558 switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
559 case 0:
560 if (!ucontrol->value.integer.value[0])
561 return 0;
562 break;
563 case 1:
564 if (ucontrol->value.integer.value[0])
565 return 0;
566 break;
567 }
568
569 regpwr2 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_2);
570 regpwr3 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_3);
571 /* disable the DACs and ADCs */
572 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_2,
573 WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
574 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_3,
575 WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
576 snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
577 WM8985_M128ENB_MASK, WM8985_M128ENB);
578 /* set the desired eqmode */
579 snd_soc_update_bits(codec, WM8985_EQ1_LOW_SHELF,
580 WM8985_EQ3DMODE_MASK,
581 ucontrol->value.integer.value[0]
582 << WM8985_EQ3DMODE_SHIFT);
583 /* restore DAC/ADC configuration */
584 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, regpwr2);
585 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, regpwr3);
586 return 0;
587}
588
6d6f8b83
DP		 589static int wm8985_reset(struct snd_soc_codec *codec)
590{
591 return snd_soc_write(codec, WM8985_SOFTWARE_RESET, 0x0);
592}
593
594static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute)
595{
596 struct snd_soc_codec *codec = dai->codec;
597
598 return snd_soc_update_bits(codec, WM8985_DAC_CONTROL,
599 WM8985_SOFTMUTE_MASK,
600 !!mute << WM8985_SOFTMUTE_SHIFT);
601}
602
603static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
604{
6d6f8b83
DP		 605 struct snd_soc_codec *codec;
606 u16 format, master, bcp, lrp;
607
608 codec = dai->codec;
6d6f8b83
DP		 609
610 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
611 case SND_SOC_DAIFMT_I2S:
612 format = 0x2;
613 break;
614 case SND_SOC_DAIFMT_RIGHT_J:
615 format = 0x0;
616 break;
617 case SND_SOC_DAIFMT_LEFT_J:
618 format = 0x1;
619 break;
620 case SND_SOC_DAIFMT_DSP_A:
621 case SND_SOC_DAIFMT_DSP_B:
622 format = 0x3;
623 break;
624 default:
625 dev_err(dai->dev, "Unknown dai format\n");
626 return -EINVAL;
627 }
628
629 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
630 WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
631
632 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
633 case SND_SOC_DAIFMT_CBM_CFM:
634 master = 1;
635 break;
636 case SND_SOC_DAIFMT_CBS_CFS:
637 master = 0;
638 break;
639 default:
640 dev_err(dai->dev, "Unknown master/slave configuration\n");
641 return -EINVAL;
642 }
643
644 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
645 WM8985_MS_MASK, master << WM8985_MS_SHIFT);
646
647 /* frame inversion is not valid for dsp modes */
648 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
649 case SND_SOC_DAIFMT_DSP_A:
650 case SND_SOC_DAIFMT_DSP_B:
651 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
652 case SND_SOC_DAIFMT_IB_IF:
653 case SND_SOC_DAIFMT_NB_IF:
654 return -EINVAL;
655 default:
656 break;
657 }
658 break;
659 default:
660 break;
661 }
662
663 bcp = lrp = 0;
664 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
665 case SND_SOC_DAIFMT_NB_NF:
666 break;
667 case SND_SOC_DAIFMT_IB_IF:
668 bcp = lrp = 1;
669 break;
670 case SND_SOC_DAIFMT_IB_NF:
671 bcp = 1;
672 break;
673 case SND_SOC_DAIFMT_NB_IF:
674 lrp = 1;
675 break;
676 default:
677 dev_err(dai->dev, "Unknown polarity configuration\n");
678 return -EINVAL;
679 }
680
681 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
682 WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
683 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
684 WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
685 return 0;
686}
687
688static int wm8985_hw_params(struct snd_pcm_substream *substream,
689 struct snd_pcm_hw_params *params,
690 struct snd_soc_dai *dai)
691{
cf1ff501 692 int i;
6d6f8b83
DP		 693 struct snd_soc_codec *codec;
694 struct wm8985_priv *wm8985;
695 u16 blen, srate_idx;
696 unsigned int tmp;
697 int srate_best;
698
699 codec = dai->codec;
700 wm8985 = snd_soc_codec_get_drvdata(codec);
701
702 wm8985->bclk = snd_soc_params_to_bclk(params);
703 if ((int)wm8985->bclk < 0)
704 return wm8985->bclk;
705
706 switch (params_format(params)) {
707 case SNDRV_PCM_FORMAT_S16_LE:
708 blen = 0x0;
709 break;
710 case SNDRV_PCM_FORMAT_S20_3LE:
711 blen = 0x1;
712 break;
713 case SNDRV_PCM_FORMAT_S24_LE:
714 blen = 0x2;
715 break;
716 case SNDRV_PCM_FORMAT_S32_LE:
717 blen = 0x3;
718 break;
719 default:
720 dev_err(dai->dev, "Unsupported word length %u\n",
721 params_format(params));
722 return -EINVAL;
723 }
724
725 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
726 WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
727
728 /*
729 * match to the nearest possible sample rate and rely
730 * on the array index to configure the SR register
731 */
732 srate_idx = 0;
733 srate_best = abs(srates[0] - params_rate(params));
734 for (i = 1; i < ARRAY_SIZE(srates); ++i) {
735 if (abs(srates[i] - params_rate(params)) >= srate_best)
736 continue;
737 srate_idx = i;
738 srate_best = abs(srates[i] - params_rate(params));
739 }
740
741 dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
742 snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
743 WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
744
745 dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
746 dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
747
748 for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
749 if (wm8985->sysclk / params_rate(params)
750 == fs_ratios[i].ratio)
751 break;
752 }
753
754 if (i == ARRAY_SIZE(fs_ratios)) {
755 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
756 wm8985->sysclk, params_rate(params));
757 return -EINVAL;
758 }
759
760 dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
761 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
762 WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
763
764 /* select the appropriate bclk divider */
765 tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
766 for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
767 if (wm8985->bclk == tmp / bclk_divs[i])
768 break;
769 }
770
771 if (i == ARRAY_SIZE(bclk_divs)) {
772 dev_err(dai->dev, "No matching BCLK divider found\n");
773 return -EINVAL;
774 }
775
776 dev_dbg(dai->dev, "BCLK div = %d\n", i);
777 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
778 WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
779 return 0;
780}
781
782struct pll_div {
783 u32 div2:1;
784 u32 n:4;
785 u32 k:24;
786};
787
788#define FIXED_PLL_SIZE ((1ULL << 24) * 10)
789static int pll_factors(struct pll_div *pll_div, unsigned int target,
790 unsigned int source)
791{
792 u64 Kpart;
793 unsigned long int K, Ndiv, Nmod;
794
795 pll_div->div2 = 0;
796 Ndiv = target / source;
797 if (Ndiv < 6) {
798 source >>= 1;
799 pll_div->div2 = 1;
800 Ndiv = target / source;
801 }
802
803 if (Ndiv < 6 || Ndiv > 12) {
804 printk(KERN_ERR "%s: WM8985 N value is not within"
805 " the recommended range: %lu\n", __func__, Ndiv);
806 return -EINVAL;
807 }
808 pll_div->n = Ndiv;
809
810 Nmod = target % source;
811 Kpart = FIXED_PLL_SIZE * (u64)Nmod;
812
813 do_div(Kpart, source);
814
815 K = Kpart & 0xffffffff;
816 if ((K % 10) >= 5)
817 K += 5;
818 K /= 10;
819 pll_div->k = K;
820
821 return 0;
822}
823
824static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
825 int source, unsigned int freq_in,
826 unsigned int freq_out)
827{
828 int ret;
829 struct snd_soc_codec *codec;
830 struct pll_div pll_div;
831
832 codec = dai->codec;
5f3d25c0
FE		 833 if (!freq_in || !freq_out) {
834 /* disable the PLL */
835 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
836 WM8985_PLLEN_MASK, 0);
837 } else {
6d6f8b83
DP		 838 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
839 if (ret)
840 return ret;
6d6f8b83 841
5f3d25c0
FE		 842 /* set PLLN and PRESCALE */
843 snd_soc_write(codec, WM8985_PLL_N,
844 (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
845 | pll_div.n);
846 /* set PLLK */
847 snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff);
848 snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
849 snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18));
850 /* set the source of the clock to be the PLL */
851 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
852 WM8985_CLKSEL_MASK, WM8985_CLKSEL);
853 /* enable the PLL */
854 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
855 WM8985_PLLEN_MASK, WM8985_PLLEN);
856 }
6d6f8b83
DP		 857 return 0;
858}
859
860static int wm8985_set_sysclk(struct snd_soc_dai *dai,
861 int clk_id, unsigned int freq, int dir)
862{
863 struct snd_soc_codec *codec;
864 struct wm8985_priv *wm8985;
865
866 codec = dai->codec;
867 wm8985 = snd_soc_codec_get_drvdata(codec);
868
869 switch (clk_id) {
870 case WM8985_CLKSRC_MCLK:
871 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
872 WM8985_CLKSEL_MASK, 0);
873 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
874 WM8985_PLLEN_MASK, 0);
875 break;
876 case WM8985_CLKSRC_PLL:
877 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
878 WM8985_CLKSEL_MASK, WM8985_CLKSEL);
879 break;
880 default:
881 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
882 return -EINVAL;
883 }
884
885 wm8985->sysclk = freq;
886 return 0;
887}
888
6d6f8b83
DP		 889static int wm8985_set_bias_level(struct snd_soc_codec *codec,
890 enum snd_soc_bias_level level)
891{
892 int ret;
893 struct wm8985_priv *wm8985;
894
895 wm8985 = snd_soc_codec_get_drvdata(codec);
896 switch (level) {
897 case SND_SOC_BIAS_ON:
898 case SND_SOC_BIAS_PREPARE:
899 /* VMID at 75k */
900 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
901 WM8985_VMIDSEL_MASK,
902 1 << WM8985_VMIDSEL_SHIFT);
903 break;
904 case SND_SOC_BIAS_STANDBY:
ce6120cc 905 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
6d6f8b83
DP		 906 ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
907 wm8985->supplies);
908 if (ret) {
909 dev_err(codec->dev,
910 "Failed to enable supplies: %d\n",
911 ret);
912 return ret;
913 }
914
411a3450 915 regcache_sync(wm8985->regmap);
6d6f8b83
DP		 916
917 /* enable anti-pop features */
918 snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
919 WM8985_POBCTRL_MASK,
920 WM8985_POBCTRL);
921 /* enable thermal shutdown */
922 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
923 WM8985_TSDEN_MASK, WM8985_TSDEN);
924 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
925 WM8985_TSOPCTRL_MASK,
926 WM8985_TSOPCTRL);
927 /* enable BIASEN */
928 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
929 WM8985_BIASEN_MASK, WM8985_BIASEN);
930 /* VMID at 75k */
931 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
932 WM8985_VMIDSEL_MASK,
933 1 << WM8985_VMIDSEL_SHIFT);
934 msleep(500);
935 /* disable anti-pop features */
936 snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
937 WM8985_POBCTRL_MASK, 0);
938 }
939 /* VMID at 300k */
940 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
941 WM8985_VMIDSEL_MASK,
942 2 << WM8985_VMIDSEL_SHIFT);
943 break;
944 case SND_SOC_BIAS_OFF:
945 /* disable thermal shutdown */
946 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
947 WM8985_TSOPCTRL_MASK, 0);
948 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
949 WM8985_TSDEN_MASK, 0);
950 /* disable VMIDSEL and BIASEN */
951 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
952 WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
953 0);
954 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_1, 0);
955 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, 0);
956 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, 0);
957
411a3450 958 regcache_mark_dirty(wm8985->regmap);
6d6f8b83
DP		 959
960 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
961 wm8985->supplies);
962 break;
963 }
964
ce6120cc 965 codec->dapm.bias_level = level;
6d6f8b83
DP		 966 return 0;
967}
968
969#ifdef CONFIG_PM
84b315ee 970static int wm8985_suspend(struct snd_soc_codec *codec)
6d6f8b83
DP		 971{
972 wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
973 return 0;
974}
975
976static int wm8985_resume(struct snd_soc_codec *codec)
977{
978 wm8985_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
979 return 0;
980}
981#else
982#define wm8985_suspend NULL
983#define wm8985_resume NULL
984#endif
985
986static int wm8985_remove(struct snd_soc_codec *codec)
987{
988 struct wm8985_priv *wm8985;
989
990 wm8985 = snd_soc_codec_get_drvdata(codec);
991 wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
992 regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
993 return 0;
994}
995
996static int wm8985_probe(struct snd_soc_codec *codec)
997{
998 size_t i;
999 struct wm8985_priv *wm8985;
1000 int ret;
6d6f8b83
DP		 1001
1002 wm8985 = snd_soc_codec_get_drvdata(codec);
411a3450 1003 codec->control_data = wm8985->regmap;
6d6f8b83 1004
411a3450 1005 ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);
6d6f8b83
DP		 1006 if (ret < 0) {
1007 dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
1008 return ret;
1009 }
1010
1011 for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
1012 wm8985->supplies[i].supply = wm8985_supply_names[i];
1013
1014 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8985->supplies),
1015 wm8985->supplies);
1016 if (ret) {
1017 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1018 return ret;
1019 }
1020
1021 ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
1022 wm8985->supplies);
1023 if (ret) {
1024 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1025 goto err_reg_get;
1026 }
1027
1028 ret = wm8985_reset(codec);
1029 if (ret < 0) {
1030 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1031 goto err_reg_enable;
1032 }
1033
6d6f8b83
DP		 1034 /* latch volume update bits */
1035 for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
9f8cbae4
MB		 1036 snd_soc_update_bits(codec, volume_update_regs[i],
1037 0x100, 0x100);
6d6f8b83 1038 /* enable BIASCUT */
9f8cbae4
MB		 1039 snd_soc_update_bits(codec, WM8985_BIAS_CTRL, WM8985_BIASCUT,
1040 WM8985_BIASCUT);
6d6f8b83 1041
6d6f8b83
DP		 1042 wm8985_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1043 return 0;
1044
1045err_reg_enable:
1046 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1047err_reg_get:
1048 regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1049 return ret;
1050}
1051
85e7652d 1052static const struct snd_soc_dai_ops wm8985_dai_ops = {
6d6f8b83
DP		 1053 .digital_mute = wm8985_dac_mute,
1054 .hw_params = wm8985_hw_params,
1055 .set_fmt = wm8985_set_fmt,
1056 .set_sysclk = wm8985_set_sysclk,
1057 .set_pll = wm8985_set_pll
1058};
1059
1060#define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1061 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1062
1063static struct snd_soc_dai_driver wm8985_dai = {
1064 .name = "wm8985-hifi",
1065 .playback = {
1066 .stream_name = "Playback",
1067 .channels_min = 2,
1068 .channels_max = 2,
1069 .rates = SNDRV_PCM_RATE_8000_48000,
1070 .formats = WM8985_FORMATS,
1071 },
1072 .capture = {
1073 .stream_name = "Capture",
1074 .channels_min = 2,
1075 .channels_max = 2,
1076 .rates = SNDRV_PCM_RATE_8000_48000,
1077 .formats = WM8985_FORMATS,
1078 },
1079 .ops = &wm8985_dai_ops,
1080 .symmetric_rates = 1
1081};
1082
1083static struct snd_soc_codec_driver soc_codec_dev_wm8985 = {
1084 .probe = wm8985_probe,
1085 .remove = wm8985_remove,
1086 .suspend = wm8985_suspend,
1087 .resume = wm8985_resume,
1088 .set_bias_level = wm8985_set_bias_level,
eb8f7693
MB		 1089
1090 .controls = wm8985_snd_controls,
1091 .num_controls = ARRAY_SIZE(wm8985_snd_controls),
1092 .dapm_widgets = wm8985_dapm_widgets,
eb8f7693
MB		 1093 .num_dapm_widgets = ARRAY_SIZE(wm8985_dapm_widgets),
1094 .dapm_routes = wm8985_dapm_routes,
1095 .num_dapm_routes = ARRAY_SIZE(wm8985_dapm_routes),
6d6f8b83
DP		 1096};
1097
411a3450
MB		 1098static const struct regmap_config wm8985_regmap = {
1099 .reg_bits = 7,
1100 .val_bits = 9,
1101
1102 .max_register = WM8985_MAX_REGISTER,
1103 .writeable_reg = wm8985_writeable,
1104
1105 .cache_type = REGCACHE_RBTREE,
1106 .reg_defaults = wm8985_reg_defaults,
1107 .num_reg_defaults = ARRAY_SIZE(wm8985_reg_defaults),
1108};
1109
6d6f8b83 1110#if defined(CONFIG_SPI_MASTER)
7a79e94e 1111static int wm8985_spi_probe(struct spi_device *spi)
6d6f8b83
DP		 1112{
1113 struct wm8985_priv *wm8985;
1114 int ret;
1115
a1fea940 1116 wm8985 = devm_kzalloc(&spi->dev, sizeof *wm8985, GFP_KERNEL);
fe3e2e7f
DC		 1117 if (!wm8985)
1118 return -ENOMEM;
6d6f8b83 1119
6d6f8b83
DP		 1120 spi_set_drvdata(spi, wm8985);
1121
f911fa82 1122 wm8985->regmap = devm_regmap_init_spi(spi, &wm8985_regmap);
411a3450
MB		 1123 if (IS_ERR(wm8985->regmap)) {
1124 ret = PTR_ERR(wm8985->regmap);
1125 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1126 ret);
f911fa82 1127 return ret;
411a3450
MB		 1128 }
1129
6d6f8b83
DP		 1130 ret = snd_soc_register_codec(&spi->dev,
1131 &soc_codec_dev_wm8985, &wm8985_dai, 1);
6d6f8b83
DP		 1132 return ret;
1133}
1134
7a79e94e 1135static int wm8985_spi_remove(struct spi_device *spi)
6d6f8b83
DP		 1136{
1137 snd_soc_unregister_codec(&spi->dev);
6d6f8b83
DP		 1138 return 0;
1139}
1140
1141static struct spi_driver wm8985_spi_driver = {
1142 .driver = {
1143 .name = "wm8985",
6d6f8b83
DP		 1144 .owner = THIS_MODULE,
1145 },
1146 .probe = wm8985_spi_probe,
7a79e94e 1147 .remove = wm8985_spi_remove
6d6f8b83
DP		 1148};
1149#endif
1150
1151#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
7a79e94e
BP		 1152static int wm8985_i2c_probe(struct i2c_client *i2c,
1153 const struct i2c_device_id *id)
6d6f8b83
DP		 1154{
1155 struct wm8985_priv *wm8985;
1156 int ret;
1157
a1fea940 1158 wm8985 = devm_kzalloc(&i2c->dev, sizeof *wm8985, GFP_KERNEL);
fe3e2e7f
DC		 1159 if (!wm8985)
1160 return -ENOMEM;
6d6f8b83 1161
6d6f8b83
DP		 1162 i2c_set_clientdata(i2c, wm8985);
1163
f911fa82 1164 wm8985->regmap = devm_regmap_init_i2c(i2c, &wm8985_regmap);
411a3450
MB		 1165 if (IS_ERR(wm8985->regmap)) {
1166 ret = PTR_ERR(wm8985->regmap);
1167 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1168 ret);
f911fa82 1169 return ret;
411a3450
MB		 1170 }
1171
6d6f8b83
DP		 1172 ret = snd_soc_register_codec(&i2c->dev,
1173 &soc_codec_dev_wm8985, &wm8985_dai, 1);
6d6f8b83
DP		 1174 return ret;
1175}
1176
7a79e94e 1177static int wm8985_i2c_remove(struct i2c_client *i2c)
6d6f8b83 1178{
411a3450 1179 snd_soc_unregister_codec(&i2c->dev);
6d6f8b83
DP		 1180 return 0;
1181}
1182
1183static const struct i2c_device_id wm8985_i2c_id[] = {
1184 { "wm8985", 0 },
1185 { }
1186};
1187MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
1188
1189static struct i2c_driver wm8985_i2c_driver = {
1190 .driver = {
1191 .name = "wm8985",
1192 .owner = THIS_MODULE,
1193 },
1194 .probe = wm8985_i2c_probe,
7a79e94e 1195 .remove = wm8985_i2c_remove,
6d6f8b83
DP		 1196 .id_table = wm8985_i2c_id
1197};
1198#endif
1199
1200static int __init wm8985_modinit(void)
1201{
1202 int ret = 0;
1203
1204#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1205 ret = i2c_add_driver(&wm8985_i2c_driver);
1206 if (ret) {
1207 printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
1208 ret);
1209 }
1210#endif
1211#if defined(CONFIG_SPI_MASTER)
1212 ret = spi_register_driver(&wm8985_spi_driver);
1213 if (ret != 0) {
1214 printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
1215 ret);
1216 }
1217#endif
1218 return ret;
1219}
1220module_init(wm8985_modinit);
1221
1222static void __exit wm8985_exit(void)
1223{
1224#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1225 i2c_del_driver(&wm8985_i2c_driver);
1226#endif
1227#if defined(CONFIG_SPI_MASTER)
1228 spi_unregister_driver(&wm8985_spi_driver);
1229#endif
1230}
1231module_exit(wm8985_exit);
1232
1233MODULE_DESCRIPTION("ASoC WM8985 driver");
1234MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1235MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)