[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / uda134x.c

/*
 * uda134x.c  --  UDA134X ALSA SoC Codec driver
 *
 * Modifications by Christian Pellegrin <chripell@evolware.org>
 *
 * Copyright 2007 Dension Audio Systems Ltd.
 * Author: Zoltan Devai
 *
 * Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>

#include <sound/uda134x.h>
#include <sound/l3.h>

#include "uda134x.h"


#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
		SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)

struct uda134x_priv {
	int sysclk;
	int dai_fmt;

	struct snd_pcm_substream *master_substream;
	struct snd_pcm_substream *slave_substream;
};

/* In-data addresses are hard-coded into the reg-cache values */
static const char uda134x_reg[UDA134X_REGS_NUM] = {
	/* Extended address registers */
	0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
	/* Status, data regs */
	0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
};

/*
 * The codec has no support for reading its registers except for peak level...
 */
static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
	unsigned int reg)
{
	u8 *cache = codec->reg_cache;

	if (reg >= UDA134X_REGS_NUM)
		return -1;
	return cache[reg];
}

/*
 * Write the register cache
 */
static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
	u8 reg, unsigned int value)
{
	u8 *cache = codec->reg_cache;

	if (reg >= UDA134X_REGS_NUM)
		return;
	cache[reg] = value;
}

/*
 * Write to the uda134x registers
 *
 */
static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
	unsigned int value)
{
	int ret;
	u8 addr;
	u8 data = value;
	struct uda134x_platform_data *pd = codec->control_data;

	pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);

	if (reg >= UDA134X_REGS_NUM) {
		printk(KERN_ERR "%s unknown register: reg: %u",
		       __func__, reg);
		return -EINVAL;
	}

	uda134x_write_reg_cache(codec, reg, value);

	switch (reg) {
	case UDA134X_STATUS0:
	case UDA134X_STATUS1:
		addr = UDA134X_STATUS_ADDR;
		break;
	case UDA134X_DATA000:
	case UDA134X_DATA001:
	case UDA134X_DATA010:
	case UDA134X_DATA011:
		addr = UDA134X_DATA0_ADDR;
		break;
	case UDA134X_DATA1:
		addr = UDA134X_DATA1_ADDR;
		break;
	default:
		/* It's an extended address register */
		addr =  (reg | UDA134X_EXTADDR_PREFIX);

		ret = l3_write(&pd->l3,
			       UDA134X_DATA0_ADDR, &addr, 1);
		if (ret != 1)
			return -EIO;

		addr = UDA134X_DATA0_ADDR;
		data = (value | UDA134X_EXTDATA_PREFIX);
		break;
	}

	ret = l3_write(&pd->l3,
		       addr, &data, 1);
	if (ret != 1)
		return -EIO;

	return 0;
}

static inline void uda134x_reset(struct snd_soc_codec *codec)
{
	u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	uda134x_write(codec, UDA134X_STATUS0, reset_reg | (1<<6));
	msleep(1);
	uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
}

static int uda134x_mute(struct snd_soc_dai *dai, int mute)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);

	pr_debug("%s mute: %d\n", __func__, mute);

	if (mute)
		mute_reg |= (1<<2);
	else
		mute_reg &= ~(1<<2);

	uda134x_write(codec, UDA134X_DATA010, mute_reg);

	return 0;
}

static int uda134x_startup(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	struct snd_pcm_runtime *master_runtime;

	if (uda134x->master_substream) {
		master_runtime = uda134x->master_substream->runtime;

		pr_debug("%s constraining to %d bits at %d\n", __func__,
			 master_runtime->sample_bits,
			 master_runtime->rate);

		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_RATE,
					     master_runtime->rate,
					     master_runtime->rate);

		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
					     master_runtime->sample_bits,
					     master_runtime->sample_bits);

		uda134x->slave_substream = substream;
	} else
		uda134x->master_substream = substream;

	return 0;
}

static void uda134x_shutdown(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	if (uda134x->master_substream == substream)
		uda134x->master_substream = uda134x->slave_substream;

	uda134x->slave_substream = NULL;
}

static int uda134x_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params,
	struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_codec *codec = rtd->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	u8 hw_params;

	if (substream == uda134x->slave_substream) {
		pr_debug("%s ignoring hw_params for slave substream\n",
			 __func__);
		return 0;
	}

	hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	hw_params &= STATUS0_SYSCLK_MASK;
	hw_params &= STATUS0_DAIFMT_MASK;

	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
		 uda134x->sysclk, params_rate(params));

	/* set SYSCLK / fs ratio */
	switch (uda134x->sysclk / params_rate(params)) {
	case 512:
		break;
	case 384:
		hw_params |= (1<<4);
		break;
	case 256:
		hw_params |= (1<<5);
		break;
	default:
		printk(KERN_ERR "%s unsupported fs\n", __func__);
		return -EINVAL;
	}

	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
		 uda134x->dai_fmt, params_format(params));

	/* set DAI format and word length */
	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		switch (params_format(params)) {
		case SNDRV_PCM_FORMAT_S16_LE:
			hw_params |= (1<<1);
			break;
		case SNDRV_PCM_FORMAT_S18_3LE:
			hw_params |= (1<<2);
			break;
		case SNDRV_PCM_FORMAT_S20_3LE:
			hw_params |= ((1<<2) | (1<<1));
			break;
		default:
			printk(KERN_ERR "%s unsupported format (right)\n",
			       __func__);
			return -EINVAL;
		}
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		hw_params |= (1<<3);
		break;
	default:
		printk(KERN_ERR "%s unsupported format\n", __func__);
		return -EINVAL;
	}

	uda134x_write(codec, UDA134X_STATUS0, hw_params);

	return 0;
}

static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
		 clk_id, freq, dir);

	/* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
	   because the codec is slave. Of course limitations of the clock
	   master (the IIS controller) apply.
	   We'll error out on set_hw_params if it's not OK */
	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
		uda134x->sysclk = freq;
		return 0;
	}

	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
	return -EINVAL;
}

static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
			       unsigned int fmt)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	pr_debug("%s fmt: %08X\n", __func__, fmt);

	/* codec supports only full slave mode */
	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
		printk(KERN_ERR "%s unsupported slave mode\n", __func__);
		return -EINVAL;
	}

	/* no support for clock inversion */
	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
		printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
		return -EINVAL;
	}

	/* We can't setup DAI format here as it depends on the word bit num */
	/* so let's just store the value for later */
	uda134x->dai_fmt = fmt;

	return 0;
}

static int uda134x_set_bias_level(struct snd_soc_codec *codec,
				  enum snd_soc_bias_level level)
{
	u8 reg;
	struct uda134x_platform_data *pd = codec->control_data;
	int i;
	u8 *cache = codec->reg_cache;

	pr_debug("%s bias level %d\n", __func__, level);

	switch (level) {
	case SND_SOC_BIAS_ON:
		/* ADC, DAC on */
		switch (pd->model) {
		case UDA134X_UDA1340:
		case UDA134X_UDA1344:
		case UDA134X_UDA1345:
			reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
			uda134x_write(codec, UDA134X_DATA011, reg | 0x03);
			break;
		case UDA134X_UDA1341:
			reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
			uda134x_write(codec, UDA134X_STATUS1, reg | 0x03);
			break;
		default:
			printk(KERN_ERR "UDA134X SoC codec: "
			       "unsupported model %d\n", pd->model);
			return -EINVAL;
		}
		break;
	case SND_SOC_BIAS_PREPARE:
		/* power on */
		if (pd->power) {
			pd->power(1);
			/* Sync reg_cache with the hardware */
			for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
				codec->driver->write(codec, i, *cache++);
		}
		break;
	case SND_SOC_BIAS_STANDBY:
		/* ADC, DAC power off */
		switch (pd->model) {
		case UDA134X_UDA1340:
		case UDA134X_UDA1344:
		case UDA134X_UDA1345:
			reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
			uda134x_write(codec, UDA134X_DATA011, reg & ~(0x03));
			break;
		case UDA134X_UDA1341:
			reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
			uda134x_write(codec, UDA134X_STATUS1, reg & ~(0x03));
			break;
		default:
			printk(KERN_ERR "UDA134X SoC codec: "
			       "unsupported model %d\n", pd->model);
			return -EINVAL;
		}
		break;
	case SND_SOC_BIAS_OFF:
		/* power off */
		if (pd->power)
			pd->power(0);
		break;
	}
	codec->dapm.bias_level = level;
	return 0;
}

static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
					    "Minimum2", "Maximum"};
static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const char *uda134x_mixmode[] = {"Differential", "Analog1",
					"Analog2", "Both"};

static const struct soc_enum uda134x_mixer_enum[] = {
SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
};

static const struct snd_kcontrol_new uda1341_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),

SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),

SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),

SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),

SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),

SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_kcontrol_new uda1340_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),

SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),

SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),

SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_kcontrol_new uda1345_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),

SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),

SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_soc_dai_ops uda134x_dai_ops = {
	.startup	= uda134x_startup,
	.shutdown	= uda134x_shutdown,
	.hw_params	= uda134x_hw_params,
	.digital_mute	= uda134x_mute,
	.set_sysclk	= uda134x_set_dai_sysclk,
	.set_fmt	= uda134x_set_dai_fmt,
};

static struct snd_soc_dai_driver uda134x_dai = {
	.name = "uda134x-hifi",
	/* playback capabilities */
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = UDA134X_RATES,
		.formats = UDA134X_FORMATS,
	},
	/* capture capabilities */
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 2,
		.rates = UDA134X_RATES,
		.formats = UDA134X_FORMATS,
	},
	/* pcm operations */
	.ops = &uda134x_dai_ops,
};

static int uda134x_soc_probe(struct snd_soc_codec *codec)
{
	struct uda134x_priv *uda134x;
	struct uda134x_platform_data *pd = codec->card->dev->platform_data;

	int ret;

	printk(KERN_INFO "UDA134X SoC Audio Codec\n");

	if (!pd) {
		printk(KERN_ERR "UDA134X SoC codec: "
		       "missing L3 bitbang function\n");
		return -ENODEV;
	}

	switch (pd->model) {
	case UDA134X_UDA1340:
	case UDA134X_UDA1341:
	case UDA134X_UDA1344:
	case UDA134X_UDA1345:
		break;
	default:
		printk(KERN_ERR "UDA134X SoC codec: "
		       "unsupported model %d\n",
			pd->model);
		return -EINVAL;
	}

	uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
	if (uda134x == NULL)
		return -ENOMEM;
	snd_soc_codec_set_drvdata(codec, uda134x);

	codec->control_data = pd;

	if (pd->power)
		pd->power(1);

	uda134x_reset(codec);

	if (pd->is_powered_on_standby)
		uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
	else
		uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);

	switch (pd->model) {
	case UDA134X_UDA1340:
	case UDA134X_UDA1344:
		ret = snd_soc_add_codec_controls(codec, uda1340_snd_controls,
					ARRAY_SIZE(uda1340_snd_controls));
	break;
	case UDA134X_UDA1341:
		ret = snd_soc_add_codec_controls(codec, uda1341_snd_controls,
					ARRAY_SIZE(uda1341_snd_controls));
	break;
	case UDA134X_UDA1345:
		ret = snd_soc_add_codec_controls(codec, uda1345_snd_controls,
					ARRAY_SIZE(uda1345_snd_controls));
	break;
	default:
		printk(KERN_ERR "%s unknown codec type: %d",
			__func__, pd->model);
		kfree(uda134x);
		return -EINVAL;
	}

	if (ret < 0) {
		printk(KERN_ERR "UDA134X: failed to register controls\n");
		kfree(uda134x);
		return ret;
	}

	return 0;
}

/* power down chip */
static int uda134x_soc_remove(struct snd_soc_codec *codec)
{
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);

	kfree(uda134x);
	return 0;
}

#if defined(CONFIG_PM)
static int uda134x_soc_suspend(struct snd_soc_codec *codec)
{
	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
	return 0;
}

static int uda134x_soc_resume(struct snd_soc_codec *codec)
{
	uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
	uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
	return 0;
}
#else
#define uda134x_soc_suspend NULL
#define uda134x_soc_resume NULL
#endif /* CONFIG_PM */

static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
	.probe =        uda134x_soc_probe,
	.remove =       uda134x_soc_remove,
	.suspend =      uda134x_soc_suspend,
	.resume =       uda134x_soc_resume,
	.reg_cache_size = sizeof(uda134x_reg),
	.reg_word_size = sizeof(u8),
	.reg_cache_default = uda134x_reg,
	.reg_cache_step = 1,
	.read = uda134x_read_reg_cache,
	.write = uda134x_write,
	.set_bias_level = uda134x_set_bias_level,
};

static int uda134x_codec_probe(struct platform_device *pdev)
{
	return snd_soc_register_codec(&pdev->dev,
			&soc_codec_dev_uda134x, &uda134x_dai, 1);
}

static int uda134x_codec_remove(struct platform_device *pdev)
{
	snd_soc_unregister_codec(&pdev->dev);
	return 0;
}

static struct platform_driver uda134x_codec_driver = {
	.driver = {
		.name = "uda134x-codec",
		.owner = THIS_MODULE,
	},
	.probe = uda134x_codec_probe,
	.remove = uda134x_codec_remove,
};

module_platform_driver(uda134x_codec_driver);

MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
1cad1de1 CP	1	/*
	2	* uda134x.c -- UDA134X ALSA SoC Codec driver
	3	*
	4	* Modifications by Christian Pellegrin <chripell@evolware.org>
	5	*
	6	* Copyright 2007 Dension Audio Systems Ltd.
	7	* Author: Zoltan Devai
	8	*
	9	* Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/delay.h>
5a0e3ad6	18	#include <linux/slab.h>
1cad1de1 CP	19	#include <sound/pcm.h>
	20	#include <sound/pcm_params.h>
	21	#include <sound/soc.h>
1cad1de1 CP	22	#include <sound/initval.h>
	23
	24	#include <sound/uda134x.h>
	25	#include <sound/l3.h>
	26
72f2b894	27	#include "uda134x.h"
1cad1de1 CP	28
1cad1de1 CP	29
1cad1de1 CP	30	#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
	31	#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE \| \
	32	SNDRV_PCM_FMTBIT_S18_3LE \| SNDRV_PCM_FMTBIT_S20_3LE)
	33
	34	struct uda134x_priv {
	35	int sysclk;
	36	int dai_fmt;
	37
	38	struct snd_pcm_substream *master_substream;
	39	struct snd_pcm_substream *slave_substream;
	40	};
	41
	42	/* In-data addresses are hard-coded into the reg-cache values */
	43	static const char uda134x_reg[UDA134X_REGS_NUM] = {
	44	/* Extended address registers */
	45	0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
	46	/* Status, data regs */
ed632ad3	47	0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
1cad1de1 CP	48	};
	49
	50	/*
	51	* The codec has no support for reading its registers except for peak level...
	52	*/
	53	static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
	54	unsigned int reg)
	55	{
	56	u8 *cache = codec->reg_cache;
	57
	58	if (reg >= UDA134X_REGS_NUM)
	59	return -1;
	60	return cache[reg];
	61	}
	62
	63	/*
	64	* Write the register cache
	65	*/
	66	static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
	67	u8 reg, unsigned int value)
	68	{
	69	u8 *cache = codec->reg_cache;
	70
	71	if (reg >= UDA134X_REGS_NUM)
	72	return;
	73	cache[reg] = value;
	74	}
	75
	76	/*
	77	* Write to the uda134x registers
	78	*
	79	*/
	80	static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
	81	unsigned int value)
	82	{
	83	int ret;
	84	u8 addr;
	85	u8 data = value;
	86	struct uda134x_platform_data *pd = codec->control_data;
	87
	88	pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);
	89
	90	if (reg >= UDA134X_REGS_NUM) {
af901ca1	91	printk(KERN_ERR "%s unknown register: reg: %u",
1cad1de1 CP	92	__func__, reg);
	93	return -EINVAL;
	94	}
	95
	96	uda134x_write_reg_cache(codec, reg, value);
	97
	98	switch (reg) {
	99	case UDA134X_STATUS0:
	100	case UDA134X_STATUS1:
	101	addr = UDA134X_STATUS_ADDR;
	102	break;
	103	case UDA134X_DATA000:
	104	case UDA134X_DATA001:
	105	case UDA134X_DATA010:
ed632ad3	106	case UDA134X_DATA011:
1cad1de1 CP	107	addr = UDA134X_DATA0_ADDR;
	108	break;
	109	case UDA134X_DATA1:
	110	addr = UDA134X_DATA1_ADDR;
	111	break;
	112	default:
	113	/* It's an extended address register */
	114	addr = (reg \| UDA134X_EXTADDR_PREFIX);
	115
	116	ret = l3_write(&pd->l3,
	117	UDA134X_DATA0_ADDR, &addr, 1);
	118	if (ret != 1)
	119	return -EIO;
	120
	121	addr = UDA134X_DATA0_ADDR;
	122	data = (value \| UDA134X_EXTDATA_PREFIX);
	123	break;
	124	}
	125
	126	ret = l3_write(&pd->l3,
	127	addr, &data, 1);
	128	if (ret != 1)
	129	return -EIO;
	130
	131	return 0;
	132	}
	133
	134	static inline void uda134x_reset(struct snd_soc_codec *codec)
	135	{
	136	u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	137	uda134x_write(codec, UDA134X_STATUS0, reset_reg \| (1<<6));
	138	msleep(1);
	139	uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
	140	}
	141
	142	static int uda134x_mute(struct snd_soc_dai *dai, int mute)
	143	{
	144	struct snd_soc_codec *codec = dai->codec;
	145	u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);
	146
	147	pr_debug("%s mute: %d\n", __func__, mute);
	148
	149	if (mute)
	150	mute_reg \|= (1<<2);
	151	else
	152	mute_reg &= ~(1<<2);
	153
0c093fb5	154	uda134x_write(codec, UDA134X_DATA010, mute_reg);
1cad1de1 CP	155
	156	return 0;
	157	}
	158
dee89c4d MB	159	static int uda134x_startup(struct snd_pcm_substream *substream,
dee89c4d MB	160	struct snd_soc_dai *dai)
1cad1de1	161	{
e6968a17	162	struct snd_soc_codec *codec = dai->codec;
b2c812e2	163	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	164	struct snd_pcm_runtime *master_runtime;
	165
	166	if (uda134x->master_substream) {
	167	master_runtime = uda134x->master_substream->runtime;
	168
	169	pr_debug("%s constraining to %d bits at %d\n", __func__,
	170	master_runtime->sample_bits,
	171	master_runtime->rate);
	172
	173	snd_pcm_hw_constraint_minmax(substream->runtime,
	174	SNDRV_PCM_HW_PARAM_RATE,
	175	master_runtime->rate,
	176	master_runtime->rate);
	177
	178	snd_pcm_hw_constraint_minmax(substream->runtime,
	179	SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
	180	master_runtime->sample_bits,
	181	master_runtime->sample_bits);
	182
	183	uda134x->slave_substream = substream;
	184	} else
	185	uda134x->master_substream = substream;
	186
	187	return 0;
	188	}
	189
dee89c4d MB	190	static void uda134x_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	191	struct snd_soc_dai *dai)
1cad1de1	192	{
e6968a17	193	struct snd_soc_codec *codec = dai->codec;
b2c812e2	194	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	195
	196	if (uda134x->master_substream == substream)
	197	uda134x->master_substream = uda134x->slave_substream;
	198
	199	uda134x->slave_substream = NULL;
	200	}
	201
	202	static int uda134x_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	203	struct snd_pcm_hw_params *params,
dee89c4d MB	204	struct snd_soc_dai *dai)
1cad1de1 CP	205	{
1cad1de1 CP	206	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad	207	struct snd_soc_codec *codec = rtd->codec;
b2c812e2	208	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	209	u8 hw_params;
	210
	211	if (substream == uda134x->slave_substream) {
	212	pr_debug("%s ignoring hw_params for slave substream\n",
	213	__func__);
	214	return 0;
	215	}
	216
	217	hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	218	hw_params &= STATUS0_SYSCLK_MASK;
	219	hw_params &= STATUS0_DAIFMT_MASK;
	220
	221	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
	222	uda134x->sysclk, params_rate(params));
	223
	224	/* set SYSCLK / fs ratio */
	225	switch (uda134x->sysclk / params_rate(params)) {
	226	case 512:
	227	break;
	228	case 384:
	229	hw_params \|= (1<<4);
	230	break;
	231	case 256:
	232	hw_params \|= (1<<5);
	233	break;
	234	default:
	235	printk(KERN_ERR "%s unsupported fs\n", __func__);
	236	return -EINVAL;
	237	}
	238
	239	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
	240	uda134x->dai_fmt, params_format(params));
	241
	242	/* set DAI format and word length */
	243	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	244	case SND_SOC_DAIFMT_I2S:
	245	break;
	246	case SND_SOC_DAIFMT_RIGHT_J:
	247	switch (params_format(params)) {
	248	case SNDRV_PCM_FORMAT_S16_LE:
	249	hw_params \|= (1<<1);
	250	break;
	251	case SNDRV_PCM_FORMAT_S18_3LE:
	252	hw_params \|= (1<<2);
	253	break;
	254	case SNDRV_PCM_FORMAT_S20_3LE:
	255	hw_params \|= ((1<<2) \| (1<<1));
	256	break;
	257	default:
	258	printk(KERN_ERR "%s unsupported format (right)\n",
	259	__func__);
	260	return -EINVAL;
	261	}
	262	break;
	263	case SND_SOC_DAIFMT_LEFT_J:
	264	hw_params \|= (1<<3);
	265	break;
	266	default:
	267	printk(KERN_ERR "%s unsupported format\n", __func__);
	268	return -EINVAL;
	269	}
	270
	271	uda134x_write(codec, UDA134X_STATUS0, hw_params);
	272
273	return 0;
274	}
275
276	static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
277	int clk_id, unsigned int freq, int dir)
278	{
279	struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2	280	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1	281
449bd54d	282	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
1cad1de1 CP	283	clk_id, freq, dir);
	284
	285	/* Anything between 256fs8Khz and 512fs48Khz should be acceptable
	286	because the codec is slave. Of course limitations of the clock
	287	master (the IIS controller) apply.
	288	We'll error out on set_hw_params if it's not OK */
	289	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
	290	uda134x->sysclk = freq;
	291	return 0;
	292	}
	293
	294	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
	295	return -EINVAL;
	296	}
	297
	298	static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
	299	unsigned int fmt)
	300	{
	301	struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2	302	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	303
	304	pr_debug("%s fmt: %08X\n", __func__, fmt);
	305
	306	/* codec supports only full slave mode */
	307	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
	308	printk(KERN_ERR "%s unsupported slave mode\n", __func__);
	309	return -EINVAL;
	310	}
	311
	312	/* no support for clock inversion */
	313	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
	314	printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
	315	return -EINVAL;
	316	}
	317
	318	/* We can't setup DAI format here as it depends on the word bit num */
	319	/* so let's just store the value for later */
	320	uda134x->dai_fmt = fmt;
	321
	322	return 0;
	323	}
	324
	325	static int uda134x_set_bias_level(struct snd_soc_codec *codec,
	326	enum snd_soc_bias_level level)
	327	{
	328	u8 reg;
	329	struct uda134x_platform_data *pd = codec->control_data;
	330	int i;
	331	u8 *cache = codec->reg_cache;
	332
	333	pr_debug("%s bias level %d\n", __func__, level);
	334
	335	switch (level) {
	336	case SND_SOC_BIAS_ON:
	337	/* ADC, DAC on */
338de9d9 VZ	338	switch (pd->model) {
	339	case UDA134X_UDA1340:
	340	case UDA134X_UDA1344:
	341	case UDA134X_UDA1345:
	342	reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
	343	uda134x_write(codec, UDA134X_DATA011, reg \| 0x03);
	344	break;
	345	case UDA134X_UDA1341:
	346	reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
	347	uda134x_write(codec, UDA134X_STATUS1, reg \| 0x03);
	348	break;
	349	default:
	350	printk(KERN_ERR "UDA134X SoC codec: "
	351	"unsupported model %d\n", pd->model);
	352	return -EINVAL;
	353	}
1cad1de1 CP	354	break;
	355	case SND_SOC_BIAS_PREPARE:
	356	/* power on */
	357	if (pd->power) {
	358	pd->power(1);
	359	/* Sync reg_cache with the hardware */
	360	for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
f0fba2ad	361	codec->driver->write(codec, i, *cache++);
1cad1de1 CP	362	}
	363	break;
	364	case SND_SOC_BIAS_STANDBY:
	365	/* ADC, DAC power off */
338de9d9 VZ	366	switch (pd->model) {
	367	case UDA134X_UDA1340:
	368	case UDA134X_UDA1344:
	369	case UDA134X_UDA1345:
	370	reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
	371	uda134x_write(codec, UDA134X_DATA011, reg & ~(0x03));
	372	break;
	373	case UDA134X_UDA1341:
	374	reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
	375	uda134x_write(codec, UDA134X_STATUS1, reg & ~(0x03));
	376	break;
	377	default:
	378	printk(KERN_ERR "UDA134X SoC codec: "
	379	"unsupported model %d\n", pd->model);
	380	return -EINVAL;
	381	}
1cad1de1 CP	382	break;
	383	case SND_SOC_BIAS_OFF:
	384	/* power off */
	385	if (pd->power)
	386	pd->power(0);
	387	break;
	388	}
ce6120cc	389	codec->dapm.bias_level = level;
1cad1de1 CP	390	return 0;
	391	}
	392
	393	static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
	394	"Minimum2", "Maximum"};
	395	static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
	396	static const char *uda134x_mixmode[] = {"Differential", "Analog1",
	397	"Analog2", "Both"};
	398
	399	static const struct soc_enum uda134x_mixer_enum[] = {
	400	SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
	401	SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
	402	SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
	403	};
	404
	405	static const struct snd_kcontrol_new uda1341_snd_controls[] = {
	406	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	407	SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
	408	SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
	409	SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
	410
	411	SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
	412	SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
	413
	414	SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
	415	SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
	416
	417	SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
	418	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	419	SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
	420
	421	SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
	422	SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
	423	SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
	424
	425	SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
	426	SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
	427	SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
	428	SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
	429	SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
	430	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	431	};
	432
	433	static const struct snd_kcontrol_new uda1340_snd_controls[] = {
	434	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	435
	436	SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
	437	SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
	438
	439	SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
	440	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	441
	442	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	443	};
	444
b28528a1 VZ	445	static const struct snd_kcontrol_new uda1345_snd_controls[] = {
	446	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	447
	448	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	449
	450	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	451	};
	452
85e7652d	453	static const struct snd_soc_dai_ops uda134x_dai_ops = {
6335d055 EM	454	.startup = uda134x_startup,
	455	.shutdown = uda134x_shutdown,
	456	.hw_params = uda134x_hw_params,
	457	.digital_mute = uda134x_mute,
	458	.set_sysclk = uda134x_set_dai_sysclk,
	459	.set_fmt = uda134x_set_dai_fmt,
	460	};
	461
f0fba2ad LG	462	static struct snd_soc_dai_driver uda134x_dai = {
f0fba2ad LG	463	.name = "uda134x-hifi",
1cad1de1 CP	464	/* playback capabilities */
	465	.playback = {
	466	.stream_name = "Playback",
	467	.channels_min = 1,
	468	.channels_max = 2,
	469	.rates = UDA134X_RATES,
	470	.formats = UDA134X_FORMATS,
	471	},
	472	/* capture capabilities */
	473	.capture = {
	474	.stream_name = "Capture",
	475	.channels_min = 1,
	476	.channels_max = 2,
	477	.rates = UDA134X_RATES,
	478	.formats = UDA134X_FORMATS,
	479	},
	480	/* pcm operations */
6335d055	481	.ops = &uda134x_dai_ops,
1cad1de1	482	};
1cad1de1	483
f0fba2ad	484	static int uda134x_soc_probe(struct snd_soc_codec *codec)
1cad1de1	485	{
1cad1de1	486	struct uda134x_priv *uda134x;
a110f4ef MB	487	struct uda134x_platform_data *pd = codec->card->dev->platform_data;
a110f4ef MB	488
f0fba2ad	489	int ret;
1cad1de1 CP	490
	491	printk(KERN_INFO "UDA134X SoC Audio Codec\n");
	492
f0fba2ad	493	if (!pd) {
1cad1de1 CP	494	printk(KERN_ERR "UDA134X SoC codec: "
	495	"missing L3 bitbang function\n");
	496	return -ENODEV;
	497	}
	498
1cad1de1 CP	499	switch (pd->model) {
	500	case UDA134X_UDA1340:
	501	case UDA134X_UDA1341:
	502	case UDA134X_UDA1344:
b28528a1	503	case UDA134X_UDA1345:
1cad1de1 CP	504	break;
	505	default:
	506	printk(KERN_ERR "UDA134X SoC codec: "
	507	"unsupported model %d\n",
	508	pd->model);
	509	return -EINVAL;
	510	}
	511
1cad1de1 CP	512	uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
1cad1de1 CP	513	if (uda134x == NULL)
f0fba2ad	514	return -ENOMEM;
b2c812e2	515	snd_soc_codec_set_drvdata(codec, uda134x);
1cad1de1	516
f0fba2ad	517	codec->control_data = pd;
1cad1de1 CP	518
	519	if (pd->power)
	520	pd->power(1);
	521
	522	uda134x_reset(codec);
	523
f0fba2ad	524	if (pd->is_powered_on_standby)
e4295b40	525	uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
f0fba2ad	526	else
e4295b40	527	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1cad1de1	528
3e8e1952 IM	529	switch (pd->model) {
	530	case UDA134X_UDA1340:
	531	case UDA134X_UDA1344:
022658be	532	ret = snd_soc_add_codec_controls(codec, uda1340_snd_controls,
3e8e1952 IM	533	ARRAY_SIZE(uda1340_snd_controls));
	534	break;
	535	case UDA134X_UDA1341:
022658be	536	ret = snd_soc_add_codec_controls(codec, uda1341_snd_controls,
3e8e1952 IM	537	ARRAY_SIZE(uda1341_snd_controls));
3e8e1952 IM	538	break;
b28528a1	539	case UDA134X_UDA1345:
022658be	540	ret = snd_soc_add_codec_controls(codec, uda1345_snd_controls,
b28528a1 VZ	541	ARRAY_SIZE(uda1345_snd_controls));
b28528a1 VZ	542	break;
3e8e1952	543	default:
af901ca1	544	printk(KERN_ERR "%s unknown codec type: %d",
3e8e1952	545	__func__, pd->model);
f0fba2ad LG	546	kfree(uda134x);
f0fba2ad LG	547	return -EINVAL;
3e8e1952 IM	548	}
3e8e1952 IM	549
1cad1de1 CP	550	if (ret < 0) {
1cad1de1 CP	551	printk(KERN_ERR "UDA134X: failed to register controls\n");
f0fba2ad LG	552	kfree(uda134x);
f0fba2ad LG	553	return ret;
1cad1de1 CP	554	}
1cad1de1 CP	555
1cad1de1	556	return 0;
1cad1de1 CP	557	}
	558
	559	/* power down chip */
f0fba2ad	560	static int uda134x_soc_remove(struct snd_soc_codec *codec)
1cad1de1	561	{
f0fba2ad	562	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	563
	564	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	565	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
	566
f0fba2ad	567	kfree(uda134x);
1cad1de1 CP	568	return 0;
	569	}
	570
	571	#if defined(CONFIG_PM)
84b315ee	572	static int uda134x_soc_suspend(struct snd_soc_codec *codec)
1cad1de1	573	{
1cad1de1 CP	574	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	575	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
	576	return 0;
	577	}
	578
f0fba2ad	579	static int uda134x_soc_resume(struct snd_soc_codec *codec)
1cad1de1	580	{
1cad1de1 CP	581	uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
	582	uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
	583	return 0;
	584	}
	585	#else
	586	#define uda134x_soc_suspend NULL
	587	#define uda134x_soc_resume NULL
	588	#endif /* CONFIG_PM */
	589
f0fba2ad	590	static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
1cad1de1 CP	591	.probe = uda134x_soc_probe,
	592	.remove = uda134x_soc_remove,
	593	.suspend = uda134x_soc_suspend,
	594	.resume = uda134x_soc_resume,
f0fba2ad LG	595	.reg_cache_size = sizeof(uda134x_reg),
f0fba2ad LG	596	.reg_word_size = sizeof(u8),
2811fe2b	597	.reg_cache_default = uda134x_reg,
f0fba2ad LG	598	.reg_cache_step = 1,
	599	.read = uda134x_read_reg_cache,
	600	.write = uda134x_write,
f0fba2ad	601	.set_bias_level = uda134x_set_bias_level,
f0fba2ad LG	602	};
f0fba2ad LG	603
7a79e94e	604	static int uda134x_codec_probe(struct platform_device *pdev)
f0fba2ad LG	605	{
	606	return snd_soc_register_codec(&pdev->dev,
	607	&soc_codec_dev_uda134x, &uda134x_dai, 1);
	608	}
	609
7a79e94e	610	static int uda134x_codec_remove(struct platform_device *pdev)
f0fba2ad LG	611	{
	612	snd_soc_unregister_codec(&pdev->dev);
	613	return 0;
	614	}
	615
	616	static struct platform_driver uda134x_codec_driver = {
	617	.driver = {
	618	.name = "uda134x-codec",
	619	.owner = THIS_MODULE,
	620	},
	621	.probe = uda134x_codec_probe,
7a79e94e	622	.remove = uda134x_codec_remove,
1cad1de1	623	};
1cad1de1	624
5bbcc3c0	625	module_platform_driver(uda134x_codec_driver);
64089b84	626
1cad1de1 CP	627	MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
	628	MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
	629	MODULE_LICENSE("GPL");