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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
b07682b6 29#include <linux/i2c/twl.h>
5a0e3ad6 30#include <linux/slab.h>
cc17557e
SS		 31#include <sound/core.h>
32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/soc.h>
35#include <sound/soc-dapm.h>
36#include <sound/initval.h>
c10b82cf 37#include <sound/tlv.h>
cc17557e
SS		 38
39#include "twl4030.h"
40
41/*
42 * twl4030 register cache & default register settings
43 */
44static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
45 0x00, /* this register not used */
db04e2c5 46 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 47 0xc3, /* REG_OPTION (0x2) */
48 0x00, /* REG_UNKNOWN (0x3) */
49 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 50 0x20, /* REG_ANAMICL (0x5) */
51 0x00, /* REG_ANAMICR (0x6) */
52 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 53 0x00, /* REG_ADCMICSEL (0x8) */
54 0x00, /* REG_DIGMIXING (0x9) */
55 0x0c, /* REG_ATXL1PGA (0xA) */
56 0x0c, /* REG_ATXR1PGA (0xB) */
57 0x00, /* REG_AVTXL2PGA (0xC) */
58 0x00, /* REG_AVTXR2PGA (0xD) */
c42a59ea 59 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e
SS		 60 0x00, /* REG_VOICE_IF (0xF) */
61 0x00, /* REG_ARXR1PGA (0x10) */
62 0x00, /* REG_ARXL1PGA (0x11) */
63 0x6c, /* REG_ARXR2PGA (0x12) */
64 0x6c, /* REG_ARXL2PGA (0x13) */
65 0x00, /* REG_VRXPGA (0x14) */
66 0x00, /* REG_VSTPGA (0x15) */
67 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 68 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e
SS		 69 0x00, /* REG_ARX2VTXPGA (0x18) */
70 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
71 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
c8124593
PU		 72 0x4a, /* REG_ARXL2_APGA_CTL (0x1B) */
73 0x4a, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 74 0x00, /* REG_ATX2ARXPGA (0x1D) */
75 0x00, /* REG_BT_IF (0x1E) */
76 0x00, /* REG_BTPGA (0x1F) */
77 0x00, /* REG_BTSTPGA (0x20) */
78 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 79 0x00, /* REG_HS_SEL (0x22) */
80 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 81 0x00, /* REG_HS_POPN_SET (0x24) */
82 0x00, /* REG_PREDL_CTL (0x25) */
83 0x00, /* REG_PREDR_CTL (0x26) */
84 0x00, /* REG_PRECKL_CTL (0x27) */
85 0x00, /* REG_PRECKR_CTL (0x28) */
86 0x00, /* REG_HFL_CTL (0x29) */
87 0x00, /* REG_HFR_CTL (0x2A) */
88 0x00, /* REG_ALC_CTL (0x2B) */
89 0x00, /* REG_ALC_SET1 (0x2C) */
90 0x00, /* REG_ALC_SET2 (0x2D) */
91 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 92 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 93 0x00, /* REG_DTMF_FREQSEL (0x30) */
94 0x00, /* REG_DTMF_TONEXT1H (0x31) */
95 0x00, /* REG_DTMF_TONEXT1L (0x32) */
96 0x00, /* REG_DTMF_TONEXT2H (0x33) */
97 0x00, /* REG_DTMF_TONEXT2L (0x34) */
98 0x00, /* REG_DTMF_TONOFF (0x35) */
99 0x00, /* REG_DTMF_WANONOFF (0x36) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
102 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 103 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e
SS		 104 0x00, /* REG_DTMF_CTL (0x3B) */
105 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
106 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
107 0x00, /* REG_MISC_SET_1 (0x3E) */
108 0x00, /* REG_PCMBTMUX (0x3F) */
109 0x00, /* not used (0x40) */
110 0x00, /* not used (0x41) */
111 0x00, /* not used (0x42) */
112 0x00, /* REG_RX_PATH_SEL (0x43) */
113 0x00, /* REG_VDL_APGA_CTL (0x44) */
114 0x00, /* REG_VIBRA_CTL (0x45) */
115 0x00, /* REG_VIBRA_SET (0x46) */
116 0x00, /* REG_VIBRA_PWM_SET (0x47) */
117 0x00, /* REG_ANAMIC_GAIN (0x48) */
118 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 119 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 120};
121
7393958f
PU		 122/* codec private data */
123struct twl4030_priv {
7a1fecf5
PU		 124 struct snd_soc_codec codec;
125
7393958f 126 unsigned int codec_powered;
2845fa13 127 unsigned int apll_enabled;
7220b9f4
PU		 128
129 struct snd_pcm_substream *master_substream;
130 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 131
132 unsigned int configured;
133 unsigned int rate;
134 unsigned int sample_bits;
135 unsigned int channels;
6943c92e
PU		 136
137 unsigned int sysclk;
138
139 /* Headset output state handling */
140 unsigned int hsl_enabled;
141 unsigned int hsr_enabled;
7393958f
PU		 142};
143
cc17557e
SS		 144/*
145 * read twl4030 register cache
146 */
147static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
148 unsigned int reg)
149{
d08664fd 150 u8 *cache = codec->reg_cache;
cc17557e 151
91432e97
IM		 152 if (reg >= TWL4030_CACHEREGNUM)
153 return -EIO;
154
cc17557e
SS		 155 return cache[reg];
156}
157
158/*
159 * write twl4030 register cache
160 */
161static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
162 u8 reg, u8 value)
163{
164 u8 *cache = codec->reg_cache;
165
166 if (reg >= TWL4030_CACHEREGNUM)
167 return;
168 cache[reg] = value;
169}
170
171/*
172 * write to the twl4030 register space
173 */
174static int twl4030_write(struct snd_soc_codec *codec,
175 unsigned int reg, unsigned int value)
176{
177 twl4030_write_reg_cache(codec, reg, value);
f3b5d300 178 if (likely(reg < TWL4030_REG_SW_SHADOW))
fc7b92fc 179 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
f3b5d300
PU		 180 reg);
181 else
182 return 0;
cc17557e
SS		 183}
184
db04e2c5 185static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 186{
7393958f 187 struct twl4030_priv *twl4030 = codec->private_data;
7a1fecf5 188 int mode;
cc17557e 189
7393958f
PU		 190 if (enable == twl4030->codec_powered)
191 return;
192
db04e2c5 193 if (enable)
7a1fecf5 194 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
db04e2c5 195 else
7a1fecf5 196 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
cc17557e 197
7a1fecf5
PU		 198 if (mode >= 0) {
199 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
200 twl4030->codec_powered = enable;
201 }
cc17557e
SS		 202
203 /* REVISIT: this delay is present in TI sample drivers */
204 /* but there seems to be no TRM requirement for it */
205 udelay(10);
206}
207
208static void twl4030_init_chip(struct snd_soc_codec *codec)
209{
16a30fbb 210 u8 *cache = codec->reg_cache;
cc17557e
SS		 211 int i;
212
213 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 214 twl4030_codec_enable(codec, 0);
cc17557e
SS		 215
216 /* set all audio section registers to reasonable defaults */
217 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
68d01955
PU		 218 if (i != TWL4030_REG_APLL_CTL)
219 twl4030_write(codec, i, cache[i]);
cc17557e
SS		 220
221}
222
2845fa13 223static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
7393958f
PU		 224{
225 struct twl4030_priv *twl4030 = codec->private_data;
7a1fecf5 226 int status;
7393958f 227
2845fa13 228 if (enable == twl4030->apll_enabled)
7393958f
PU		 229 return;
230
2845fa13 231 if (enable)
7393958f 232 /* Enable PLL */
7a1fecf5 233 status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL);
2845fa13
PU		 234 else
235 /* Disable PLL */
236 status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL);
7a1fecf5
PU		 237
238 if (status >= 0)
239 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
7393958f 240
2845fa13 241 twl4030->apll_enabled = enable;
7393958f
PU		 242}
243
006f367e
PU		 244static void twl4030_power_up(struct snd_soc_codec *codec)
245{
7393958f 246 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 247 u8 anamicl, regmisc1, byte;
248 int i = 0;
249
7393958f
PU		 250 if (twl4030->codec_powered)
251 return;
252
006f367e
PU		 253 /* set CODECPDZ to turn on codec */
254 twl4030_codec_enable(codec, 1);
255
256 /* initiate offset cancellation */
257 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
258 twl4030_write(codec, TWL4030_REG_ANAMICL,
259 anamicl | TWL4030_CNCL_OFFSET_START);
260
261 /* wait for offset cancellation to complete */
262 do {
263 /* this takes a little while, so don't slam i2c */
264 udelay(2000);
fc7b92fc 265 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 266 TWL4030_REG_ANAMICL);
267 } while ((i++ < 100) &&
268 ((byte & TWL4030_CNCL_OFFSET_START) ==
269 TWL4030_CNCL_OFFSET_START));
270
271 /* Make sure that the reg_cache has the same value as the HW */
272 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
273
274 /* anti-pop when changing analog gain */
275 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
276 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
277 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
278
279 /* toggle CODECPDZ as per TRM */
280 twl4030_codec_enable(codec, 0);
281 twl4030_codec_enable(codec, 1);
282}
283
7393958f
PU		 284/*
285 * Unconditional power down
286 */
006f367e
PU		 287static void twl4030_power_down(struct snd_soc_codec *codec)
288{
289 /* power down */
290 twl4030_codec_enable(codec, 0);
291}
292
5e98a464 293/* Earpiece */
1a787e7a
JS		 294static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
295 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
296 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
297 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
298 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
299};
5e98a464 300
2a6f5c58 301/* PreDrive Left */
1a787e7a
JS		 302static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
303 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
304 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
305 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
306 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
307};
2a6f5c58
PU		 308
309/* PreDrive Right */
1a787e7a
JS		 310static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
311 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
312 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
313 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
314 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
315};
2a6f5c58 316
dfad21a2 317/* Headset Left */
1a787e7a
JS		 318static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
319 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
320 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
321 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
322};
dfad21a2
PU		 323
324/* Headset Right */
1a787e7a
JS		 325static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
326 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
327 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
328 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
329};
dfad21a2 330
5152d8c2 331/* Carkit Left */
1a787e7a
JS		 332static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
333 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
334 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
335 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
336};
5152d8c2
PU		 337
338/* Carkit Right */
1a787e7a
JS		 339static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
340 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
341 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
342 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
343};
5152d8c2 344
df339804
PU		 345/* Handsfree Left */
346static const char *twl4030_handsfreel_texts[] =
1a787e7a 347 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 348
349static const struct soc_enum twl4030_handsfreel_enum =
350 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
351 ARRAY_SIZE(twl4030_handsfreel_texts),
352 twl4030_handsfreel_texts);
353
354static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
355SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
356
0f89bdca
PU		 357/* Handsfree Left virtual mute */
358static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
359 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
360
df339804
PU		 361/* Handsfree Right */
362static const char *twl4030_handsfreer_texts[] =
1a787e7a 363 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 364
365static const struct soc_enum twl4030_handsfreer_enum =
366 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
367 ARRAY_SIZE(twl4030_handsfreer_texts),
368 twl4030_handsfreer_texts);
369
370static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
371SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
372
0f89bdca
PU		 373/* Handsfree Right virtual mute */
374static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
375 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
376
376f7839
PU		 377/* Vibra */
378/* Vibra audio path selection */
379static const char *twl4030_vibra_texts[] =
380 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
381
382static const struct soc_enum twl4030_vibra_enum =
383 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
384 ARRAY_SIZE(twl4030_vibra_texts),
385 twl4030_vibra_texts);
386
387static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
388SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
389
390/* Vibra path selection: local vibrator (PWM) or audio driven */
391static const char *twl4030_vibrapath_texts[] =
392 {"Local vibrator", "Audio"};
393
394static const struct soc_enum twl4030_vibrapath_enum =
395 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
396 ARRAY_SIZE(twl4030_vibrapath_texts),
397 twl4030_vibrapath_texts);
398
399static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
400SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
401
276c6222 402/* Left analog microphone selection */
97b8096d 403static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 404 SOC_DAPM_SINGLE("Main Mic Capture Switch",
405 TWL4030_REG_ANAMICL, 0, 1, 0),
406 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
407 TWL4030_REG_ANAMICL, 1, 1, 0),
408 SOC_DAPM_SINGLE("AUXL Capture Switch",
409 TWL4030_REG_ANAMICL, 2, 1, 0),
410 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
411 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 412};
276c6222
PU		 413
414/* Right analog microphone selection */
97b8096d 415static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 416 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
417 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 418};
276c6222
PU		 419
420/* TX1 L/R Analog/Digital microphone selection */
421static const char *twl4030_micpathtx1_texts[] =
422 {"Analog", "Digimic0"};
423
424static const struct soc_enum twl4030_micpathtx1_enum =
425 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
426 ARRAY_SIZE(twl4030_micpathtx1_texts),
427 twl4030_micpathtx1_texts);
428
429static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
430SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
431
432/* TX2 L/R Analog/Digital microphone selection */
433static const char *twl4030_micpathtx2_texts[] =
434 {"Analog", "Digimic1"};
435
436static const struct soc_enum twl4030_micpathtx2_enum =
437 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
438 ARRAY_SIZE(twl4030_micpathtx2_texts),
439 twl4030_micpathtx2_texts);
440
441static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
442SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
443
7393958f
PU		 444/* Analog bypass for AudioR1 */
445static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
446 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
447
448/* Analog bypass for AudioL1 */
449static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
450 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
451
452/* Analog bypass for AudioR2 */
453static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
454 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
455
456/* Analog bypass for AudioL2 */
457static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
458 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
459
fcd274a3
LCM		 460/* Analog bypass for Voice */
461static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
462 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
463
6bab83fd
PU		 464/* Digital bypass gain, 0 mutes the bypass */
465static const unsigned int twl4030_dapm_dbypass_tlv[] = {
466 TLV_DB_RANGE_HEAD(2),
467 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
468 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
469};
470
471/* Digital bypass left (TX1L -> RX2L) */
472static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
473 SOC_DAPM_SINGLE_TLV("Volume",
474 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
475 twl4030_dapm_dbypass_tlv);
476
477/* Digital bypass right (TX1R -> RX2R) */
478static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
479 SOC_DAPM_SINGLE_TLV("Volume",
480 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
481 twl4030_dapm_dbypass_tlv);
482
ee8f6894
LCM		 483/*
484 * Voice Sidetone GAIN volume control:
485 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
486 */
487static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
488
489/* Digital bypass voice: sidetone (VUL -> VDL)*/
490static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
491 SOC_DAPM_SINGLE_TLV("Volume",
492 TWL4030_REG_VSTPGA, 0, 0x29, 0,
493 twl4030_dapm_dbypassv_tlv);
494
276c6222
PU		 495static int micpath_event(struct snd_soc_dapm_widget *w,
496 struct snd_kcontrol *kcontrol, int event)
497{
498 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
499 unsigned char adcmicsel, micbias_ctl;
500
501 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
502 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
503 /* Prepare the bits for the given TX path:
504 * shift_l == 0: TX1 microphone path
505 * shift_l == 2: TX2 microphone path */
506 if (e->shift_l) {
507 /* TX2 microphone path */
508 if (adcmicsel & TWL4030_TX2IN_SEL)
509 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
510 else
511 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
512 } else {
513 /* TX1 microphone path */
514 if (adcmicsel & TWL4030_TX1IN_SEL)
515 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
516 else
517 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
518 }
519
520 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
521
522 return 0;
523}
524
9008adf9
PU		 525/*
526 * Output PGA builder:
527 * Handle the muting and unmuting of the given output (turning off the
528 * amplifier associated with the output pin)
529 * On mute bypass the reg_cache and mute the volume
530 * On unmute: restore the register content
531 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
532 */
533#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
534static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
535 struct snd_kcontrol *kcontrol, int event) \
536{ \
537 u8 reg_val; \
538 \
539 switch (event) { \
540 case SND_SOC_DAPM_POST_PMU: \
541 twl4030_write(w->codec, reg, \
542 twl4030_read_reg_cache(w->codec, reg)); \
543 break; \
544 case SND_SOC_DAPM_POST_PMD: \
545 reg_val = twl4030_read_reg_cache(w->codec, reg); \
fc7b92fc 546 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
9008adf9
PU		 547 reg_val & (~mask), \
548 reg); \
549 break; \
550 } \
551 return 0; \
552}
553
554TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
555TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
556TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
557TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
558TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
559
5a2e9a48 560static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 561{
49d92c7d
SM		 562 unsigned char hs_ctl;
563
5a2e9a48 564 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 565
5a2e9a48
PU		 566 if (ramp) {
567 /* HF ramp-up */
568 hs_ctl |= TWL4030_HF_CTL_REF_EN;
569 twl4030_write(codec, reg, hs_ctl);
570 udelay(10);
49d92c7d 571 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 572 twl4030_write(codec, reg, hs_ctl);
573 udelay(40);
49d92c7d 574 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 575 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 576 twl4030_write(codec, reg, hs_ctl);
49d92c7d 577 } else {
5a2e9a48
PU		 578 /* HF ramp-down */
579 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
580 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
581 twl4030_write(codec, reg, hs_ctl);
582 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
583 twl4030_write(codec, reg, hs_ctl);
584 udelay(40);
585 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
586 twl4030_write(codec, reg, hs_ctl);
49d92c7d 587 }
5a2e9a48 588}
49d92c7d 589
5a2e9a48
PU		 590static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
591 struct snd_kcontrol *kcontrol, int event)
592{
593 switch (event) {
594 case SND_SOC_DAPM_POST_PMU:
595 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
596 break;
597 case SND_SOC_DAPM_POST_PMD:
598 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
599 break;
600 }
601 return 0;
602}
603
604static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
605 struct snd_kcontrol *kcontrol, int event)
606{
607 switch (event) {
608 case SND_SOC_DAPM_POST_PMU:
609 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
610 break;
611 case SND_SOC_DAPM_POST_PMD:
612 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
613 break;
614 }
49d92c7d
SM		 615 return 0;
616}
617
86139a13
JV		 618static int vibramux_event(struct snd_soc_dapm_widget *w,
619 struct snd_kcontrol *kcontrol, int event)
620{
621 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
622 return 0;
623}
624
7729cf74
PU		 625static int apll_event(struct snd_soc_dapm_widget *w,
626 struct snd_kcontrol *kcontrol, int event)
627{
628 switch (event) {
629 case SND_SOC_DAPM_PRE_PMU:
630 twl4030_apll_enable(w->codec, 1);
631 break;
632 case SND_SOC_DAPM_POST_PMD:
633 twl4030_apll_enable(w->codec, 0);
634 break;
635 }
636 return 0;
637}
638
6943c92e 639static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 640{
4e49ffd1
CVJ		 641 struct snd_soc_device *socdev = codec->socdev;
642 struct twl4030_setup_data *setup = socdev->codec_data;
643
aad749e5 644 unsigned char hs_gain, hs_pop;
6943c92e
PU		 645 struct twl4030_priv *twl4030 = codec->private_data;
646 /* Base values for ramp delay calculation: 2^19 - 2^26 */
647 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
648 8388608, 16777216, 33554432, 67108864};
aad749e5 649
6943c92e
PU		 650 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
651 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 652
4e49ffd1
CVJ		 653 /* Enable external mute control, this dramatically reduces
654 * the pop-noise */
655 if (setup && setup->hs_extmute) {
656 if (setup->set_hs_extmute) {
657 setup->set_hs_extmute(1);
658 } else {
659 hs_pop |= TWL4030_EXTMUTE;
660 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
661 }
662 }
663
6943c92e
PU		 664 if (ramp) {
665 /* Headset ramp-up according to the TRM */
aad749e5 666 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 667 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
668 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 669 hs_pop |= TWL4030_RAMP_EN;
6943c92e 670 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 671 /* Wait ramp delay time + 1, so the VMID can settle */
672 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
673 twl4030->sysclk) + 1);
6943c92e
PU		 674 } else {
675 /* Headset ramp-down _not_ according to
676 * the TRM, but in a way that it is working */
aad749e5 677 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 678 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
679 /* Wait ramp delay time + 1, so the VMID can settle */
680 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
681 twl4030->sysclk) + 1);
aad749e5 682 /* Bypass the reg_cache to mute the headset */
fc7b92fc 683 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 684 hs_gain & (~0x0f),
685 TWL4030_REG_HS_GAIN_SET);
6943c92e 686
aad749e5 687 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 688 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
689 }
4e49ffd1
CVJ		 690
691 /* Disable external mute */
692 if (setup && setup->hs_extmute) {
693 if (setup->set_hs_extmute) {
694 setup->set_hs_extmute(0);
695 } else {
696 hs_pop &= ~TWL4030_EXTMUTE;
697 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
698 }
699 }
6943c92e
PU		 700}
701
702static int headsetlpga_event(struct snd_soc_dapm_widget *w,
703 struct snd_kcontrol *kcontrol, int event)
704{
705 struct twl4030_priv *twl4030 = w->codec->private_data;
706
707 switch (event) {
708 case SND_SOC_DAPM_POST_PMU:
709 /* Do the ramp-up only once */
710 if (!twl4030->hsr_enabled)
711 headset_ramp(w->codec, 1);
712
713 twl4030->hsl_enabled = 1;
714 break;
715 case SND_SOC_DAPM_POST_PMD:
716 /* Do the ramp-down only if both headsetL/R is disabled */
717 if (!twl4030->hsr_enabled)
718 headset_ramp(w->codec, 0);
719
720 twl4030->hsl_enabled = 0;
721 break;
722 }
723 return 0;
724}
725
726static int headsetrpga_event(struct snd_soc_dapm_widget *w,
727 struct snd_kcontrol *kcontrol, int event)
728{
729 struct twl4030_priv *twl4030 = w->codec->private_data;
730
731 switch (event) {
732 case SND_SOC_DAPM_POST_PMU:
733 /* Do the ramp-up only once */
734 if (!twl4030->hsl_enabled)
735 headset_ramp(w->codec, 1);
736
737 twl4030->hsr_enabled = 1;
738 break;
739 case SND_SOC_DAPM_POST_PMD:
740 /* Do the ramp-down only if both headsetL/R is disabled */
741 if (!twl4030->hsl_enabled)
742 headset_ramp(w->codec, 0);
743
744 twl4030->hsr_enabled = 0;
aad749e5
PU		 745 break;
746 }
747 return 0;
748}
749
b0bd53a7
PU		 750/*
751 * Some of the gain controls in TWL (mostly those which are associated with
752 * the outputs) are implemented in an interesting way:
753 * 0x0 : Power down (mute)
754 * 0x1 : 6dB
755 * 0x2 : 0 dB
756 * 0x3 : -6 dB
757 * Inverting not going to help with these.
758 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
759 */
760#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
761 xinvert, tlv_array) \
762{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
763 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
764 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
765 .tlv.p = (tlv_array), \
766 .info = snd_soc_info_volsw, \
767 .get = snd_soc_get_volsw_twl4030, \
768 .put = snd_soc_put_volsw_twl4030, \
769 .private_value = (unsigned long)&(struct soc_mixer_control) \
770 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
771 .max = xmax, .invert = xinvert} }
772#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
773 xinvert, tlv_array) \
774{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
775 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
776 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
777 .tlv.p = (tlv_array), \
778 .info = snd_soc_info_volsw_2r, \
779 .get = snd_soc_get_volsw_r2_twl4030,\
780 .put = snd_soc_put_volsw_r2_twl4030, \
781 .private_value = (unsigned long)&(struct soc_mixer_control) \
782 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 783 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 784#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
785 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
786 xinvert, tlv_array)
787
788static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
789 struct snd_ctl_elem_value *ucontrol)
790{
791 struct soc_mixer_control *mc =
792 (struct soc_mixer_control *)kcontrol->private_value;
793 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
794 unsigned int reg = mc->reg;
795 unsigned int shift = mc->shift;
796 unsigned int rshift = mc->rshift;
797 int max = mc->max;
798 int mask = (1 << fls(max)) - 1;
799
800 ucontrol->value.integer.value[0] =
801 (snd_soc_read(codec, reg) >> shift) & mask;
802 if (ucontrol->value.integer.value[0])
803 ucontrol->value.integer.value[0] =
804 max + 1 - ucontrol->value.integer.value[0];
805
806 if (shift != rshift) {
807 ucontrol->value.integer.value[1] =
808 (snd_soc_read(codec, reg) >> rshift) & mask;
809 if (ucontrol->value.integer.value[1])
810 ucontrol->value.integer.value[1] =
811 max + 1 - ucontrol->value.integer.value[1];
812 }
813
814 return 0;
815}
816
817static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
818 struct snd_ctl_elem_value *ucontrol)
819{
820 struct soc_mixer_control *mc =
821 (struct soc_mixer_control *)kcontrol->private_value;
822 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
823 unsigned int reg = mc->reg;
824 unsigned int shift = mc->shift;
825 unsigned int rshift = mc->rshift;
826 int max = mc->max;
827 int mask = (1 << fls(max)) - 1;
828 unsigned short val, val2, val_mask;
829
830 val = (ucontrol->value.integer.value[0] & mask);
831
832 val_mask = mask << shift;
833 if (val)
834 val = max + 1 - val;
835 val = val << shift;
836 if (shift != rshift) {
837 val2 = (ucontrol->value.integer.value[1] & mask);
838 val_mask |= mask << rshift;
839 if (val2)
840 val2 = max + 1 - val2;
841 val |= val2 << rshift;
842 }
843 return snd_soc_update_bits(codec, reg, val_mask, val);
844}
845
846static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
847 struct snd_ctl_elem_value *ucontrol)
848{
849 struct soc_mixer_control *mc =
850 (struct soc_mixer_control *)kcontrol->private_value;
851 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
852 unsigned int reg = mc->reg;
853 unsigned int reg2 = mc->rreg;
854 unsigned int shift = mc->shift;
855 int max = mc->max;
856 int mask = (1<<fls(max))-1;
857
858 ucontrol->value.integer.value[0] =
859 (snd_soc_read(codec, reg) >> shift) & mask;
860 ucontrol->value.integer.value[1] =
861 (snd_soc_read(codec, reg2) >> shift) & mask;
862
863 if (ucontrol->value.integer.value[0])
864 ucontrol->value.integer.value[0] =
865 max + 1 - ucontrol->value.integer.value[0];
866 if (ucontrol->value.integer.value[1])
867 ucontrol->value.integer.value[1] =
868 max + 1 - ucontrol->value.integer.value[1];
869
870 return 0;
871}
872
873static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
874 struct snd_ctl_elem_value *ucontrol)
875{
876 struct soc_mixer_control *mc =
877 (struct soc_mixer_control *)kcontrol->private_value;
878 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
879 unsigned int reg = mc->reg;
880 unsigned int reg2 = mc->rreg;
881 unsigned int shift = mc->shift;
882 int max = mc->max;
883 int mask = (1 << fls(max)) - 1;
884 int err;
885 unsigned short val, val2, val_mask;
886
887 val_mask = mask << shift;
888 val = (ucontrol->value.integer.value[0] & mask);
889 val2 = (ucontrol->value.integer.value[1] & mask);
890
891 if (val)
892 val = max + 1 - val;
893 if (val2)
894 val2 = max + 1 - val2;
895
896 val = val << shift;
897 val2 = val2 << shift;
898
899 err = snd_soc_update_bits(codec, reg, val_mask, val);
900 if (err < 0)
901 return err;
902
903 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
904 return err;
905}
906
b74bd40f
LCM		 907/* Codec operation modes */
908static const char *twl4030_op_modes_texts[] = {
909 "Option 2 (voice/audio)", "Option 1 (audio)"
910};
911
912static const struct soc_enum twl4030_op_modes_enum =
913 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
914 ARRAY_SIZE(twl4030_op_modes_texts),
915 twl4030_op_modes_texts);
916
423c238d 917static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 918 struct snd_ctl_elem_value *ucontrol)
919{
920 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
921 struct twl4030_priv *twl4030 = codec->private_data;
922 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
923 unsigned short val;
924 unsigned short mask, bitmask;
925
926 if (twl4030->configured) {
927 printk(KERN_ERR "twl4030 operation mode cannot be "
928 "changed on-the-fly\n");
929 return -EBUSY;
930 }
931
932 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
933 ;
934 if (ucontrol->value.enumerated.item[0] > e->max - 1)
935 return -EINVAL;
936
937 val = ucontrol->value.enumerated.item[0] << e->shift_l;
938 mask = (bitmask - 1) << e->shift_l;
939 if (e->shift_l != e->shift_r) {
940 if (ucontrol->value.enumerated.item[1] > e->max - 1)
941 return -EINVAL;
942 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
943 mask |= (bitmask - 1) << e->shift_r;
944 }
945
946 return snd_soc_update_bits(codec, e->reg, mask, val);
947}
948
c10b82cf
PU		 949/*
950 * FGAIN volume control:
951 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
952 */
d889a72c 953static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 954
0d33ea0b
PU		 955/*
956 * CGAIN volume control:
957 * 0 dB to 12 dB in 6 dB steps
958 * value 2 and 3 means 12 dB
959 */
d889a72c
PU		 960static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
961
1a787e7a
JS		 962/*
963 * Voice Downlink GAIN volume control:
964 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
965 */
966static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
967
d889a72c
PU		 968/*
969 * Analog playback gain
970 * -24 dB to 12 dB in 2 dB steps
971 */
972static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 973
4290239c
PU		 974/*
975 * Gain controls tied to outputs
976 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
977 */
978static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
979
18cc8d8d
JS		 980/*
981 * Gain control for earpiece amplifier
982 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
983 */
984static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
985
381a22b5
PU		 986/*
987 * Capture gain after the ADCs
988 * from 0 dB to 31 dB in 1 dB steps
989 */
990static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
991
5920b453
GI		 992/*
993 * Gain control for input amplifiers
994 * 0 dB to 30 dB in 6 dB steps
995 */
996static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
997
328d0a13
LCM		 998/* AVADC clock priority */
999static const char *twl4030_avadc_clk_priority_texts[] = {
1000 "Voice high priority", "HiFi high priority"
1001};
1002
1003static const struct soc_enum twl4030_avadc_clk_priority_enum =
1004 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1005 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1006 twl4030_avadc_clk_priority_texts);
1007
89492be8
PU		 1008static const char *twl4030_rampdelay_texts[] = {
1009 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1010 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1011 "3495/2581/1748 ms"
1012};
1013
1014static const struct soc_enum twl4030_rampdelay_enum =
1015 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1016 ARRAY_SIZE(twl4030_rampdelay_texts),
1017 twl4030_rampdelay_texts);
1018
376f7839
PU		 1019/* Vibra H-bridge direction mode */
1020static const char *twl4030_vibradirmode_texts[] = {
1021 "Vibra H-bridge direction", "Audio data MSB",
1022};
1023
1024static const struct soc_enum twl4030_vibradirmode_enum =
1025 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1026 ARRAY_SIZE(twl4030_vibradirmode_texts),
1027 twl4030_vibradirmode_texts);
1028
1029/* Vibra H-bridge direction */
1030static const char *twl4030_vibradir_texts[] = {
1031 "Positive polarity", "Negative polarity",
1032};
1033
1034static const struct soc_enum twl4030_vibradir_enum =
1035 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1036 ARRAY_SIZE(twl4030_vibradir_texts),
1037 twl4030_vibradir_texts);
1038
cc17557e 1039static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1040 /* Codec operation mode control */
1041 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1042 snd_soc_get_enum_double,
1043 snd_soc_put_twl4030_opmode_enum_double),
1044
d889a72c
PU		 1045 /* Common playback gain controls */
1046 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1047 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1048 0, 0x3f, 0, digital_fine_tlv),
1049 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1050 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1051 0, 0x3f, 0, digital_fine_tlv),
1052
1053 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1054 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1055 6, 0x2, 0, digital_coarse_tlv),
1056 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1057 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1058 6, 0x2, 0, digital_coarse_tlv),
1059
1060 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1061 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1062 3, 0x12, 1, analog_tlv),
1063 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1064 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1065 3, 0x12, 1, analog_tlv),
44c55870
PU		 1066 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1067 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1068 1, 1, 0),
1069 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1070 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1071 1, 1, 0),
381a22b5 1072
1a787e7a
JS		 1073 /* Common voice downlink gain controls */
1074 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1075 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1076
1077 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1078 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1079
1080 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1081 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1082
4290239c
PU		 1083 /* Separate output gain controls */
1084 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1085 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1086 4, 3, 0, output_tvl),
1087
1088 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1089 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1090
1091 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1092 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1093 4, 3, 0, output_tvl),
1094
1095 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1096 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1097
381a22b5 1098 /* Common capture gain controls */
276c6222 1099 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1100 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1101 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1102 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1103 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1104 0, 0x1f, 0, digital_capture_tlv),
5920b453 1105
276c6222 1106 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1107 0, 3, 5, 0, input_gain_tlv),
89492be8 1108
328d0a13
LCM		 1109 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1110
89492be8 1111 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1112
1113 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1114 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1115};
1116
cc17557e 1117static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1118 /* Left channel inputs */
1119 SND_SOC_DAPM_INPUT("MAINMIC"),
1120 SND_SOC_DAPM_INPUT("HSMIC"),
1121 SND_SOC_DAPM_INPUT("AUXL"),
1122 SND_SOC_DAPM_INPUT("CARKITMIC"),
1123 /* Right channel inputs */
1124 SND_SOC_DAPM_INPUT("SUBMIC"),
1125 SND_SOC_DAPM_INPUT("AUXR"),
1126 /* Digital microphones (Stereo) */
1127 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1128 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1129
1130 /* Outputs */
cc17557e
SS		 1131 SND_SOC_DAPM_OUTPUT("OUTL"),
1132 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1133 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1134 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1135 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1136 SND_SOC_DAPM_OUTPUT("HSOL"),
1137 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1138 SND_SOC_DAPM_OUTPUT("CARKITL"),
1139 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1140 SND_SOC_DAPM_OUTPUT("HFL"),
1141 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1142 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1143
53b5047d 1144 /* DACs */
b4852b79 1145 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1146 SND_SOC_NOPM, 0, 0),
b4852b79 1147 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1148 SND_SOC_NOPM, 0, 0),
b4852b79 1149 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1150 SND_SOC_NOPM, 0, 0),
b4852b79 1151 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1152 SND_SOC_NOPM, 0, 0),
1a787e7a 1153 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1154 SND_SOC_NOPM, 0, 0),
cc17557e 1155
7393958f 1156 /* Analog bypasses */
78e08e2f
PU		 1157 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1158 &twl4030_dapm_abypassr1_control),
1159 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1160 &twl4030_dapm_abypassl1_control),
1161 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1162 &twl4030_dapm_abypassr2_control),
1163 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1164 &twl4030_dapm_abypassl2_control),
1165 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1166 &twl4030_dapm_abypassv_control),
1167
1168 /* Master analog loopback switch */
1169 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1170 NULL, 0),
7393958f 1171
6bab83fd 1172 /* Digital bypasses */
78e08e2f
PU		 1173 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1174 &twl4030_dapm_dbypassl_control),
1175 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1176 &twl4030_dapm_dbypassr_control),
1177 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1178 &twl4030_dapm_dbypassv_control),
6bab83fd 1179
4005d39a
PU		 1180 /* Digital mixers, power control for the physical DACs */
1181 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1182 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1183 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1184 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1185 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1186 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1187 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1188 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1189 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1190 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1191
1192 /* Analog mixers, power control for the physical PGAs */
1193 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1194 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1195 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1196 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1197 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1198 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1199 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1200 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1201 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1202 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1203
7729cf74
PU		 1204 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1205 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1206
c42a59ea
PU		 1207 SND_SOC_DAPM_SUPPLY("AIF Enable", TWL4030_REG_AUDIO_IF, 0, 0, NULL, 0),
1208
1a787e7a 1209 /* Output MIXER controls */
5e98a464 1210 /* Earpiece */
1a787e7a
JS		 1211 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1212 &twl4030_dapm_earpiece_controls[0],
1213 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1214 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1215 0, 0, NULL, 0, earpiecepga_event,
1216 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1217 /* PreDrivL/R */
1a787e7a
JS		 1218 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1219 &twl4030_dapm_predrivel_controls[0],
1220 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1221 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1222 0, 0, NULL, 0, predrivelpga_event,
1223 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1224 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1225 &twl4030_dapm_predriver_controls[0],
1226 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1227 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1228 0, 0, NULL, 0, predriverpga_event,
1229 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1230 /* HeadsetL/R */
6943c92e 1231 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1232 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1233 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1234 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1235 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1236 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1237 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1238 &twl4030_dapm_hsor_controls[0],
1239 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1240 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1241 0, 0, NULL, 0, headsetrpga_event,
1242 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1243 /* CarkitL/R */
1a787e7a
JS		 1244 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1245 &twl4030_dapm_carkitl_controls[0],
1246 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1247 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1248 0, 0, NULL, 0, carkitlpga_event,
1249 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1250 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1251 &twl4030_dapm_carkitr_controls[0],
1252 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1253 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1254 0, 0, NULL, 0, carkitrpga_event,
1255 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1256
1257 /* Output MUX controls */
df339804 1258 /* HandsfreeL/R */
5a2e9a48
PU		 1259 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1260 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1261 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1262 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1263 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1264 0, 0, NULL, 0, handsfreelpga_event,
1265 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1266 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1267 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1268 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1269 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1270 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1271 0, 0, NULL, 0, handsfreerpga_event,
1272 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1273 /* Vibra */
86139a13
JV		 1274 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1275 &twl4030_dapm_vibra_control, vibramux_event,
1276 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1277 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1278 &twl4030_dapm_vibrapath_control),
5e98a464 1279
276c6222
PU		 1280 /* Introducing four virtual ADC, since TWL4030 have four channel for
1281 capture */
1282 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1283 SND_SOC_NOPM, 0, 0),
1284 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1285 SND_SOC_NOPM, 0, 0),
1286 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1287 SND_SOC_NOPM, 0, 0),
1288 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1289 SND_SOC_NOPM, 0, 0),
1290
1291 /* Analog/Digital mic path selection.
1292 TX1 Left/Right: either analog Left/Right or Digimic0
1293 TX2 Left/Right: either analog Left/Right or Digimic1 */
1294 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1295 &twl4030_dapm_micpathtx1_control, micpath_event,
1296 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1297 SND_SOC_DAPM_POST_REG),
1298 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1299 &twl4030_dapm_micpathtx2_control, micpath_event,
1300 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1301 SND_SOC_DAPM_POST_REG),
1302
97b8096d 1303 /* Analog input mixers for the capture amplifiers */
9028935d 1304 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1305 TWL4030_REG_ANAMICL, 4, 0,
1306 &twl4030_dapm_analoglmic_controls[0],
1307 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1308 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1309 TWL4030_REG_ANAMICR, 4, 0,
1310 &twl4030_dapm_analogrmic_controls[0],
1311 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1312
fb2a2f84
PU		 1313 SND_SOC_DAPM_PGA("ADC Physical Left",
1314 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1315 SND_SOC_DAPM_PGA("ADC Physical Right",
1316 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1317
1318 SND_SOC_DAPM_PGA("Digimic0 Enable",
1319 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1320 SND_SOC_DAPM_PGA("Digimic1 Enable",
1321 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1322
1323 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1324 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1325 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1326
cc17557e
SS		 1327};
1328
1329static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1330 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1331 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1332 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1333 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1334 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1335
7729cf74
PU		 1336 /* Supply for the digital part (APLL) */
1337 {"Digital R1 Playback Mixer", NULL, "APLL Enable"},
1338 {"Digital L1 Playback Mixer", NULL, "APLL Enable"},
1339 {"Digital R2 Playback Mixer", NULL, "APLL Enable"},
1340 {"Digital L2 Playback Mixer", NULL, "APLL Enable"},
1341 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1342
c42a59ea
PU		 1343 {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
1344 {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
1345 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1346 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1347
4005d39a
PU		 1348 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1349 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1350 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1351 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1352 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1353
5e98a464
PU		 1354 /* Internal playback routings */
1355 /* Earpiece */
4005d39a
PU		 1356 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1357 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1358 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1359 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1360 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1361 /* PreDrivL */
4005d39a
PU		 1362 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1363 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1364 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1365 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1366 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1367 /* PreDrivR */
4005d39a
PU		 1368 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1369 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1370 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1371 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1372 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1373 /* HeadsetL */
4005d39a
PU		 1374 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1375 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1376 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1377 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1378 /* HeadsetR */
4005d39a
PU		 1379 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1380 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1381 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1382 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1383 /* CarkitL */
4005d39a
PU		 1384 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1385 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1386 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1387 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1388 /* CarkitR */
4005d39a
PU		 1389 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1390 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1391 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1392 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1393 /* HandsfreeL */
4005d39a
PU		 1394 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1395 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1396 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1397 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1398 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1399 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1400 /* HandsfreeR */
4005d39a
PU		 1401 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1402 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1403 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1404 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1405 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1406 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1407 /* Vibra */
1408 {"Vibra Mux", "AudioL1", "DAC Left1"},
1409 {"Vibra Mux", "AudioR1", "DAC Right1"},
1410 {"Vibra Mux", "AudioL2", "DAC Left2"},
1411 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1412
cc17557e 1413 /* outputs */
4005d39a
PU		 1414 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1415 {"OUTR", NULL, "Analog R2 Playback Mixer"},
9008adf9
PU		 1416 {"EARPIECE", NULL, "Earpiece PGA"},
1417 {"PREDRIVEL", NULL, "PredriveL PGA"},
1418 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1419 {"HSOL", NULL, "HeadsetL PGA"},
1420 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1421 {"CARKITL", NULL, "CarkitL PGA"},
1422 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1423 {"HFL", NULL, "HandsfreeL PGA"},
1424 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1425 {"Vibra Route", "Audio", "Vibra Mux"},
1426 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1427
276c6222 1428 /* Capture path */
9028935d
PU		 1429 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1430 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1431 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1432 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1433
9028935d
PU		 1434 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1435 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1436
9028935d
PU		 1437 {"ADC Physical Left", NULL, "Analog Left"},
1438 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1439
1440 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1441 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1442
1443 /* TX1 Left capture path */
fb2a2f84 1444 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1445 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1446 /* TX1 Right capture path */
fb2a2f84 1447 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1448 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1449 /* TX2 Left capture path */
fb2a2f84 1450 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1451 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1452 /* TX2 Right capture path */
fb2a2f84 1453 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1454 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1455
1456 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1457 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1458 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1459 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1460
1c3d2002
PU		 1461 {"ADC Virtual Left1", NULL, "APLL Enable"},
1462 {"ADC Virtual Right1", NULL, "APLL Enable"},
1463 {"ADC Virtual Left2", NULL, "APLL Enable"},
1464 {"ADC Virtual Right2", NULL, "APLL Enable"},
1465
c42a59ea
PU		 1466 {"ADC Virtual Left1", NULL, "AIF Enable"},
1467 {"ADC Virtual Right1", NULL, "AIF Enable"},
1468 {"ADC Virtual Left2", NULL, "AIF Enable"},
1469 {"ADC Virtual Right2", NULL, "AIF Enable"},
1470
7393958f 1471 /* Analog bypass routes */
9028935d
PU		 1472 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1473 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1474 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1475 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1476 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1477
78e08e2f
PU		 1478 /* Supply for the Analog loopbacks */
1479 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1480 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1481 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1482 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1483 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1484
7393958f
PU		 1485 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1486 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1487 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1488 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1489 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1490
6bab83fd
PU		 1491 /* Digital bypass routes */
1492 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1493 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1494 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1495
4005d39a
PU		 1496 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1497 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1498 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1499
cc17557e
SS		 1500};
1501
1502static int twl4030_add_widgets(struct snd_soc_codec *codec)
1503{
1504 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1505 ARRAY_SIZE(twl4030_dapm_widgets));
1506
1507 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1508
cc17557e
SS		 1509 return 0;
1510}
1511
cc17557e
SS		 1512static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1513 enum snd_soc_bias_level level)
1514{
1515 switch (level) {
1516 case SND_SOC_BIAS_ON:
cc17557e
SS		 1517 break;
1518 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1519 break;
1520 case SND_SOC_BIAS_STANDBY:
78e08e2f
PU		 1521 if (codec->bias_level == SND_SOC_BIAS_OFF)
1522 twl4030_power_up(codec);
cc17557e
SS		 1523 break;
1524 case SND_SOC_BIAS_OFF:
1525 twl4030_power_down(codec);
1526 break;
1527 }
1528 codec->bias_level = level;
1529
1530 return 0;
1531}
1532
6b87a91f
PU		 1533static void twl4030_constraints(struct twl4030_priv *twl4030,
1534 struct snd_pcm_substream *mst_substream)
1535{
1536 struct snd_pcm_substream *slv_substream;
1537
1538 /* Pick the stream, which need to be constrained */
1539 if (mst_substream == twl4030->master_substream)
1540 slv_substream = twl4030->slave_substream;
1541 else if (mst_substream == twl4030->slave_substream)
1542 slv_substream = twl4030->master_substream;
1543 else /* This should not happen.. */
1544 return;
1545
1546 /* Set the constraints according to the already configured stream */
1547 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1548 SNDRV_PCM_HW_PARAM_RATE,
1549 twl4030->rate,
1550 twl4030->rate);
1551
1552 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1553 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1554 twl4030->sample_bits,
1555 twl4030->sample_bits);
1556
1557 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1558 SNDRV_PCM_HW_PARAM_CHANNELS,
1559 twl4030->channels,
1560 twl4030->channels);
1561}
1562
8a1f936a
PU		 1563/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1564 * capture has to be enabled/disabled. */
1565static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1566 int enable)
1567{
1568 u8 reg, mask;
1569
1570 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1571
1572 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1573 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1574 else
1575 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1576
1577 if (enable)
1578 reg |= mask;
1579 else
1580 reg &= ~mask;
1581
1582 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1583}
1584
d6648da1
PU		 1585static int twl4030_startup(struct snd_pcm_substream *substream,
1586 struct snd_soc_dai *dai)
7220b9f4
PU		 1587{
1588 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1589 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1590 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1591 struct twl4030_priv *twl4030 = codec->private_data;
1592
7220b9f4 1593 if (twl4030->master_substream) {
7220b9f4 1594 twl4030->slave_substream = substream;
6b87a91f
PU		 1595 /* The DAI has one configuration for playback and capture, so
1596 * if the DAI has been already configured then constrain this
1597 * substream to match it. */
1598 if (twl4030->configured)
1599 twl4030_constraints(twl4030, twl4030->master_substream);
1600 } else {
8a1f936a
PU		 1601 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1602 TWL4030_OPTION_1)) {
1603 /* In option2 4 channel is not supported, set the
1604 * constraint for the first stream for channels, the
1605 * second stream will 'inherit' this cosntraint */
1606 snd_pcm_hw_constraint_minmax(substream->runtime,
1607 SNDRV_PCM_HW_PARAM_CHANNELS,
1608 2, 2);
1609 }
7220b9f4 1610 twl4030->master_substream = substream;
6b87a91f 1611 }
7220b9f4
PU		 1612
1613 return 0;
1614}
1615
d6648da1
PU		 1616static void twl4030_shutdown(struct snd_pcm_substream *substream,
1617 struct snd_soc_dai *dai)
7220b9f4
PU		 1618{
1619 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1620 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1621 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1622 struct twl4030_priv *twl4030 = codec->private_data;
1623
1624 if (twl4030->master_substream == substream)
1625 twl4030->master_substream = twl4030->slave_substream;
1626
1627 twl4030->slave_substream = NULL;
6b87a91f
PU		 1628
1629 /* If all streams are closed, or the remaining stream has not yet
1630 * been configured than set the DAI as not configured. */
1631 if (!twl4030->master_substream)
1632 twl4030->configured = 0;
1633 else if (!twl4030->master_substream->runtime->channels)
1634 twl4030->configured = 0;
8a1f936a
PU		 1635
1636 /* If the closing substream had 4 channel, do the necessary cleanup */
1637 if (substream->runtime->channels == 4)
1638 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1639}
1640
cc17557e 1641static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1642 struct snd_pcm_hw_params *params,
1643 struct snd_soc_dai *dai)
cc17557e
SS		 1644{
1645 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1646 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1647 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1648 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1649 u8 mode, old_mode, format, old_format;
1650
8a1f936a
PU		 1651 /* If the substream has 4 channel, do the necessary setup */
1652 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1653 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1654 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1655
1656 /* Safety check: are we in the correct operating mode and
1657 * the interface is in TDM mode? */
1658 if ((mode & TWL4030_OPTION_1) &&
1659 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1660 twl4030_tdm_enable(codec, substream->stream, 1);
1661 else
1662 return -EINVAL;
1663 }
1664
6b87a91f
PU		 1665 if (twl4030->configured)
1666 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1667 return 0;
1668
cc17557e
SS		 1669 /* bit rate */
1670 old_mode = twl4030_read_reg_cache(codec,
1671 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1672 mode = old_mode & ~TWL4030_APLL_RATE;
1673
1674 switch (params_rate(params)) {
1675 case 8000:
1676 mode |= TWL4030_APLL_RATE_8000;
1677 break;
1678 case 11025:
1679 mode |= TWL4030_APLL_RATE_11025;
1680 break;
1681 case 12000:
1682 mode |= TWL4030_APLL_RATE_12000;
1683 break;
1684 case 16000:
1685 mode |= TWL4030_APLL_RATE_16000;
1686 break;
1687 case 22050:
1688 mode |= TWL4030_APLL_RATE_22050;
1689 break;
1690 case 24000:
1691 mode |= TWL4030_APLL_RATE_24000;
1692 break;
1693 case 32000:
1694 mode |= TWL4030_APLL_RATE_32000;
1695 break;
1696 case 44100:
1697 mode |= TWL4030_APLL_RATE_44100;
1698 break;
1699 case 48000:
1700 mode |= TWL4030_APLL_RATE_48000;
1701 break;
103f211d
PU		 1702 case 96000:
1703 mode |= TWL4030_APLL_RATE_96000;
1704 break;
cc17557e
SS		 1705 default:
1706 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1707 params_rate(params));
1708 return -EINVAL;
1709 }
1710
1711 if (mode != old_mode) {
1712 /* change rate and set CODECPDZ */
7393958f 1713 twl4030_codec_enable(codec, 0);
cc17557e 1714 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1715 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1716 }
1717
1718 /* sample size */
1719 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1720 format = old_format;
1721 format &= ~TWL4030_DATA_WIDTH;
1722 switch (params_format(params)) {
1723 case SNDRV_PCM_FORMAT_S16_LE:
1724 format |= TWL4030_DATA_WIDTH_16S_16W;
1725 break;
1726 case SNDRV_PCM_FORMAT_S24_LE:
1727 format |= TWL4030_DATA_WIDTH_32S_24W;
1728 break;
1729 default:
1730 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1731 params_format(params));
1732 return -EINVAL;
1733 }
1734
1735 if (format != old_format) {
1736
1737 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1738 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1739
1740 /* change format */
1741 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1742
1743 /* set CODECPDZ afterwards */
db04e2c5 1744 twl4030_codec_enable(codec, 1);
cc17557e 1745 }
6b87a91f
PU		 1746
1747 /* Store the important parameters for the DAI configuration and set
1748 * the DAI as configured */
1749 twl4030->configured = 1;
1750 twl4030->rate = params_rate(params);
1751 twl4030->sample_bits = hw_param_interval(params,
1752 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1753 twl4030->channels = params_channels(params);
1754
1755 /* If both playback and capture streams are open, and one of them
1756 * is setting the hw parameters right now (since we are here), set
1757 * constraints to the other stream to match the current one. */
1758 if (twl4030->slave_substream)
1759 twl4030_constraints(twl4030, substream);
1760
cc17557e
SS		 1761 return 0;
1762}
1763
1764static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1765 int clk_id, unsigned int freq, int dir)
1766{
1767 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1768 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1769
1770 switch (freq) {
1771 case 19200000:
cc17557e 1772 case 26000000:
cc17557e 1773 case 38400000:
cc17557e
SS		 1774 break;
1775 default:
68d01955 1776 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
cc17557e
SS		 1777 return -EINVAL;
1778 }
1779
68d01955
PU		 1780 if ((freq / 1000) != twl4030->sysclk) {
1781 dev_err(codec->dev,
1782 "Mismatch in APLL mclk: %u (configured: %u)\n",
1783 freq, twl4030->sysclk * 1000);
1784 return -EINVAL;
1785 }
cc17557e
SS		 1786
1787 return 0;
1788}
1789
1790static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1791 unsigned int fmt)
1792{
1793 struct snd_soc_codec *codec = codec_dai->codec;
1794 u8 old_format, format;
1795
1796 /* get format */
1797 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1798 format = old_format;
1799
1800 /* set master/slave audio interface */
1801 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1802 case SND_SOC_DAIFMT_CBM_CFM:
1803 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1804 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1805 break;
1806 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1807 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1808 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1809 break;
1810 default:
1811 return -EINVAL;
1812 }
1813
1814 /* interface format */
1815 format &= ~TWL4030_AIF_FORMAT;
1816 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1817 case SND_SOC_DAIFMT_I2S:
1818 format |= TWL4030_AIF_FORMAT_CODEC;
1819 break;
8a1f936a
PU		 1820 case SND_SOC_DAIFMT_DSP_A:
1821 format |= TWL4030_AIF_FORMAT_TDM;
1822 break;
cc17557e
SS		 1823 default:
1824 return -EINVAL;
1825 }
1826
1827 if (format != old_format) {
1828
1829 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1830 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1831
1832 /* change format */
1833 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1834
1835 /* set CODECPDZ afterwards */
db04e2c5 1836 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1837 }
1838
1839 return 0;
1840}
1841
68140443
LCM		 1842static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1843{
1844 struct snd_soc_codec *codec = dai->codec;
1845 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1846
1847 if (tristate)
1848 reg |= TWL4030_AIF_TRI_EN;
1849 else
1850 reg &= ~TWL4030_AIF_TRI_EN;
1851
1852 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1853}
1854
b7a755a8
MLC		 1855/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1856 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1857static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1858 int enable)
1859{
1860 u8 reg, mask;
1861
1862 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1863
1864 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1865 mask = TWL4030_ARXL1_VRX_EN;
1866 else
1867 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1868
1869 if (enable)
1870 reg |= mask;
1871 else
1872 reg &= ~mask;
1873
1874 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1875}
1876
7154b3e8
JS		 1877static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1878 struct snd_soc_dai *dai)
1879{
1880 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1881 struct snd_soc_device *socdev = rtd->socdev;
1882 struct snd_soc_codec *codec = socdev->card->codec;
68d01955 1883 struct twl4030_priv *twl4030 = codec->private_data;
7154b3e8
JS		 1884 u8 mode;
1885
1886 /* If the system master clock is not 26MHz, the voice PCM interface is
1887 * not avilable.
1888 */
68d01955
PU		 1889 if (twl4030->sysclk != 26000) {
1890 dev_err(codec->dev, "The board is configured for %u Hz, while"
1891 "the Voice interface needs 26MHz APLL mclk\n",
1892 twl4030->sysclk * 1000);
7154b3e8
JS		 1893 return -EINVAL;
1894 }
1895
1896 /* If the codec mode is not option2, the voice PCM interface is not
1897 * avilable.
1898 */
1899 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1900 & TWL4030_OPT_MODE;
1901
1902 if (mode != TWL4030_OPTION_2) {
1903 printk(KERN_ERR "TWL4030 voice startup: "
1904 "the codec mode is not option2\n");
1905 return -EINVAL;
1906 }
1907
1908 return 0;
1909}
1910
b7a755a8
MLC		 1911static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1912 struct snd_soc_dai *dai)
1913{
1914 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1915 struct snd_soc_device *socdev = rtd->socdev;
1916 struct snd_soc_codec *codec = socdev->card->codec;
1917
1918 /* Enable voice digital filters */
1919 twl4030_voice_enable(codec, substream->stream, 0);
1920}
1921
7154b3e8
JS		 1922static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1923 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1924{
1925 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1926 struct snd_soc_device *socdev = rtd->socdev;
1927 struct snd_soc_codec *codec = socdev->card->codec;
1928 u8 old_mode, mode;
1929
b7a755a8
MLC		 1930 /* Enable voice digital filters */
1931 twl4030_voice_enable(codec, substream->stream, 1);
1932
7154b3e8
JS		 1933 /* bit rate */
1934 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1935 & ~(TWL4030_CODECPDZ);
1936 mode = old_mode;
1937
1938 switch (params_rate(params)) {
1939 case 8000:
1940 mode &= ~(TWL4030_SEL_16K);
1941 break;
1942 case 16000:
1943 mode |= TWL4030_SEL_16K;
1944 break;
1945 default:
1946 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1947 params_rate(params));
1948 return -EINVAL;
1949 }
1950
1951 if (mode != old_mode) {
1952 /* change rate and set CODECPDZ */
1953 twl4030_codec_enable(codec, 0);
1954 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1955 twl4030_codec_enable(codec, 1);
1956 }
1957
1958 return 0;
1959}
1960
1961static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1962 int clk_id, unsigned int freq, int dir)
1963{
1964 struct snd_soc_codec *codec = codec_dai->codec;
68d01955 1965 struct twl4030_priv *twl4030 = codec->private_data;
7154b3e8 1966
68d01955
PU		 1967 if (freq != 26000000) {
1968 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
1969 "interface needs 26MHz APLL mclk\n", freq);
1970 return -EINVAL;
1971 }
1972 if ((freq / 1000) != twl4030->sysclk) {
1973 dev_err(codec->dev,
1974 "Mismatch in APLL mclk: %u (configured: %u)\n",
1975 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 1976 return -EINVAL;
1977 }
7154b3e8
JS		 1978 return 0;
1979}
1980
1981static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1982 unsigned int fmt)
1983{
1984 struct snd_soc_codec *codec = codec_dai->codec;
1985 u8 old_format, format;
1986
1987 /* get format */
1988 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1989 format = old_format;
1990
1991 /* set master/slave audio interface */
1992 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 1993 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 1994 format &= ~(TWL4030_VIF_SLAVE_EN);
1995 break;
1996 case SND_SOC_DAIFMT_CBS_CFS:
1997 format |= TWL4030_VIF_SLAVE_EN;
1998 break;
1999 default:
2000 return -EINVAL;
2001 }
2002
2003 /* clock inversion */
2004 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2005 case SND_SOC_DAIFMT_IB_NF:
2006 format &= ~(TWL4030_VIF_FORMAT);
2007 break;
2008 case SND_SOC_DAIFMT_NB_IF:
2009 format |= TWL4030_VIF_FORMAT;
2010 break;
2011 default:
2012 return -EINVAL;
2013 }
2014
2015 if (format != old_format) {
2016 /* change format and set CODECPDZ */
2017 twl4030_codec_enable(codec, 0);
2018 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2019 twl4030_codec_enable(codec, 1);
2020 }
2021
2022 return 0;
2023}
2024
68140443
LCM		 2025static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2026{
2027 struct snd_soc_codec *codec = dai->codec;
2028 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2029
2030 if (tristate)
2031 reg |= TWL4030_VIF_TRI_EN;
2032 else
2033 reg &= ~TWL4030_VIF_TRI_EN;
2034
2035 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2036}
2037
bbba9444 2038#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2039#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2040
10d9e3d9 2041static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2042 .startup = twl4030_startup,
2043 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2044 .hw_params = twl4030_hw_params,
2045 .set_sysclk = twl4030_set_dai_sysclk,
2046 .set_fmt = twl4030_set_dai_fmt,
68140443 2047 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2048};
2049
7154b3e8
JS		 2050static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2051 .startup = twl4030_voice_startup,
b7a755a8 2052 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2053 .hw_params = twl4030_voice_hw_params,
2054 .set_sysclk = twl4030_voice_set_dai_sysclk,
2055 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2056 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2057};
2058
2059struct snd_soc_dai twl4030_dai[] = {
2060{
cc17557e
SS		 2061 .name = "twl4030",
2062 .playback = {
b4852b79 2063 .stream_name = "HiFi Playback",
cc17557e 2064 .channels_min = 2,
8a1f936a 2065 .channels_max = 4,
31ad0f31 2066 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2067 .formats = TWL4030_FORMATS,},
2068 .capture = {
2069 .stream_name = "Capture",
2070 .channels_min = 2,
8a1f936a 2071 .channels_max = 4,
cc17557e
SS		 2072 .rates = TWL4030_RATES,
2073 .formats = TWL4030_FORMATS,},
10d9e3d9 2074 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2075},
2076{
2077 .name = "twl4030 Voice",
2078 .playback = {
b4852b79 2079 .stream_name = "Voice Playback",
7154b3e8
JS		 2080 .channels_min = 1,
2081 .channels_max = 1,
2082 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2083 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2084 .capture = {
2085 .stream_name = "Capture",
2086 .channels_min = 1,
2087 .channels_max = 2,
2088 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2089 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2090 .ops = &twl4030_dai_voice_ops,
2091},
cc17557e
SS		 2092};
2093EXPORT_SYMBOL_GPL(twl4030_dai);
2094
7a1fecf5 2095static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
cc17557e
SS		 2096{
2097 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2098 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2099
2100 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2101
2102 return 0;
2103}
2104
7a1fecf5 2105static int twl4030_soc_resume(struct platform_device *pdev)
cc17557e
SS		 2106{
2107 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2108 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2109
2110 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2111 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2112 return 0;
2113}
2114
7a1fecf5 2115static struct snd_soc_codec *twl4030_codec;
cc17557e 2116
7a1fecf5 2117static int twl4030_soc_probe(struct platform_device *pdev)
cc17557e 2118{
7a1fecf5 2119 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
9da28c7b 2120 struct twl4030_setup_data *setup = socdev->codec_data;
7a1fecf5
PU		 2121 struct snd_soc_codec *codec;
2122 struct twl4030_priv *twl4030;
2123 int ret;
cc17557e 2124
7a1fecf5 2125 BUG_ON(!twl4030_codec);
cc17557e 2126
7a1fecf5
PU		 2127 codec = twl4030_codec;
2128 twl4030 = codec->private_data;
2129 socdev->card->codec = codec;
cc17557e 2130
9da28c7b
PU		 2131 /* Configuration for headset ramp delay from setup data */
2132 if (setup) {
2133 unsigned char hs_pop;
2134
68d01955
PU		 2135 if (setup->sysclk != twl4030->sysclk)
2136 dev_warn(&pdev->dev,
2137 "Mismatch in APLL mclk: %u (configured: %u)\n",
2138 setup->sysclk, twl4030->sysclk);
9da28c7b
PU		 2139
2140 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2141 hs_pop &= ~TWL4030_RAMP_DELAY;
2142 hs_pop |= (setup->ramp_delay_value << 2);
2143 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
9da28c7b
PU		 2144 }
2145
cc17557e
SS		 2146 /* register pcms */
2147 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2148 if (ret < 0) {
7a1fecf5
PU		 2149 dev_err(&pdev->dev, "failed to create pcms\n");
2150 return ret;
cc17557e
SS		 2151 }
2152
3e8e1952
IM		 2153 snd_soc_add_controls(codec, twl4030_snd_controls,
2154 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2155 twl4030_add_widgets(codec);
2156
7a1fecf5 2157 return 0;
cc17557e
SS		 2158}
2159
7a1fecf5 2160static int twl4030_soc_remove(struct platform_device *pdev)
cc17557e
SS		 2161{
2162 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5
PU		 2163 struct snd_soc_codec *codec = socdev->card->codec;
2164
2165 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2166 snd_soc_free_pcms(socdev);
2167 snd_soc_dapm_free(socdev);
7a1fecf5
PU		 2168
2169 return 0;
2170}
2171
2172static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2173{
2174 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
cc17557e 2175 struct snd_soc_codec *codec;
7393958f 2176 struct twl4030_priv *twl4030;
7a1fecf5 2177 int ret;
cc17557e 2178
68d01955
PU		 2179 if (!pdata) {
2180 dev_err(&pdev->dev, "platform_data is missing\n");
7a1fecf5
PU		 2181 return -EINVAL;
2182 }
cc17557e 2183
7393958f
PU		 2184 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2185 if (twl4030 == NULL) {
7a1fecf5 2186 dev_err(&pdev->dev, "Can not allocate memroy\n");
7393958f
PU		 2187 return -ENOMEM;
2188 }
2189
7a1fecf5 2190 codec = &twl4030->codec;
7393958f 2191 codec->private_data = twl4030;
7a1fecf5
PU		 2192 codec->dev = &pdev->dev;
2193 twl4030_dai[0].dev = &pdev->dev;
2194 twl4030_dai[1].dev = &pdev->dev;
2195
cc17557e
SS		 2196 mutex_init(&codec->mutex);
2197 INIT_LIST_HEAD(&codec->dapm_widgets);
2198 INIT_LIST_HEAD(&codec->dapm_paths);
2199
7a1fecf5
PU		 2200 codec->name = "twl4030";
2201 codec->owner = THIS_MODULE;
2202 codec->read = twl4030_read_reg_cache;
2203 codec->write = twl4030_write;
2204 codec->set_bias_level = twl4030_set_bias_level;
2205 codec->dai = twl4030_dai;
fd63df22 2206 codec->num_dai = ARRAY_SIZE(twl4030_dai);
7a1fecf5
PU		 2207 codec->reg_cache_size = sizeof(twl4030_reg);
2208 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2209 GFP_KERNEL);
2210 if (codec->reg_cache == NULL) {
2211 ret = -ENOMEM;
2212 goto error_cache;
2213 }
2214
2215 platform_set_drvdata(pdev, twl4030);
2216 twl4030_codec = codec;
2217
2218 /* Set the defaults, and power up the codec */
68d01955 2219 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
7a1fecf5 2220 twl4030_init_chip(codec);
b3f5a272 2221 codec->bias_level = SND_SOC_BIAS_OFF;
7a1fecf5
PU		 2222 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2223
2224 ret = snd_soc_register_codec(codec);
2225 if (ret != 0) {
2226 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2227 goto error_codec;
2228 }
2229
2230 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2231 if (ret != 0) {
2232 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2233 snd_soc_unregister_codec(codec);
2234 goto error_codec;
2235 }
cc17557e
SS		 2236
2237 return 0;
7a1fecf5
PU		 2238
2239error_codec:
2240 twl4030_power_down(codec);
2241 kfree(codec->reg_cache);
2242error_cache:
2243 kfree(twl4030);
2244 return ret;
cc17557e
SS		 2245}
2246
7a1fecf5 2247static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2248{
7a1fecf5 2249 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
cc17557e 2250
cb67286d
PU		 2251 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2252 snd_soc_unregister_codec(&twl4030->codec);
2253 kfree(twl4030->codec.reg_cache);
7a1fecf5 2254 kfree(twl4030);
cc17557e 2255
7a1fecf5 2256 twl4030_codec = NULL;
cc17557e
SS		 2257 return 0;
2258}
2259
7a1fecf5
PU		 2260MODULE_ALIAS("platform:twl4030_codec_audio");
2261
2262static struct platform_driver twl4030_codec_driver = {
2263 .probe = twl4030_codec_probe,
2264 .remove = __devexit_p(twl4030_codec_remove),
2265 .driver = {
2266 .name = "twl4030_codec_audio",
2267 .owner = THIS_MODULE,
2268 },
cc17557e 2269};
cc17557e 2270
24e07db8 2271static int __init twl4030_modinit(void)
64089b84 2272{
7a1fecf5 2273 return platform_driver_register(&twl4030_codec_driver);
64089b84 2274}
24e07db8 2275module_init(twl4030_modinit);
64089b84
MB		 2276
2277static void __exit twl4030_exit(void)
2278{
7a1fecf5 2279 platform_driver_unregister(&twl4030_codec_driver);
64089b84
MB		 2280}
2281module_exit(twl4030_exit);
2282
7a1fecf5
PU		 2283struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2284 .probe = twl4030_soc_probe,
2285 .remove = twl4030_soc_remove,
2286 .suspend = twl4030_soc_suspend,
2287 .resume = twl4030_soc_resume,
2288};
2289EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2290
cc17557e
SS		 2291MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2292MODULE_AUTHOR("Steve Sakoman");
2293MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)