projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
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| c8bf93f0 PU |
1 | /* |
| 2 | * ALSA SoC Texas Instruments TLV320DAC33 codec driver | |
| 3 | * | |
| 93864cf0 | 4 | * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> |
| c8bf93f0 PU |
5 | * |
| 6 | * Copyright: (C) 2009 Nokia Corporation | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, but | |
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | * General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
| 20 | * 02110-1301 USA | |
| 21 | * | |
| 22 | */ | |
| 23 | ||
| 24 | #ifndef __TLV320DAC33_H | |
| 25 | #define __TLV320DAC33_H | |
| 26 | ||
| 27 | #define DAC33_PAGE_SELECT 0x00 | |
| 28 | #define DAC33_PWR_CTRL 0x01 | |
| 29 | #define DAC33_PLL_CTRL_A 0x02 | |
| 30 | #define DAC33_PLL_CTRL_B 0x03 | |
| 31 | #define DAC33_PLL_CTRL_C 0x04 | |
| 32 | #define DAC33_PLL_CTRL_D 0x05 | |
| 33 | #define DAC33_PLL_CTRL_E 0x06 | |
| 34 | #define DAC33_INT_OSC_CTRL 0x07 | |
| 35 | #define DAC33_INT_OSC_FREQ_RAT_A 0x08 | |
| 36 | #define DAC33_INT_OSC_FREQ_RAT_B 0x09 | |
| 37 | #define DAC33_INT_OSC_DAC_RATIO_SET 0x0A | |
| 38 | #define DAC33_CALIB_TIME 0x0B | |
| 39 | #define DAC33_INT_OSC_CTRL_B 0x0C | |
| 40 | #define DAC33_INT_OSC_CTRL_C 0x0D | |
| 41 | #define DAC33_INT_OSC_STATUS 0x0E | |
| 42 | #define DAC33_INT_OSC_DAC_RATIO_READ 0x0F | |
| 43 | #define DAC33_INT_OSC_FREQ_RAT_READ_A 0x10 | |
| 44 | #define DAC33_INT_OSC_FREQ_RAT_READ_B 0x11 | |
| 45 | #define DAC33_SER_AUDIOIF_CTRL_A 0x12 | |
| 46 | #define DAC33_SER_AUDIOIF_CTRL_B 0x13 | |
| 47 | #define DAC33_SER_AUDIOIF_CTRL_C 0x14 | |
| 48 | #define DAC33_FIFO_CTRL_A 0x15 | |
| 49 | #define DAC33_UTHR_MSB 0x16 | |
| 50 | #define DAC33_UTHR_LSB 0x17 | |
| 51 | #define DAC33_ATHR_MSB 0x18 | |
| 52 | #define DAC33_ATHR_LSB 0x19 | |
| 53 | #define DAC33_LTHR_MSB 0x1A | |
| 54 | #define DAC33_LTHR_LSB 0x1B | |
| 55 | #define DAC33_PREFILL_MSB 0x1C | |
| 56 | #define DAC33_PREFILL_LSB 0x1D | |
| 57 | #define DAC33_NSAMPLE_MSB 0x1E | |
| 58 | #define DAC33_NSAMPLE_LSB 0x1F | |
| 59 | #define DAC33_FIFO_WPTR_MSB 0x20 | |
| 60 | #define DAC33_FIFO_WPTR_LSB 0x21 | |
| 61 | #define DAC33_FIFO_RPTR_MSB 0x22 | |
| 62 | #define DAC33_FIFO_RPTR_LSB 0x23 | |
| 63 | #define DAC33_FIFO_DEPTH_MSB 0x24 | |
| 64 | #define DAC33_FIFO_DEPTH_LSB 0x25 | |
| 65 | #define DAC33_SAMPLES_REMAINING_MSB 0x26 | |
| 66 | #define DAC33_SAMPLES_REMAINING_LSB 0x27 | |
| 67 | #define DAC33_FIFO_IRQ_FLAG 0x28 | |
| 68 | #define DAC33_FIFO_IRQ_MASK 0x29 | |
| 69 | #define DAC33_FIFO_IRQ_MODE_A 0x2A | |
| 70 | #define DAC33_FIFO_IRQ_MODE_B 0x2B | |
| 71 | #define DAC33_DAC_CTRL_A 0x2C | |
| 72 | #define DAC33_DAC_CTRL_B 0x2D | |
| 73 | #define DAC33_DAC_CTRL_C 0x2E | |
| 74 | #define DAC33_LDAC_DIG_VOL_CTRL 0x2F | |
| 75 | #define DAC33_RDAC_DIG_VOL_CTRL 0x30 | |
| 76 | #define DAC33_DAC_STATUS_FLAGS 0x31 | |
| 77 | #define DAC33_ASRC_CTRL_A 0x32 | |
| 78 | #define DAC33_ASRC_CTRL_B 0x33 | |
| 79 | #define DAC33_SRC_REF_CLK_RATIO_A 0x34 | |
| 80 | #define DAC33_SRC_REF_CLK_RATIO_B 0x35 | |
| 81 | #define DAC33_SRC_EST_REF_CLK_RATIO_A 0x36 | |
| 82 | #define DAC33_SRC_EST_REF_CLK_RATIO_B 0x37 | |
| 83 | #define DAC33_INTP_CTRL_A 0x38 | |
| 84 | #define DAC33_INTP_CTRL_B 0x39 | |
| 85 | /* Registers 0x3A - 0x3F Reserved */ | |
| 86 | #define DAC33_LDAC_PWR_CTRL 0x40 | |
| 87 | #define DAC33_RDAC_PWR_CTRL 0x41 | |
| 88 | #define DAC33_OUT_AMP_CM_CTRL 0x42 | |
| 89 | #define DAC33_OUT_AMP_PWR_CTRL 0x43 | |
| 90 | #define DAC33_OUT_AMP_CTRL 0x44 | |
| 91 | #define DAC33_LINEL_TO_LLO_VOL 0x45 | |
| 92 | /* Registers 0x45 - 0x47 Reserved */ | |
| 93 | #define DAC33_LINER_TO_RLO_VOL 0x48 | |
| 94 | #define DAC33_ANA_VOL_SOFT_STEP_CTRL 0x49 | |
| 95 | #define DAC33_OSC_TRIM 0x4A | |
| 96 | /* Registers 0x4B - 0x7C Reserved */ | |
| 97 | #define DAC33_DEVICE_ID_MSB 0x7D | |
| 98 | #define DAC33_DEVICE_ID_LSB 0x7E | |
| 99 | #define DAC33_DEVICE_REV_ID 0x7F | |
| 100 | ||
| 101 | #define DAC33_CACHEREGNUM 128 | |
| 102 | ||
| 103 | /* Bit definitions */ | |
| 104 | ||
| 105 | /* DAC33_PWR_CTRL (0x01) */ | |
| 106 | #define DAC33_DACRPDNB (0x01 << 0) | |
| 107 | #define DAC33_DACLPDNB (0x01 << 1) | |
| 108 | #define DAC33_OSCPDNB (0x01 << 2) | |
| 109 | #define DAC33_PLLPDNB (0x01 << 3) | |
| 110 | #define DAC33_PDNALLB (0x01 << 4) | |
| 111 | #define DAC33_SOFT_RESET (0x01 << 7) | |
| 112 | ||
| 113 | /* DAC33_INT_OSC_CTRL (0x07) */ | |
| 114 | #define DAC33_REFSEL (0x01 << 1) | |
| 115 | ||
| 116 | /* DAC33_INT_OSC_CTRL_B (0x0C) */ | |
| 117 | #define DAC33_ADJSTEP(x) (x << 0) | |
| 118 | #define DAC33_ADJTHRSHLD(x) (x << 4) | |
| 119 | ||
| 120 | /* DAC33_INT_OSC_CTRL_C (0x0D) */ | |
| 121 | #define DAC33_REFDIV(x) (x << 4) | |
| 122 | ||
| 123 | /* DAC33_INT_OSC_STATUS (0x0E) */ | |
| 124 | #define DAC33_OSCSTATUS_IDLE_CALIB (0x00) | |
| 125 | #define DAC33_OSCSTATUS_NORMAL (0x01) | |
| 126 | #define DAC33_OSCSTATUS_ADJUSTMENT (0x03) | |
| 127 | #define DAC33_OSCSTATUS_NOT_USED (0x02) | |
| 128 | ||
| 129 | /* DAC33_SER_AUDIOIF_CTRL_A (0x12) */ | |
| 130 | #define DAC33_MSWCLK (0x01 << 0) | |
| 131 | #define DAC33_MSBCLK (0x01 << 1) | |
| 132 | #define DAC33_AFMT_MASK (0x03 << 2) | |
| 133 | #define DAC33_AFMT_I2S (0x00 << 2) | |
| 134 | #define DAC33_AFMT_DSP (0x01 << 2) | |
| 135 | #define DAC33_AFMT_RIGHT_J (0x02 << 2) | |
| 136 | #define DAC33_AFMT_LEFT_J (0x03 << 2) | |
| 137 | #define DAC33_WLEN_MASK (0x03 << 4) | |
| 138 | #define DAC33_WLEN_16 (0x00 << 4) | |
| 139 | #define DAC33_WLEN_20 (0x01 << 4) | |
| 140 | #define DAC33_WLEN_24 (0x02 << 4) | |
| 141 | #define DAC33_WLEN_32 (0x03 << 4) | |
| 142 | #define DAC33_NCYCL_MASK (0x03 << 6) | |
| 143 | #define DAC33_NCYCL_16 (0x00 << 6) | |
| 144 | #define DAC33_NCYCL_20 (0x01 << 6) | |
| 145 | #define DAC33_NCYCL_24 (0x02 << 6) | |
| 146 | #define DAC33_NCYCL_32 (0x03 << 6) | |
| 147 | ||
| 148 | /* DAC33_SER_AUDIOIF_CTRL_B (0x13) */ | |
| 149 | #define DAC33_DATA_DELAY_MASK (0x03 << 2) | |
| 150 | #define DAC33_DATA_DELAY(x) (x << 2) | |
| 151 | #define DAC33_BCLKON (0x01 << 5) | |
| 152 | ||
| 153 | /* DAC33_FIFO_CTRL_A (0x15) */ | |
| 154 | #define DAC33_WIDTH (0x01 << 0) | |
| 155 | #define DAC33_FBYPAS (0x01 << 1) | |
| 156 | #define DAC33_FAUTO (0x01 << 2) | |
| 157 | #define DAC33_FIFOFLUSH (0x01 << 3) | |
| 158 | ||
| 159 | /* | |
| 160 | * UTHR, ATHR, LTHR, PREFILL, NSAMPLE (0x16 - 0x1F) | |
| 161 | * 13-bit values | |
| 162 | */ | |
| 163 | #define DAC33_THRREG(x) (((x) & 0x1FFF) << 3) | |
| 164 | ||
| 165 | /* DAC33_FIFO_IRQ_MASK (0x29) */ | |
| 166 | #define DAC33_MNS (0x01 << 0) | |
| 167 | #define DAC33_MPS (0x01 << 1) | |
| 168 | #define DAC33_MAT (0x01 << 2) | |
| 169 | #define DAC33_MLT (0x01 << 3) | |
| 170 | #define DAC33_MUT (0x01 << 4) | |
| 171 | #define DAC33_MUF (0x01 << 5) | |
| 172 | #define DAC33_MOF (0x01 << 6) | |
| 173 | ||
| 174 | #define DAC33_FIFO_IRQ_MODE_MASK (0x03) | |
| 175 | #define DAC33_FIFO_IRQ_MODE_RISING (0x00) | |
| 176 | #define DAC33_FIFO_IRQ_MODE_FALLING (0x01) | |
| 177 | #define DAC33_FIFO_IRQ_MODE_LEVEL (0x02) | |
| 178 | #define DAC33_FIFO_IRQ_MODE_EDGE (0x03) | |
| 179 | ||
| 180 | /* DAC33_FIFO_IRQ_MODE_A (0x2A) */ | |
| 181 | #define DAC33_UTM(x) (x << 0) | |
| 182 | #define DAC33_UFM(x) (x << 2) | |
| 183 | #define DAC33_OFM(x) (x << 4) | |
| 184 | ||
| 185 | /* DAC33_FIFO_IRQ_MODE_B (0x2B) */ | |
| 186 | #define DAC33_NSM(x) (x << 0) | |
| 187 | #define DAC33_PSM(x) (x << 2) | |
| 188 | #define DAC33_ATM(x) (x << 4) | |
| 017deee6 | 189 | #define DAC33_LTM(x) (x << 6) |
| c8bf93f0 PU |
190 | |
| 191 | /* DAC33_DAC_CTRL_A (0x2C) */ | |
| 192 | #define DAC33_DACRATE(x) (x << 0) | |
| 193 | #define DAC33_DACDUAL (0x01 << 4) | |
| 194 | #define DAC33_DACLKSEL_MASK (0x03 << 5) | |
| 195 | #define DAC33_DACLKSEL_INTSOC (0x00 << 5) | |
| 196 | #define DAC33_DACLKSEL_PLL (0x01 << 5) | |
| 197 | #define DAC33_DACLKSEL_MCLK (0x02 << 5) | |
| 198 | #define DAC33_DACLKSEL_BCLK (0x03 << 5) | |
| 199 | ||
| 200 | /* DAC33_DAC_CTRL_B (0x2D) */ | |
| 201 | #define DAC33_DACSRCR_MASK (0x03 << 0) | |
| 202 | #define DAC33_DACSRCR_MUTE (0x00 << 0) | |
| 203 | #define DAC33_DACSRCR_RIGHT (0x01 << 0) | |
| 204 | #define DAC33_DACSRCR_LEFT (0x02 << 0) | |
| 205 | #define DAC33_DACSRCR_MONOMIX (0x03 << 0) | |
| 206 | #define DAC33_DACSRCL_MASK (0x03 << 2) | |
| 207 | #define DAC33_DACSRCL_MUTE (0x00 << 2) | |
| 208 | #define DAC33_DACSRCL_LEFT (0x01 << 2) | |
| 209 | #define DAC33_DACSRCL_RIGHT (0x02 << 2) | |
| 210 | #define DAC33_DACSRCL_MONOMIX (0x03 << 2) | |
| 211 | #define DAC33_DVOLSTEP_MASK (0x03 << 4) | |
| 212 | #define DAC33_DVOLSTEP_SS_PERFS (0x00 << 4) | |
| 213 | #define DAC33_DVOLSTEP_SS_PER2FS (0x01 << 4) | |
| 214 | #define DAC33_DVOLSTEP_SS_DISABLED (0x02 << 4) | |
| 215 | #define DAC33_DVOLCTRL_MASK (0x03 << 6) | |
| 216 | #define DAC33_DVOLCTRL_LR_INDEPENDENT1 (0x00 << 6) | |
| 217 | #define DAC33_DVOLCTRL_LR_RIGHT_CONTROL (0x01 << 6) | |
| 218 | #define DAC33_DVOLCTRL_LR_LEFT_CONTROL (0x02 << 6) | |
| 219 | #define DAC33_DVOLCTRL_LR_INDEPENDENT2 (0x03 << 6) | |
| 220 | ||
| 221 | /* DAC33_DAC_CTRL_C (0x2E) */ | |
| 222 | #define DAC33_DEEMENR (0x01 << 0) | |
| 223 | #define DAC33_EFFENR (0x01 << 1) | |
| 224 | #define DAC33_DEEMENL (0x01 << 2) | |
| 225 | #define DAC33_EFFENL (0x01 << 3) | |
| 226 | #define DAC33_EN3D (0x01 << 4) | |
| 227 | #define DAC33_RESYNMUTE (0x01 << 5) | |
| 228 | #define DAC33_RESYNEN (0x01 << 6) | |
| 229 | ||
| 230 | /* DAC33_ASRC_CTRL_A (0x32) */ | |
| 231 | #define DAC33_SRCBYP (0x01 << 0) | |
| 232 | #define DAC33_SRCLKSEL_MASK (0x03 << 1) | |
| 233 | #define DAC33_SRCLKSEL_INTSOC (0x00 << 1) | |
| 234 | #define DAC33_SRCLKSEL_PLL (0x01 << 1) | |
| 235 | #define DAC33_SRCLKSEL_MCLK (0x02 << 1) | |
| 236 | #define DAC33_SRCLKSEL_BCLK (0x03 << 1) | |
| 237 | #define DAC33_SRCLKDIV(x) (x << 3) | |
| 238 | ||
| 239 | /* DAC33_ASRC_CTRL_B (0x33) */ | |
| 240 | #define DAC33_SRCSETUP(x) (x << 0) | |
| 241 | #define DAC33_SRCREFSEL (0x01 << 4) | |
| 242 | #define DAC33_SRCREFDIV(x) (x << 5) | |
| 243 | ||
| 244 | /* DAC33_INTP_CTRL_A (0x38) */ | |
| 245 | #define DAC33_INTPSEL (0x01 << 0) | |
| 246 | #define DAC33_INTPM_MASK (0x03 << 1) | |
| 247 | #define DAC33_INTPM_ALOW_OPENDRAIN (0x00 << 1) | |
| 248 | #define DAC33_INTPM_ALOW (0x01 << 1) | |
| 249 | #define DAC33_INTPM_AHIGH (0x02 << 1) | |
| 250 | ||
| 251 | /* DAC33_LDAC_PWR_CTRL (0x40) */ | |
| 252 | /* DAC33_RDAC_PWR_CTRL (0x41) */ | |
| 253 | #define DAC33_DACLRNUM (0x01 << 2) | |
| 254 | #define DAC33_LROUT_GAIN(x) (x << 0) | |
| 255 | ||
| 256 | /* DAC33_ANA_VOL_SOFT_STEP_CTRL (0x49) */ | |
| 257 | #define DAC33_VOLCLKSEL (0x01 << 0) | |
| 258 | #define DAC33_VOLCLKEN (0x01 << 1) | |
| 259 | #define DAC33_VOLBYPASS (0x01 << 2) | |
| 260 | ||
| 261 | #define TLV320DAC33_MCLK 0 | |
| 262 | #define TLV320DAC33_SLEEPCLK 1 | |
| 263 | ||
| c8bf93f0 | 264 | #endif /* __TLV320DAC33_H */ |