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Merge tag 'v3.10.55' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / tlv320aic3x.c
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44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
c24fdc88 43#include <linux/of_gpio.h>
5a0e3ad6 44#include <linux/slab.h>
44d0a879
VB		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
44d0a879 49#include <sound/initval.h>
7565fc38 50#include <sound/tlv.h>
5193d62f 51#include <sound/tlv320aic3x.h>
44d0a879
VB		 52
53#include "tlv320aic3x.h"
54
07779fdd
JN		 55#define AIC3X_NUM_SUPPLIES 4
56static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
57 "IOVDD", /* I/O Voltage */
58 "DVDD", /* Digital Core Voltage */
59 "AVDD", /* Analog DAC Voltage */
60 "DRVDD", /* ADC Analog and Output Driver Voltage */
61};
44d0a879 62
414c73ab
JN		 63static LIST_HEAD(reset_list);
64
5a895f8a
JN		 65struct aic3x_priv;
66
67struct aic3x_disable_nb {
68 struct notifier_block nb;
69 struct aic3x_priv *aic3x;
70};
71
44d0a879
VB		 72/* codec private data */
73struct aic3x_priv {
5a895f8a 74 struct snd_soc_codec *codec;
07779fdd 75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 77 enum snd_soc_control_type control_type;
78 struct aic3x_setup_data *setup;
44d0a879 79 unsigned int sysclk;
414c73ab 80 struct list_head list;
44d0a879 81 int master;
5193d62f 82 int gpio_reset;
6c1a7d40 83 int power;
6184f105
RC		 84#define AIC3X_MODEL_3X 0
85#define AIC3X_MODEL_33 1
86#define AIC3X_MODEL_3007 2
87 u16 model;
e2e8bfdf
HG		 88
89 /* Selects the micbias voltage */
90 enum aic3x_micbias_voltage micbias_vg;
44d0a879
VB		 91};
92
93/*
94 * AIC3X register cache
95 * We can't read the AIC3X register space when we are
96 * using 2 wire for device control, so we cache them instead.
97 * There is no point in caching the reset register
98 */
99static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
100 0x00, 0x00, 0x00, 0x10, /* 0 */
101 0x04, 0x00, 0x00, 0x00, /* 4 */
102 0x00, 0x00, 0x00, 0x01, /* 8 */
103 0x00, 0x00, 0x00, 0x80, /* 12 */
104 0x80, 0xff, 0xff, 0x78, /* 16 */
105 0x78, 0x78, 0x78, 0x78, /* 20 */
106 0x78, 0x00, 0x00, 0xfe, /* 24 */
107 0x00, 0x00, 0xfe, 0x00, /* 28 */
108 0x18, 0x18, 0x00, 0x00, /* 32 */
109 0x00, 0x00, 0x00, 0x00, /* 36 */
110 0x00, 0x00, 0x00, 0x80, /* 40 */
111 0x80, 0x00, 0x00, 0x00, /* 44 */
112 0x00, 0x00, 0x00, 0x04, /* 48 */
113 0x00, 0x00, 0x00, 0x00, /* 52 */
114 0x00, 0x00, 0x04, 0x00, /* 56 */
115 0x00, 0x00, 0x00, 0x00, /* 60 */
116 0x00, 0x04, 0x00, 0x00, /* 64 */
117 0x00, 0x00, 0x00, 0x00, /* 68 */
118 0x04, 0x00, 0x00, 0x00, /* 72 */
119 0x00, 0x00, 0x00, 0x00, /* 76 */
120 0x00, 0x00, 0x00, 0x00, /* 80 */
121 0x00, 0x00, 0x00, 0x00, /* 84 */
122 0x00, 0x00, 0x00, 0x00, /* 88 */
123 0x00, 0x00, 0x00, 0x00, /* 92 */
124 0x00, 0x00, 0x00, 0x00, /* 96 */
c9e8e8d2
JP		 125 0x00, 0x00, 0x02, 0x00, /* 100 */
126 0x00, 0x00, 0x00, 0x00, /* 104 */
127 0x00, 0x00, /* 108 */
44d0a879
VB		 128};
129
44d0a879
VB		 130#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
131{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
132 .info = snd_soc_info_volsw, \
133 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
134 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
135
136/*
137 * All input lines are connected when !0xf and disconnected with 0xf bit field,
138 * so we have to use specific dapm_put call for input mixer
139 */
140static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
141 struct snd_ctl_elem_value *ucontrol)
142{
9d03545d
JN		 143 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
144 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
4453dba5
EN		 145 struct soc_mixer_control *mc =
146 (struct soc_mixer_control *)kcontrol->private_value;
147 unsigned int reg = mc->reg;
148 unsigned int shift = mc->shift;
149 int max = mc->max;
150 unsigned int mask = (1 << fls(max)) - 1;
151 unsigned int invert = mc->invert;
44d0a879
VB		 152 unsigned short val, val_mask;
153 int ret;
154 struct snd_soc_dapm_path *path;
155 int found = 0;
156
157 val = (ucontrol->value.integer.value[0] & mask);
158
159 mask = 0xf;
160 if (val)
161 val = mask;
162
163 if (invert)
164 val = mask - val;
165 val_mask = mask << shift;
166 val = val << shift;
167
168 mutex_lock(&widget->codec->mutex);
169
170 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
171 /* find dapm widget path assoc with kcontrol */
8ddab3f5 172 list_for_each_entry(path, &widget->dapm->card->paths, list) {
44d0a879
VB		 173 if (path->kcontrol != kcontrol)
174 continue;
175
176 /* found, now check type */
177 found = 1;
178 if (val)
179 /* new connection */
180 path->connect = invert ? 0 : 1;
181 else
182 /* old connection must be powered down */
183 path->connect = invert ? 1 : 0;
25c77c5f
MB		 184
185 dapm_mark_dirty(path->source, "tlv320aic3x source");
186 dapm_mark_dirty(path->sink, "tlv320aic3x sink");
187
44d0a879
VB		 188 break;
189 }
44d0a879
VB		 190 }
191
44d0a879 192 mutex_unlock(&widget->codec->mutex);
2894770e
AI		 193
194 if (found)
195 snd_soc_dapm_sync(widget->dapm);
196
197 ret = snd_soc_update_bits_locked(widget->codec, reg, val_mask, val);
44d0a879
VB		 198 return ret;
199}
200
e2e8bfdf
HG		 201/*
202 * mic bias power on/off share the same register bits with
203 * output voltage of mic bias. when power on mic bias, we
204 * need reclaim it to voltage value.
205 * 0x0 = Powered off
206 * 0x1 = MICBIAS output is powered to 2.0V,
207 * 0x2 = MICBIAS output is powered to 2.5V
208 * 0x3 = MICBIAS output is connected to AVDD
209 */
210static int mic_bias_event(struct snd_soc_dapm_widget *w,
211 struct snd_kcontrol *kcontrol, int event)
212{
213 struct snd_soc_codec *codec = w->codec;
214 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
215
216 switch (event) {
217 case SND_SOC_DAPM_POST_PMU:
218 /* change mic bias voltage to user defined */
219 snd_soc_update_bits(codec, MICBIAS_CTRL,
220 MICBIAS_LEVEL_MASK,
221 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
222 break;
223
224 case SND_SOC_DAPM_PRE_PMD:
225 snd_soc_update_bits(codec, MICBIAS_CTRL,
226 MICBIAS_LEVEL_MASK, 0);
227 break;
228 }
229 return 0;
230}
231
44d0a879
VB		 232static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
233static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
234static const char *aic3x_left_hpcom_mux[] =
235 { "differential of HPLOUT", "constant VCM", "single-ended" };
236static const char *aic3x_right_hpcom_mux[] =
237 { "differential of HPROUT", "constant VCM", "single-ended",
238 "differential of HPLCOM", "external feedback" };
239static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 240static const char *aic3x_adc_hpf[] =
241 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 242
243#define LDAC_ENUM 0
244#define RDAC_ENUM 1
245#define LHPCOM_ENUM 2
246#define RHPCOM_ENUM 3
404b5665
JN		 247#define LINE1L_2_L_ENUM 4
248#define LINE1L_2_R_ENUM 5
249#define LINE1R_2_L_ENUM 6
250#define LINE1R_2_R_ENUM 7
251#define LINE2L_ENUM 8
252#define LINE2R_ENUM 9
253#define ADC_HPF_ENUM 10
44d0a879
VB		 254
255static const struct soc_enum aic3x_enum[] = {
256 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
257 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
258 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
259 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
260 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
404b5665
JN		 261 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
262 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
44d0a879
VB		 263 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
264 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
265 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 266 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 267};
268
bb1daa80
JP		 269static const char *aic3x_agc_level[] =
270 { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" };
271static const struct soc_enum aic3x_agc_level_enum[] = {
272 SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level),
273 SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level),
274};
275
276static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" };
277static const struct soc_enum aic3x_agc_attack_enum[] = {
278 SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack),
279 SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack),
280};
281
282static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" };
283static const struct soc_enum aic3x_agc_decay_enum[] = {
284 SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay),
285 SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay),
286};
287
7565fc38
JN		 288/*
289 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
290 */
291static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
292/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
293static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
294/*
295 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
296 * Step size is approximately 0.5 dB over most of the scale but increasing
297 * near the very low levels.
298 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
299 * but having increasing dB difference below that (and where it doesn't count
300 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
301 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
302 */
303static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
304
44d0a879
VB		 305static const struct snd_kcontrol_new aic3x_snd_controls[] = {
306 /* Output */
7565fc38
JN		 307 SOC_DOUBLE_R_TLV("PCM Playback Volume",
308 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 309
098b1718
JN		 310 /*
311 * Output controls that map to output mixer switches. Note these are
312 * only for swapped L-to-R and R-to-L routes. See below stereo controls
313 * for direct L-to-L and R-to-R routes.
314 */
315 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
316 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
317 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
318 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
319 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
320 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
321
322 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
323 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
324 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
325 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
326 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
327 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
328
329 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
330 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
331 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
332 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
333 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
334 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
335
336 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
337 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
338 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
339 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
340 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
341 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
342
343 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
344 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
345 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
346 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
347 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
348 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
349
350 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
351 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
352 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
353 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
354 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
355 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
356
357 /* Stereo output controls for direct L-to-L and R-to-R routes */
358 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
359 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
360 0, 118, 1, output_stage_tlv),
361 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
362 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
363 0, 118, 1, output_stage_tlv),
7565fc38
JN		 364 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
365 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
366 0, 118, 1, output_stage_tlv),
098b1718
JN		 367
368 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
369 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 370 0, 118, 1, output_stage_tlv),
098b1718
JN		 371 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
372 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 373 0, 118, 1, output_stage_tlv),
7565fc38
JN		 374 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
375 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
376 0, 118, 1, output_stage_tlv),
098b1718
JN		 377
378 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
379 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 380 0, 118, 1, output_stage_tlv),
098b1718
JN		 381 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
382 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 383 0, 118, 1, output_stage_tlv),
7565fc38
JN		 384 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
385 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
386 0, 118, 1, output_stage_tlv),
098b1718
JN		 387
388 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
389 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 390 0, 118, 1, output_stage_tlv),
098b1718
JN		 391 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
392 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 393 0, 118, 1, output_stage_tlv),
7565fc38
JN		 394 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
395 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
396 0, 118, 1, output_stage_tlv),
098b1718
JN		 397
398 /* Output pin mute controls */
399 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
400 0x01, 0),
401 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
402 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
403 0x01, 0),
f9bc0297 404 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 405 0x01, 0),
44d0a879
VB		 406
407 /*
408 * Note: enable Automatic input Gain Controller with care. It can
409 * adjust PGA to max value when ADC is on and will never go back.
410 */
411 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
bb1daa80
JP		 412 SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]),
413 SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]),
414 SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]),
415 SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]),
416 SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]),
417 SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]),
44d0a879 418
77444191
JP		 419 /* De-emphasis */
420 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
44d0a879
VB		 421
422 /* Input */
7565fc38
JN		 423 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
424 0, 119, 0, adc_tlv),
44d0a879 425 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 426
427 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 428};
429
6184f105
RC		 430/*
431 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
432 */
433static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
434
435static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
14a95fe8 436 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
6184f105 437
44d0a879
VB		 438/* Left DAC Mux */
439static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
440SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
441
442/* Right DAC Mux */
443static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
444SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
445
446/* Left HPCOM Mux */
447static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
448SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
449
450/* Right HPCOM Mux */
451static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
452SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
453
c3b79e05
JN		 454/* Left Line Mixer */
455static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
456 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
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VB		 462};
463
c3b79e05
JN		 464/* Right Line Mixer */
465static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
466 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
470 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
472};
473
474/* Mono Mixer */
475static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
476 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
477 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
479 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
480 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
481 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
482};
483
484/* Left HP Mixer */
485static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
486 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
487 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
488 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
489 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
490 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
491 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
492};
493
494/* Right HP Mixer */
495static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
496 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
497 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
498 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
499 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
500 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
501 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
502};
503
504/* Left HPCOM Mixer */
505static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
506 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
507 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
508 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
509 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
510 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
511 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
512};
513
514/* Right HPCOM Mixer */
515static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
516 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
517 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
518 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
519 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
520 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
521 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
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VB		 522};
523
524/* Left PGA Mixer */
525static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
526 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 527 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
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VB		 528 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
529 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 530 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
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VB		 531};
532
533/* Right PGA Mixer */
534static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
535 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 536 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 537 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 538 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
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VB		 539 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
540};
541
542/* Left Line1 Mux */
404b5665
JN		 543static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
544SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
545static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
546SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
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VB		 547
548/* Right Line1 Mux */
404b5665
JN		 549static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
550SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
551static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
552SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
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VB		 553
554/* Left Line2 Mux */
555static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
556SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
557
558/* Right Line2 Mux */
559static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
560SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
561
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VB		 562static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
563 /* Left DAC to Left Outputs */
564 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
565 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
566 &aic3x_left_dac_mux_controls),
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VB		 567 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
568 &aic3x_left_hpcom_mux_controls),
569 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
570 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
571 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
572
573 /* Right DAC to Right Outputs */
574 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
575 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
576 &aic3x_right_dac_mux_controls),
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VB		 577 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
578 &aic3x_right_hpcom_mux_controls),
579 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
580 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
581 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
582
583 /* Mono Output */
584 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
585
54f01916 586 /* Inputs to Left ADC */
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VB		 587 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
588 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
589 &aic3x_left_pga_mixer_controls[0],
590 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
591 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 592 &aic3x_left_line1l_mux_controls),
54f01916 593 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 594 &aic3x_left_line1r_mux_controls),
44d0a879
VB		 595 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
596 &aic3x_left_line2_mux_controls),
597
54f01916 598 /* Inputs to Right ADC */
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VB		 599 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
600 LINE1R_2_RADC_CTRL, 2, 0),
601 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
602 &aic3x_right_pga_mixer_controls[0],
603 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916 604 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 605 &aic3x_right_line1l_mux_controls),
44d0a879 606 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 607 &aic3x_right_line1r_mux_controls),
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VB		 608 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
609 &aic3x_right_line2_mux_controls),
610
ee15ffdb
JN		 611 /*
612 * Not a real mic bias widget but similar function. This is for dynamic
613 * control of GPIO1 digital mic modulator clock output function when
614 * using digital mic.
615 */
616 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
617 AIC3X_GPIO1_REG, 4, 0xf,
618 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
619 AIC3X_GPIO1_FUNC_DISABLED),
620
621 /*
622 * Also similar function like mic bias. Selects digital mic with
623 * configurable oversampling rate instead of ADC converter.
624 */
625 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
626 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
627 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
628 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
629 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
630 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
631
44d0a879 632 /* Mic Bias */
e2e8bfdf
HG		 633 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
634 mic_bias_event,
635 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
44d0a879 636
c3b79e05
JN		 637 /* Output mixers */
638 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
639 &aic3x_left_line_mixer_controls[0],
640 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
641 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
642 &aic3x_right_line_mixer_controls[0],
643 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
644 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
645 &aic3x_mono_mixer_controls[0],
646 ARRAY_SIZE(aic3x_mono_mixer_controls)),
647 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
648 &aic3x_left_hp_mixer_controls[0],
649 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
650 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
651 &aic3x_right_hp_mixer_controls[0],
652 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
653 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
654 &aic3x_left_hpcom_mixer_controls[0],
655 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
656 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
657 &aic3x_right_hpcom_mixer_controls[0],
658 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
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VB		 659
660 SND_SOC_DAPM_OUTPUT("LLOUT"),
661 SND_SOC_DAPM_OUTPUT("RLOUT"),
662 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
663 SND_SOC_DAPM_OUTPUT("HPLOUT"),
664 SND_SOC_DAPM_OUTPUT("HPROUT"),
665 SND_SOC_DAPM_OUTPUT("HPLCOM"),
666 SND_SOC_DAPM_OUTPUT("HPRCOM"),
667
668 SND_SOC_DAPM_INPUT("MIC3L"),
669 SND_SOC_DAPM_INPUT("MIC3R"),
670 SND_SOC_DAPM_INPUT("LINE1L"),
671 SND_SOC_DAPM_INPUT("LINE1R"),
672 SND_SOC_DAPM_INPUT("LINE2L"),
673 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 674
675 /*
676 * Virtual output pin to detection block inside codec. This can be
677 * used to keep codec bias on if gpio or detection features are needed.
678 * Force pin on or construct a path with an input jack and mic bias
679 * widgets.
680 */
681 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 682};
683
6184f105
RC		 684static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
685 /* Class-D outputs */
686 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
687 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
688
689 SND_SOC_DAPM_OUTPUT("SPOP"),
690 SND_SOC_DAPM_OUTPUT("SPOM"),
691};
692
d0cc0d3a 693static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 694 /* Left Input */
695 {"Left Line1L Mux", "single-ended", "LINE1L"},
696 {"Left Line1L Mux", "differential", "LINE1L"},
697
698 {"Left Line2L Mux", "single-ended", "LINE2L"},
699 {"Left Line2L Mux", "differential", "LINE2L"},
700
701 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 702 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
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VB		 703 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
704 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 705 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
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VB		 706
707 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 708 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 709
710 /* Right Input */
711 {"Right Line1R Mux", "single-ended", "LINE1R"},
712 {"Right Line1R Mux", "differential", "LINE1R"},
713
714 {"Right Line2R Mux", "single-ended", "LINE2R"},
715 {"Right Line2R Mux", "differential", "LINE2R"},
716
54f01916 717 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 718 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
719 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 720 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
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VB		 721 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
722
723 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 724 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 725
ee15ffdb
JN		 726 /*
727 * Logical path between digital mic enable and GPIO1 modulator clock
728 * output function
729 */
730 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
731 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
732 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 733
734 /* Left DAC Output */
735 {"Left DAC Mux", "DAC_L1", "Left DAC"},
736 {"Left DAC Mux", "DAC_L2", "Left DAC"},
737 {"Left DAC Mux", "DAC_L3", "Left DAC"},
738
739 /* Right DAC Output */
740 {"Right DAC Mux", "DAC_R1", "Right DAC"},
741 {"Right DAC Mux", "DAC_R2", "Right DAC"},
742 {"Right DAC Mux", "DAC_R3", "Right DAC"},
743
744 /* Left Line Output */
745 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
746 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
747 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
748 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
749 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
750 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
751
752 {"Left Line Out", NULL, "Left Line Mixer"},
753 {"Left Line Out", NULL, "Left DAC Mux"},
754 {"LLOUT", NULL, "Left Line Out"},
755
756 /* Right Line Output */
757 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
758 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
759 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
760 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
761 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
762 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
763
764 {"Right Line Out", NULL, "Right Line Mixer"},
765 {"Right Line Out", NULL, "Right DAC Mux"},
766 {"RLOUT", NULL, "Right Line Out"},
767
768 /* Mono Output */
769 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
770 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
771 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
772 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
773 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
774 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
775
776 {"Mono Out", NULL, "Mono Mixer"},
777 {"MONO_LOUT", NULL, "Mono Out"},
778
779 /* Left HP Output */
780 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
781 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
782 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
783 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
784 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
785 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
786
787 {"Left HP Out", NULL, "Left HP Mixer"},
788 {"Left HP Out", NULL, "Left DAC Mux"},
789 {"HPLOUT", NULL, "Left HP Out"},
790
791 /* Right HP Output */
792 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
793 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
794 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
795 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
796 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
797 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
798
799 {"Right HP Out", NULL, "Right HP Mixer"},
800 {"Right HP Out", NULL, "Right DAC Mux"},
801 {"HPROUT", NULL, "Right HP Out"},
802
803 /* Left HPCOM Output */
804 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
805 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
806 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
807 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
808 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
809 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
810
811 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
812 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
813 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
814 {"Left HP Com", NULL, "Left HPCOM Mux"},
815 {"HPLCOM", NULL, "Left HP Com"},
816
817 /* Right HPCOM Output */
818 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
819 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
820 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
821 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
822 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
823 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
824
825 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
826 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
827 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
828 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
829 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
830 {"Right HP Com", NULL, "Right HPCOM Mux"},
831 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 832};
833
6184f105
RC		 834static const struct snd_soc_dapm_route intercon_3007[] = {
835 /* Class-D outputs */
836 {"Left Class-D Out", NULL, "Left Line Out"},
837 {"Right Class-D Out", NULL, "Left Line Out"},
838 {"SPOP", NULL, "Left Class-D Out"},
839 {"SPOM", NULL, "Right Class-D Out"},
840};
841
44d0a879
VB		 842static int aic3x_add_widgets(struct snd_soc_codec *codec)
843{
6184f105 844 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 845 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 846
ce6120cc 847 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
d0cc0d3a 848 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 849
850 /* set up audio path interconnects */
ce6120cc 851 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
44d0a879 852
6184f105 853 if (aic3x->model == AIC3X_MODEL_3007) {
ce6120cc 854 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 855 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 856 snd_soc_dapm_add_routes(dapm, intercon_3007,
857 ARRAY_SIZE(intercon_3007));
6184f105
RC		 858 }
859
44d0a879
VB		 860 return 0;
861}
862
44d0a879 863static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 864 struct snd_pcm_hw_params *params,
865 struct snd_soc_dai *dai)
44d0a879 866{
e6968a17 867 struct snd_soc_codec *codec = dai->codec;
b2c812e2 868 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 869 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 870 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
871 u16 d, pll_d = 1;
255173b4 872 int clk;
44d0a879 873
4f9c16cc 874 /* select data word length */
e18eca43 875 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 876 switch (params_format(params)) {
877 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 878 break;
4f9c16cc
DM		 879 case SNDRV_PCM_FORMAT_S20_3LE:
880 data |= (0x01 << 4);
44d0a879 881 break;
4f9c16cc
DM		 882 case SNDRV_PCM_FORMAT_S24_LE:
883 data |= (0x02 << 4);
44d0a879 884 break;
4f9c16cc
DM		 885 case SNDRV_PCM_FORMAT_S32_LE:
886 data |= (0x03 << 4);
44d0a879
VB		 887 break;
888 }
e18eca43 889 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 890
891 /* Fsref can be 44100 or 48000 */
892 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
893
894 /* Try to find a value for Q which allows us to bypass the PLL and
895 * generate CODEC_CLK directly. */
896 for (pll_q = 2; pll_q < 18; pll_q++)
897 if (aic3x->sysclk / (128 * pll_q) == fsref) {
898 bypass_pll = 1;
899 break;
900 }
901
902 if (bypass_pll) {
903 pll_q &= 0xf;
e18eca43
JN		 904 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
905 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 906 /* disable PLL if it is bypassed */
9c173d15 907 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
06c71282
C		 908
909 } else {
e18eca43 910 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 911 /* enable PLL when it is used */
9c173d15
AL		 912 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
913 PLL_ENABLE, PLL_ENABLE);
06c71282 914 }
4f9c16cc
DM		 915
916 /* Route Left DAC to left channel input and
917 * right DAC to right channel input */
918 data = (LDAC2LCH | RDAC2RCH);
919 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
920 if (params_rate(params) >= 64000)
921 data |= DUAL_RATE_MODE;
e18eca43 922 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 923
924 /* codec sample rate select */
4f9c16cc
DM		 925 data = (fsref * 20) / params_rate(params);
926 if (params_rate(params) < 64000)
927 data /= 2;
928 data /= 5;
929 data -= 2;
44d0a879 930 data |= (data << 4);
e18eca43 931 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 932
4f9c16cc
DM		 933 if (bypass_pll)
934 return 0;
935
25985edc 936 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 937 * one wins the game. Try with d==0 first, next with d!=0.
938 * Constraints for j are according to the datasheet.
4f9c16cc 939 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 940 */
255173b4 941
4f9c16cc
DM		 942 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
943
944 for (r = 1; r <= 16; r++)
945 for (p = 1; p <= 8; p++) {
255173b4
PM		 946 for (j = 4; j <= 55; j++) {
947 /* This is actually 1000*((j+(d/10000))*r)/p
948 * The term had to be converted to get
949 * rid of the division by 10000; d = 0 here
950 */
5baf8315 951 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 952
953 /* Check whether this values get closer than
954 * the best ones we had before
955 */
5baf8315 956 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 957 abs(codec_clk - last_clk)) {
958 pll_j = j; pll_d = 0;
959 pll_r = r; pll_p = p;
5baf8315 960 last_clk = tmp_clk;
255173b4
PM		 961 }
962
963 /* Early exit for exact matches */
5baf8315 964 if (tmp_clk == codec_clk)
255173b4
PM		 965 goto found;
966 }
967 }
4f9c16cc 968
255173b4
PM		 969 /* try with d != 0 */
970 for (p = 1; p <= 8; p++) {
971 j = codec_clk * p / 1000;
4f9c16cc 972
255173b4
PM		 973 if (j < 4 || j > 11)
974 continue;
4f9c16cc 975
255173b4
PM		 976 /* do not use codec_clk here since we'd loose precision */
977 d = ((2048 * p * fsref) - j * aic3x->sysclk)
978 * 100 / (aic3x->sysclk/100);
4f9c16cc 979
255173b4 980 clk = (10000 * j + d) / (10 * p);
4f9c16cc 981
255173b4
PM		 982 /* check whether this values get closer than the best
983 * ones we had before */
984 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
985 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
986 last_clk = clk;
4f9c16cc
DM		 987 }
988
255173b4
PM		 989 /* Early exit for exact matches */
990 if (clk == codec_clk)
991 goto found;
992 }
993
4f9c16cc
DM		 994 if (last_clk == 0) {
995 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
996 return -EINVAL;
997 }
44d0a879 998
255173b4 999found:
c9fe573a 1000 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
e18eca43
JN		 1001 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1002 pll_r << PLLR_SHIFT);
1003 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1004 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
1005 (pll_d >> 6) << PLLD_MSB_SHIFT);
1006 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
1007 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 1008
44d0a879
VB		 1009 return 0;
1010}
1011
e550e17f 1012static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 1013{
1014 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 1015 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
1016 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 1017
1018 if (mute) {
e18eca43
JN		 1019 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1020 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 1021 } else {
e18eca43
JN		 1022 snd_soc_write(codec, LDAC_VOL, ldac_reg);
1023 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 1024 }
1025
1026 return 0;
1027}
1028
e550e17f 1029static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1030 int clk_id, unsigned int freq, int dir)
1031{
1032 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1033 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1034
a1f34af0
JP		 1035 /* set clock on MCLK or GPIO2 or BCLK */
1036 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1037 clk_id << PLLCLK_IN_SHIFT);
1038 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1039 clk_id << CLKDIV_IN_SHIFT);
1040
4f9c16cc
DM		 1041 aic3x->sysclk = freq;
1042 return 0;
44d0a879
VB		 1043}
1044
e550e17f 1045static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1046 unsigned int fmt)
1047{
1048 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1049 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 1050 u8 iface_areg, iface_breg;
a24f4f68 1051 int delay = 0;
81971a14 1052
e18eca43
JN		 1053 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1054 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1055
1056 /* set master/slave audio interface */
1057 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1058 case SND_SOC_DAIFMT_CBM_CFM:
1059 aic3x->master = 1;
1060 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1061 break;
1062 case SND_SOC_DAIFMT_CBS_CFS:
1063 aic3x->master = 0;
68e47981 1064 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
44d0a879
VB		 1065 break;
1066 default:
1067 return -EINVAL;
1068 }
1069
4b7d2831
JN		 1070 /*
1071 * match both interface format and signal polarities since they
1072 * are fixed
1073 */
1074 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1075 SND_SOC_DAIFMT_INV_MASK)) {
1076 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1077 break;
a24f4f68
TK		 1078 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1079 delay = 1;
4b7d2831 1080 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1081 iface_breg |= (0x01 << 6);
1082 break;
4b7d2831 1083 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1084 iface_breg |= (0x02 << 6);
1085 break;
4b7d2831 1086 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1087 iface_breg |= (0x03 << 6);
1088 break;
1089 default:
1090 return -EINVAL;
1091 }
1092
1093 /* set iface */
e18eca43
JN		 1094 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1095 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1096 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1097
1098 return 0;
1099}
1100
6c1a7d40
JN		 1101static int aic3x_init_3007(struct snd_soc_codec *codec)
1102{
1103 u8 tmp1, tmp2, *cache = codec->reg_cache;
1104
1105 /*
1106 * There is no need to cache writes to undocumented page 0xD but
1107 * respective page 0 register cache entries must be preserved
1108 */
1109 tmp1 = cache[0xD];
1110 tmp2 = cache[0x8];
1111 /* Class-D speaker driver init; datasheet p. 46 */
1112 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1113 snd_soc_write(codec, 0xD, 0x0D);
1114 snd_soc_write(codec, 0x8, 0x5C);
1115 snd_soc_write(codec, 0x8, 0x5D);
1116 snd_soc_write(codec, 0x8, 0x5C);
1117 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1118 cache[0xD] = tmp1;
1119 cache[0x8] = tmp2;
1120
1121 return 0;
1122}
1123
5a895f8a
JN		 1124static int aic3x_regulator_event(struct notifier_block *nb,
1125 unsigned long event, void *data)
1126{
1127 struct aic3x_disable_nb *disable_nb =
1128 container_of(nb, struct aic3x_disable_nb, nb);
1129 struct aic3x_priv *aic3x = disable_nb->aic3x;
1130
1131 if (event & REGULATOR_EVENT_DISABLE) {
1132 /*
1133 * Put codec to reset and require cache sync as at least one
1134 * of the supplies was disabled
1135 */
79ee820d 1136 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a
JN		 1137 gpio_set_value(aic3x->gpio_reset, 0);
1138 aic3x->codec->cache_sync = 1;
1139 }
1140
1141 return 0;
1142}
1143
6c1a7d40
JN		 1144static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1145{
1146 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1147 int i, ret;
1148 u8 *cache = codec->reg_cache;
1149
1150 if (power) {
1151 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1152 aic3x->supplies);
1153 if (ret)
1154 goto out;
1155 aic3x->power = 1;
5a895f8a
JN		 1156 /*
1157 * Reset release and cache sync is necessary only if some
1158 * supply was off or if there were cached writes
1159 */
1160 if (!codec->cache_sync)
1161 goto out;
1162
79ee820d 1163 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1164 udelay(1);
1165 gpio_set_value(aic3x->gpio_reset, 1);
1166 }
1167
1168 /* Sync reg_cache with the hardware */
1169 codec->cache_only = 0;
508b7686 1170 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
6c1a7d40
JN		 1171 snd_soc_write(codec, i, cache[i]);
1172 if (aic3x->model == AIC3X_MODEL_3007)
1173 aic3x_init_3007(codec);
1174 codec->cache_sync = 0;
1175 } else {
9fb352b1
JN		 1176 /*
1177 * Do soft reset to this codec instance in order to clear
1178 * possible VDD leakage currents in case the supply regulators
1179 * remain on
1180 */
1181 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1182 codec->cache_sync = 1;
6c1a7d40 1183 aic3x->power = 0;
5a895f8a
JN		 1184 /* HW writes are needless when bias is off */
1185 codec->cache_only = 1;
6c1a7d40
JN		 1186 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1187 aic3x->supplies);
1188 }
1189out:
1190 return ret;
1191}
1192
0be9898a
MB		 1193static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1194 enum snd_soc_bias_level level)
44d0a879 1195{
b2c812e2 1196 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1197
0be9898a
MB		 1198 switch (level) {
1199 case SND_SOC_BIAS_ON:
db13802e
JN		 1200 break;
1201 case SND_SOC_BIAS_PREPARE:
ce6120cc 1202 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1203 aic3x->master) {
44d0a879 1204 /* enable pll */
9c173d15
AL		 1205 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1206 PLL_ENABLE, PLL_ENABLE);
44d0a879
VB		 1207 }
1208 break;
0be9898a 1209 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1210 if (!aic3x->power)
1211 aic3x_set_power(codec, 1);
ce6120cc 1212 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1213 aic3x->master) {
44d0a879 1214 /* disable pll */
9c173d15
AL		 1215 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1216 PLL_ENABLE, 0);
44d0a879
VB		 1217 }
1218 break;
c23fd751 1219 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1220 if (aic3x->power)
1221 aic3x_set_power(codec, 0);
c23fd751 1222 break;
44d0a879 1223 }
ce6120cc 1224 codec->dapm.bias_level = level;
44d0a879
VB		 1225
1226 return 0;
1227}
1228
1229#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1230#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1231 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1232
85e7652d 1233static const struct snd_soc_dai_ops aic3x_dai_ops = {
6335d055
EM		 1234 .hw_params = aic3x_hw_params,
1235 .digital_mute = aic3x_mute,
1236 .set_sysclk = aic3x_set_dai_sysclk,
1237 .set_fmt = aic3x_set_dai_fmt,
1238};
1239
f0fba2ad
LG		 1240static struct snd_soc_dai_driver aic3x_dai = {
1241 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1242 .playback = {
1243 .stream_name = "Playback",
06378da4 1244 .channels_min = 2,
44d0a879
VB		 1245 .channels_max = 2,
1246 .rates = AIC3X_RATES,
1247 .formats = AIC3X_FORMATS,},
1248 .capture = {
1249 .stream_name = "Capture",
06378da4 1250 .channels_min = 2,
44d0a879
VB		 1251 .channels_max = 2,
1252 .rates = AIC3X_RATES,
1253 .formats = AIC3X_FORMATS,},
6335d055 1254 .ops = &aic3x_dai_ops,
14017615 1255 .symmetric_rates = 1,
44d0a879 1256};
44d0a879 1257
84b315ee 1258static int aic3x_suspend(struct snd_soc_codec *codec)
44d0a879 1259{
0be9898a 1260 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1261
1262 return 0;
1263}
1264
f0fba2ad 1265static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1266{
29e189c2 1267 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1268
1269 return 0;
1270}
1271
1272/*
1273 * initialise the AIC3X driver
1274 * register the mixer and dsp interfaces with the kernel
1275 */
cb3826f5 1276static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1277{
6184f105 1278 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5 1279
e18eca43
JN		 1280 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1281 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1282
44d0a879 1283 /* DAC default volume and mute */
e18eca43
JN		 1284 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1285 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1286
1287 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1288 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1289 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1290 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1291 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1292 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1293 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1294 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1295 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1296 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1297 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1298
1299 /* unmute all outputs */
9c173d15
AL		 1300 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1301 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1302 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1303 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1304 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1305 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1306 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
44d0a879
VB		 1307
1308 /* ADC default volume and unmute */
e18eca43
JN		 1309 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1310 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1311 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1312 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1313 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1314
1315 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1316 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1317 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1318 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1319 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1320 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1321 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1322 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1323 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1324 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1325 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1326
1327 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1328 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1329 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1330 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1331 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1332 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1333 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1334 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1335 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1336 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1337 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1338
6184f105 1339 if (aic3x->model == AIC3X_MODEL_3007) {
6c1a7d40 1340 aic3x_init_3007(codec);
e18eca43 1341 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1342 }
1343
cb3826f5
BD		 1344 return 0;
1345}
54e7e616 1346
414c73ab
JN		 1347static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1348{
1349 struct aic3x_priv *a;
1350
1351 list_for_each_entry(a, &reset_list, list) {
1352 if (gpio_is_valid(aic3x->gpio_reset) &&
1353 aic3x->gpio_reset == a->gpio_reset)
1354 return true;
1355 }
1356
1357 return false;
1358}
1359
f0fba2ad 1360static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1361{
f0fba2ad 1362 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1363 int ret, i;
f0fba2ad 1364
414c73ab 1365 INIT_LIST_HEAD(&aic3x->list);
5a895f8a 1366 aic3x->codec = codec;
cb3826f5 1367
a84a441b
JN		 1368 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1369 if (ret != 0) {
1370 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1371 return ret;
1372 }
1373
414c73ab
JN		 1374 if (gpio_is_valid(aic3x->gpio_reset) &&
1375 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1376 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1377 if (ret != 0)
1378 goto err_gpio;
1379 gpio_direction_output(aic3x->gpio_reset, 0);
1380 }
1381
1382 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1383 aic3x->supplies[i].supply = aic3x_supply_names[i];
1384
1385 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1386 aic3x->supplies);
1387 if (ret != 0) {
1388 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1389 goto err_get;
1390 }
5a895f8a
JN		 1391 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1392 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1393 aic3x->disable_nb[i].aic3x = aic3x;
1394 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1395 &aic3x->disable_nb[i].nb);
1396 if (ret) {
1397 dev_err(codec->dev,
1398 "Failed to request regulator notifier: %d\n",
1399 ret);
1400 goto err_notif;
1401 }
1402 }
2f24111a 1403
7d1be0a6 1404 codec->cache_only = 1;
37b47656
JN		 1405 aic3x_init(codec);
1406
f0fba2ad
LG		 1407 if (aic3x->setup) {
1408 /* setup GPIO functions */
e18eca43
JN		 1409 snd_soc_write(codec, AIC3X_GPIO1_REG,
1410 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1411 snd_soc_write(codec, AIC3X_GPIO2_REG,
1412 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1413 }
1414
022658be 1415 snd_soc_add_codec_controls(codec, aic3x_snd_controls,
f0fba2ad 1416 ARRAY_SIZE(aic3x_snd_controls));
6184f105 1417 if (aic3x->model == AIC3X_MODEL_3007)
022658be 1418 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1419
e2e8bfdf
HG		 1420 /* set mic bias voltage */
1421 switch (aic3x->micbias_vg) {
1422 case AIC3X_MICBIAS_2_0V:
1423 case AIC3X_MICBIAS_2_5V:
1424 case AIC3X_MICBIAS_AVDDV:
1425 snd_soc_update_bits(codec, MICBIAS_CTRL,
1426 MICBIAS_LEVEL_MASK,
1427 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1428 break;
1429 case AIC3X_MICBIAS_OFF:
1430 /*
1431 * noting to do. target won't enter here. This is just to avoid
1432 * compile time warning "warning: enumeration value
1433 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1434 */
1435 break;
1436 }
1437
f0fba2ad 1438 aic3x_add_widgets(codec);
414c73ab 1439 list_add(&aic3x->list, &reset_list);
cb3826f5
BD		 1440
1441 return 0;
2f24111a 1442
5a895f8a
JN		 1443err_notif:
1444 while (i--)
1445 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1446 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1447 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1448err_get:
414c73ab
JN		 1449 if (gpio_is_valid(aic3x->gpio_reset) &&
1450 !aic3x_is_shared_reset(aic3x))
2f24111a
JN		 1451 gpio_free(aic3x->gpio_reset);
1452err_gpio:
2f24111a 1453 return ret;
44d0a879
VB		 1454}
1455
f0fba2ad 1456static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1457{
2f24111a 1458 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1459 int i;
2f24111a 1460
f0fba2ad 1461 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
414c73ab
JN		 1462 list_del(&aic3x->list);
1463 if (gpio_is_valid(aic3x->gpio_reset) &&
1464 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1465 gpio_set_value(aic3x->gpio_reset, 0);
1466 gpio_free(aic3x->gpio_reset);
1467 }
5a895f8a
JN		 1468 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1469 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1470 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1471 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1472
cb3826f5
BD		 1473 return 0;
1474}
44d0a879 1475
f0fba2ad 1476static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad 1477 .set_bias_level = aic3x_set_bias_level,
eb3032f8 1478 .idle_bias_off = true,
f0fba2ad
LG		 1479 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1480 .reg_word_size = sizeof(u8),
1481 .reg_cache_default = aic3x_reg,
1482 .probe = aic3x_probe,
1483 .remove = aic3x_remove,
1484 .suspend = aic3x_suspend,
1485 .resume = aic3x_resume,
1486};
1487
44d0a879
VB		 1488/*
1489 * AIC3X 2 wire address can be up to 4 devices with device addresses
1490 * 0x18, 0x19, 0x1A, 0x1B
1491 */
44d0a879 1492
6184f105 1493static const struct i2c_device_id aic3x_i2c_id[] = {
177fdd89
AL		 1494 { "tlv320aic3x", AIC3X_MODEL_3X },
1495 { "tlv320aic33", AIC3X_MODEL_33 },
1496 { "tlv320aic3007", AIC3X_MODEL_3007 },
6184f105
RC		 1497 { }
1498};
1499MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1500
44d0a879
VB		 1501/*
1502 * If the i2c layer weren't so broken, we could pass this kind of data
1503 * around
1504 */
ba8ed121
JD		 1505static int aic3x_i2c_probe(struct i2c_client *i2c,
1506 const struct i2c_device_id *id)
44d0a879 1507{
5193d62f 1508 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1509 struct aic3x_priv *aic3x;
c24fdc88
HG		 1510 struct aic3x_setup_data *ai3x_setup;
1511 struct device_node *np = i2c->dev.of_node;
2f24111a 1512 int ret;
e2e8bfdf 1513 u32 value;
44d0a879 1514
e2257db3 1515 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
cb3826f5
BD		 1516 if (aic3x == NULL) {
1517 dev_err(&i2c->dev, "failed to create private data\n");
1518 return -ENOMEM;
1519 }
1520
a84a441b
JN		 1521 aic3x->control_type = SND_SOC_I2C;
1522
cb3826f5 1523 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1524 if (pdata) {
1525 aic3x->gpio_reset = pdata->gpio_reset;
1526 aic3x->setup = pdata->setup;
e2e8bfdf 1527 aic3x->micbias_vg = pdata->micbias_vg;
c24fdc88
HG		 1528 } else if (np) {
1529 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1530 GFP_KERNEL);
1531 if (ai3x_setup == NULL) {
1532 dev_err(&i2c->dev, "failed to create private data\n");
1533 return -ENOMEM;
1534 }
1535
1536 ret = of_get_named_gpio(np, "gpio-reset", 0);
1537 if (ret >= 0)
1538 aic3x->gpio_reset = ret;
1539 else
1540 aic3x->gpio_reset = -1;
1541
1542 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1543 ai3x_setup->gpio_func, 2) >= 0) {
1544 aic3x->setup = ai3x_setup;
1545 }
1546
e2e8bfdf
HG		 1547 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1548 switch (value) {
1549 case 1 :
1550 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1551 break;
1552 case 2 :
1553 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1554 break;
1555 case 3 :
1556 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1557 break;
1558 default :
1559 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1560 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1561 "found in DT\n");
1562 }
1563 } else {
1564 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1565 }
1566
c776357e
JN		 1567 } else {
1568 aic3x->gpio_reset = -1;
1569 }
cb3826f5 1570
177fdd89 1571 aic3x->model = id->driver_data;
6184f105 1572
f0fba2ad
LG		 1573 ret = snd_soc_register_codec(&i2c->dev,
1574 &soc_codec_dev_aic3x, &aic3x_dai, 1);
07779fdd 1575 return ret;
44d0a879
VB		 1576}
1577
ba8ed121 1578static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1579{
f0fba2ad 1580 snd_soc_unregister_codec(&client->dev);
f0fba2ad 1581 return 0;
44d0a879
VB		 1582}
1583
c24fdc88
HG		 1584#if defined(CONFIG_OF)
1585static const struct of_device_id tlv320aic3x_of_match[] = {
1586 { .compatible = "ti,tlv320aic3x", },
1587 {},
1588};
1589MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1590#endif
1591
44d0a879
VB		 1592/* machine i2c codec control layer */
1593static struct i2c_driver aic3x_i2c_driver = {
1594 .driver = {
f0fba2ad 1595 .name = "tlv320aic3x-codec",
44d0a879 1596 .owner = THIS_MODULE,
c24fdc88 1597 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
44d0a879 1598 },
cb3826f5 1599 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1600 .remove = aic3x_i2c_remove,
1601 .id_table = aic3x_i2c_id,
44d0a879 1602};
44d0a879 1603
fd39d14b 1604module_i2c_driver(aic3x_i2c_driver);
64089b84 1605
44d0a879
VB		 1606MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1607MODULE_AUTHOR("Vladimir Barinov");
1608MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)