[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / jz4740.c

/*
 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/regmap.h>

#include <linux/delay.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>

#define JZ4740_REG_CODEC_1 0x0
#define JZ4740_REG_CODEC_2 0x4

#define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
#define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
#define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
#define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
#define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
#define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
#define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
#define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
#define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
#define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
#define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
#define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
#define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
#define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
#define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
#define JZ4740_CODEC_1_SUSPEND BIT(1)
#define JZ4740_CODEC_1_RESET BIT(0)

#define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
#define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
#define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
#define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
#define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
#define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
#define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8

#define JZ4740_CODEC_2_INPUT_VOLUME_MASK		0x1f0000
#define JZ4740_CODEC_2_SAMPLE_RATE_MASK			0x000f00
#define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK		0x000030
#define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK	0x000003

#define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET		16
#define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET		 8
#define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET	 4
#define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET	 0

static const struct reg_default jz4740_codec_reg_defaults[] = {
	{ JZ4740_REG_CODEC_1, 0x021b2302 },
	{ JZ4740_REG_CODEC_2, 0x00170803 },
};

struct jz4740_codec {
	struct regmap *regmap;
};

static const unsigned int jz4740_mic_tlv[] = {
	TLV_DB_RANGE_HEAD(2),
	0, 2, TLV_DB_SCALE_ITEM(0, 600, 0),
	3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0),
};

static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0);
static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0);

static const struct snd_kcontrol_new jz4740_codec_controls[] = {
	SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2,
			JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0,
			jz4740_out_tlv),
	SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2,
			JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0,
			jz4740_in_tlv),
	SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
	SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2,
			JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0,
			jz4740_mic_tlv),
};

static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
	SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
	SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
};

static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
	SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
	SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
};

static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
	SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
	SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),

	SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
			jz4740_codec_output_controls,
			ARRAY_SIZE(jz4740_codec_output_controls)),

	SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
			jz4740_codec_input_controls,
			ARRAY_SIZE(jz4740_codec_input_controls)),
	SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),

	SND_SOC_DAPM_OUTPUT("LOUT"),
	SND_SOC_DAPM_OUTPUT("ROUT"),

	SND_SOC_DAPM_INPUT("MIC"),
	SND_SOC_DAPM_INPUT("LIN"),
	SND_SOC_DAPM_INPUT("RIN"),
};

static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
	{"Line Input", NULL, "LIN"},
	{"Line Input", NULL, "RIN"},

	{"Input Mixer", "Line Capture Switch", "Line Input"},
	{"Input Mixer", "Mic Capture Switch", "MIC"},

	{"ADC", NULL, "Input Mixer"},

	{"Output Mixer", "Bypass Switch", "Input Mixer"},
	{"Output Mixer", "DAC Switch", "DAC"},

	{"LOUT", NULL, "Output Mixer"},
	{"ROUT", NULL, "Output Mixer"},
};

static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(dai->codec);
	uint32_t val;

	switch (params_rate(params)) {
	case 8000:
		val = 0;
		break;
	case 11025:
		val = 1;
		break;
	case 12000:
		val = 2;
		break;
	case 16000:
		val = 3;
		break;
	case 22050:
		val = 4;
		break;
	case 24000:
		val = 5;
		break;
	case 32000:
		val = 6;
		break;
	case 44100:
		val = 7;
		break;
	case 48000:
		val = 8;
		break;
	default:
		return -EINVAL;
	}

	val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;

	regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_2,
				JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);

	return 0;
}

static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
	.hw_params = jz4740_codec_hw_params,
};

static struct snd_soc_dai_driver jz4740_codec_dai = {
	.name = "jz4740-hifi",
	.playback = {
		.stream_name = "Playback",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
	},
	.capture = {
		.stream_name = "Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
	},
	.ops = &jz4740_codec_dai_ops,
	.symmetric_rates = 1,
};

static void jz4740_codec_wakeup(struct regmap *regmap)
{
	regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
		JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
	udelay(2);

	regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
		JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0);

	regcache_sync(regmap);
}

static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
	enum snd_soc_bias_level level)
{
	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
	struct regmap *regmap = jz4740_codec->regmap;
	unsigned int mask;
	unsigned int value;

	switch (level) {
	case SND_SOC_BIAS_ON:
		break;
	case SND_SOC_BIAS_PREPARE:
		mask = JZ4740_CODEC_1_VREF_DISABLE |
				JZ4740_CODEC_1_VREF_AMP_DISABLE |
				JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
		value = 0;

		regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
		break;
	case SND_SOC_BIAS_STANDBY:
		/* The only way to clear the suspend flag is to reset the codec */
		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
			jz4740_codec_wakeup(regmap);

		mask = JZ4740_CODEC_1_VREF_DISABLE |
			JZ4740_CODEC_1_VREF_AMP_DISABLE |
			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
		value = JZ4740_CODEC_1_VREF_DISABLE |
			JZ4740_CODEC_1_VREF_AMP_DISABLE |
			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;

		regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
		break;
	case SND_SOC_BIAS_OFF:
		mask = JZ4740_CODEC_1_SUSPEND;
		value = JZ4740_CODEC_1_SUSPEND;

		regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
		regcache_mark_dirty(regmap);
		break;
	default:
		break;
	}

	codec->dapm.bias_level = level;

	return 0;
}

static int jz4740_codec_dev_probe(struct snd_soc_codec *codec)
{
	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);

	regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);

	jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);

	return 0;
}

static int jz4740_codec_dev_remove(struct snd_soc_codec *codec)
{
	jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);

	return 0;
}

#ifdef CONFIG_PM_SLEEP

static int jz4740_codec_suspend(struct snd_soc_codec *codec)
{
	return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
}

static int jz4740_codec_resume(struct snd_soc_codec *codec)
{
	return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
}

#else
#define jz4740_codec_suspend NULL
#define jz4740_codec_resume NULL
#endif

static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = {
	.probe = jz4740_codec_dev_probe,
	.remove = jz4740_codec_dev_remove,
	.suspend = jz4740_codec_suspend,
	.resume = jz4740_codec_resume,
	.set_bias_level = jz4740_codec_set_bias_level,

	.controls = jz4740_codec_controls,
	.num_controls = ARRAY_SIZE(jz4740_codec_controls),
	.dapm_widgets = jz4740_codec_dapm_widgets,
	.num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
	.dapm_routes = jz4740_codec_dapm_routes,
	.num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
};

static const struct regmap_config jz4740_codec_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = JZ4740_REG_CODEC_2,

	.reg_defaults = jz4740_codec_reg_defaults,
	.num_reg_defaults = ARRAY_SIZE(jz4740_codec_reg_defaults),
	.cache_type = REGCACHE_RBTREE,
};

static int jz4740_codec_probe(struct platform_device *pdev)
{
	int ret;
	struct jz4740_codec *jz4740_codec;
	struct resource *mem;
	void __iomem *base;

	jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
				    GFP_KERNEL);
	if (!jz4740_codec)
		return -ENOMEM;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(base))
		return PTR_ERR(base);

	jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
					    &jz4740_codec_regmap_config);
	if (IS_ERR(jz4740_codec->regmap))
		return PTR_ERR(jz4740_codec->regmap);

	platform_set_drvdata(pdev, jz4740_codec);

	ret = snd_soc_register_codec(&pdev->dev,
			&soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
	if (ret)
		dev_err(&pdev->dev, "Failed to register codec\n");

	return ret;
}

static int jz4740_codec_remove(struct platform_device *pdev)
{
	snd_soc_unregister_codec(&pdev->dev);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver jz4740_codec_driver = {
	.probe = jz4740_codec_probe,
	.remove = jz4740_codec_remove,
	.driver = {
		.name = "jz4740-codec",
		.owner = THIS_MODULE,
	},
};

module_platform_driver(jz4740_codec_driver);

MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:jz4740-codec");
Commit	Line	Data
3b097d64 LPC	1	/*
	2	* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* You should have received a copy of the GNU General Public License along
	9	* with this program; if not, write to the Free Software Foundation, Inc.,
	10	* 675 Mass Ave, Cambridge, MA 02139, USA.
	11	*
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/slab.h>
68bfcafa	18	#include <linux/io.h>
dd1b18ab	19	#include <linux/regmap.h>
3b097d64 LPC	20
	21	#include <linux/delay.h>
	22
	23	#include <sound/core.h>
	24	#include <sound/pcm.h>
	25	#include <sound/pcm_params.h>
	26	#include <sound/initval.h>
3b097d64	27	#include <sound/soc.h>
a484a9a3	28	#include <sound/tlv.h>
3b097d64 LPC	29
3b097d64 LPC	30	#define JZ4740_REG_CODEC_1 0x0
dd1b18ab	31	#define JZ4740_REG_CODEC_2 0x4
3b097d64 LPC	32
	33	#define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
	34	#define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
	35	#define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
	36	#define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
	37	#define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
	38	#define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
	39	#define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
	40	#define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
	41	#define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
	42	#define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
	43	#define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
	44	#define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
	45	#define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
	46	#define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
	47	#define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) \| BIT(10))
	48	#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
	49	#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
	50	#define JZ4740_CODEC_1_SUSPEND BIT(1)
	51	#define JZ4740_CODEC_1_RESET BIT(0)
	52
	53	#define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
	54	#define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
	55	#define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
	56	#define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
	57	#define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
	58	#define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
	59	#define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
	60	#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
	61
	62	#define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
	63	#define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
	64	#define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
	65	#define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
	66
	67	#define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
	68	#define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
	69	#define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
	70	#define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
	71
dd1b18ab LPC	72	static const struct reg_default jz4740_codec_reg_defaults[] = {
	73	{ JZ4740_REG_CODEC_1, 0x021b2302 },
	74	{ JZ4740_REG_CODEC_2, 0x00170803 },
3b097d64 LPC	75	};
	76
	77	struct jz4740_codec {
dd1b18ab	78	struct regmap *regmap;
3b097d64 LPC	79	};
3b097d64 LPC	80
a484a9a3 LPC	81	static const unsigned int jz4740_mic_tlv[] = {
	82	TLV_DB_RANGE_HEAD(2),
	83	0, 2, TLV_DB_SCALE_ITEM(0, 600, 0),
	84	3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0),
	85	};
	86
	87	static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0);
	88	static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0);
	89
3b097d64	90	static const struct snd_kcontrol_new jz4740_codec_controls[] = {
a484a9a3 LPC	91	SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2,
	92	JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0,
	93	jz4740_out_tlv),
	94	SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2,
	95	JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0,
	96	jz4740_in_tlv),
3b097d64 LPC	97	SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
3b097d64 LPC	98	JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
a484a9a3 LPC	99	SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2,
	100	JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0,
	101	jz4740_mic_tlv),
3b097d64 LPC	102	};
	103
	104	static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
	105	SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
	106	JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
	107	SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
	108	JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
	109	};
	110
	111	static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
	112	SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
	113	JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
	114	SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
	115	JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
	116	};
	117
	118	static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
	119	SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
	120	JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
	121	SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
	122	JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
	123
	124	SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
	125	JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
	126	jz4740_codec_output_controls,
	127	ARRAY_SIZE(jz4740_codec_output_controls)),
	128
	129	SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
	130	jz4740_codec_input_controls,
	131	ARRAY_SIZE(jz4740_codec_input_controls)),
	132	SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
	133
	134	SND_SOC_DAPM_OUTPUT("LOUT"),
	135	SND_SOC_DAPM_OUTPUT("ROUT"),
	136
	137	SND_SOC_DAPM_INPUT("MIC"),
	138	SND_SOC_DAPM_INPUT("LIN"),
	139	SND_SOC_DAPM_INPUT("RIN"),
	140	};
	141
	142	static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
	143	{"Line Input", NULL, "LIN"},
	144	{"Line Input", NULL, "RIN"},
	145
	146	{"Input Mixer", "Line Capture Switch", "Line Input"},
	147	{"Input Mixer", "Mic Capture Switch", "MIC"},
	148
	149	{"ADC", NULL, "Input Mixer"},
	150
	151	{"Output Mixer", "Bypass Switch", "Input Mixer"},
	152	{"Output Mixer", "DAC Switch", "DAC"},
	153
	154	{"LOUT", NULL, "Output Mixer"},
	155	{"ROUT", NULL, "Output Mixer"},
	156	};
	157
	158	static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
	159	struct snd_pcm_hw_params params, struct snd_soc_dai dai)
	160	{
dd1b18ab	161	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(dai->codec);
3b097d64	162	uint32_t val;
3b097d64 LPC	163
	164	switch (params_rate(params)) {
	165	case 8000:
	166	val = 0;
	167	break;
	168	case 11025:
	169	val = 1;
	170	break;
	171	case 12000:
	172	val = 2;
	173	break;
	174	case 16000:
	175	val = 3;
	176	break;
	177	case 22050:
	178	val = 4;
	179	break;
	180	case 24000:
	181	val = 5;
	182	break;
	183	case 32000:
	184	val = 6;
	185	break;
	186	case 44100:
	187	val = 7;
	188	break;
	189	case 48000:
	190	val = 8;
	191	break;
	192	default:
	193	return -EINVAL;
	194	}
	195
	196	val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
	197
dd1b18ab	198	regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_2,
3b097d64 LPC	199	JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
	200
	201	return 0;
	202	}
	203
85e7652d	204	static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
3b097d64 LPC	205	.hw_params = jz4740_codec_hw_params,
	206	};
	207
f0fba2ad LG	208	static struct snd_soc_dai_driver jz4740_codec_dai = {
f0fba2ad LG	209	.name = "jz4740-hifi",
3b097d64 LPC	210	.playback = {
	211	.stream_name = "Playback",
	212	.channels_min = 2,
	213	.channels_max = 2,
	214	.rates = SNDRV_PCM_RATE_8000_48000,
	215	.formats = SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S8,
	216	},
	217	.capture = {
	218	.stream_name = "Capture",
	219	.channels_min = 2,
	220	.channels_max = 2,
	221	.rates = SNDRV_PCM_RATE_8000_48000,
	222	.formats = SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S8,
	223	},
	224	.ops = &jz4740_codec_dai_ops,
	225	.symmetric_rates = 1,
	226	};
3b097d64	227
dd1b18ab	228	static void jz4740_codec_wakeup(struct regmap *regmap)
3b097d64	229	{
dd1b18ab	230	regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
3b097d64 LPC	231	JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
	232	udelay(2);
	233
dd1b18ab	234	regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
3b097d64 LPC	235	JZ4740_CODEC_1_SUSPEND \| JZ4740_CODEC_1_RESET, 0);
3b097d64 LPC	236
dd1b18ab	237	regcache_sync(regmap);
3b097d64 LPC	238	}
	239
	240	static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
	241	enum snd_soc_bias_level level)
	242	{
dd1b18ab LPC	243	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
dd1b18ab LPC	244	struct regmap *regmap = jz4740_codec->regmap;
3b097d64 LPC	245	unsigned int mask;
	246	unsigned int value;
	247
	248	switch (level) {
	249	case SND_SOC_BIAS_ON:
	250	break;
	251	case SND_SOC_BIAS_PREPARE:
	252	mask = JZ4740_CODEC_1_VREF_DISABLE \|
	253	JZ4740_CODEC_1_VREF_AMP_DISABLE \|
	254	JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
	255	value = 0;
	256
dd1b18ab	257	regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
3b097d64 LPC	258	break;
	259	case SND_SOC_BIAS_STANDBY:
	260	/* The only way to clear the suspend flag is to reset the codec */
ce6120cc	261	if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
dd1b18ab	262	jz4740_codec_wakeup(regmap);
3b097d64 LPC	263
	264	mask = JZ4740_CODEC_1_VREF_DISABLE \|
	265	JZ4740_CODEC_1_VREF_AMP_DISABLE \|
	266	JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
	267	value = JZ4740_CODEC_1_VREF_DISABLE \|
	268	JZ4740_CODEC_1_VREF_AMP_DISABLE \|
	269	JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
	270
dd1b18ab	271	regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
3b097d64 LPC	272	break;
	273	case SND_SOC_BIAS_OFF:
	274	mask = JZ4740_CODEC_1_SUSPEND;
	275	value = JZ4740_CODEC_1_SUSPEND;
	276
dd1b18ab LPC	277	regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
dd1b18ab LPC	278	regcache_mark_dirty(regmap);
3b097d64 LPC	279	break;
	280	default:
	281	break;
	282	}
	283
ce6120cc	284	codec->dapm.bias_level = level;
3b097d64 LPC	285
	286	return 0;
	287	}
	288
f0fba2ad	289	static int jz4740_codec_dev_probe(struct snd_soc_codec *codec)
3b097d64	290	{
dd1b18ab LPC	291	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
	292
	293	regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_1,
f0fba2ad	294	JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
3b097d64	295
f0fba2ad LG	296	jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f0fba2ad LG	297
3b097d64 LPC	298	return 0;
	299	}
	300
f0fba2ad	301	static int jz4740_codec_dev_remove(struct snd_soc_codec *codec)
3b097d64	302	{
f0fba2ad	303	jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
3b097d64 LPC	304
	305	return 0;
	306	}
	307
	308	#ifdef CONFIG_PM_SLEEP
	309
84b315ee	310	static int jz4740_codec_suspend(struct snd_soc_codec *codec)
3b097d64	311	{
3b097d64 LPC	312	return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
	313	}
	314
f0fba2ad	315	static int jz4740_codec_resume(struct snd_soc_codec *codec)
3b097d64	316	{
3b097d64 LPC	317	return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	318	}
	319
	320	#else
	321	#define jz4740_codec_suspend NULL
	322	#define jz4740_codec_resume NULL
	323	#endif
	324
f0fba2ad	325	static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = {
3b097d64 LPC	326	.probe = jz4740_codec_dev_probe,
	327	.remove = jz4740_codec_dev_remove,
	328	.suspend = jz4740_codec_suspend,
	329	.resume = jz4740_codec_resume,
f0fba2ad	330	.set_bias_level = jz4740_codec_set_bias_level,
67447912 LPC	331
	332	.controls = jz4740_codec_controls,
	333	.num_controls = ARRAY_SIZE(jz4740_codec_controls),
	334	.dapm_widgets = jz4740_codec_dapm_widgets,
	335	.num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
	336	.dapm_routes = jz4740_codec_dapm_routes,
	337	.num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
3b097d64	338	};
3b097d64	339
dd1b18ab LPC	340	static const struct regmap_config jz4740_codec_regmap_config = {
	341	.reg_bits = 32,
	342	.reg_stride = 4,
	343	.val_bits = 32,
	344	.max_register = JZ4740_REG_CODEC_2,
	345
	346	.reg_defaults = jz4740_codec_reg_defaults,
	347	.num_reg_defaults = ARRAY_SIZE(jz4740_codec_reg_defaults),
	348	.cache_type = REGCACHE_RBTREE,
	349	};
	350
7a79e94e	351	static int jz4740_codec_probe(struct platform_device *pdev)
3b097d64 LPC	352	{
	353	int ret;
	354	struct jz4740_codec *jz4740_codec;
3b097d64	355	struct resource *mem;
dd1b18ab	356	void __iomem *base;
3b097d64	357
558460c6 AL	358	jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
558460c6 AL	359	GFP_KERNEL);
3b097d64 LPC	360	if (!jz4740_codec)
	361	return -ENOMEM;
	362
	363	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b25b5aa0 TR	364	base = devm_ioremap_resource(&pdev->dev, mem);
	365	if (IS_ERR(base))
	366	return PTR_ERR(base);
3b097d64	367
dd1b18ab LPC	368	jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
	369	&jz4740_codec_regmap_config);
	370	if (IS_ERR(jz4740_codec->regmap))
	371	return PTR_ERR(jz4740_codec->regmap);
	372
3b097d64 LPC	373	platform_set_drvdata(pdev, jz4740_codec);
3b097d64 LPC	374
f0fba2ad LG	375	ret = snd_soc_register_codec(&pdev->dev,
f0fba2ad LG	376	&soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
355d74b5	377	if (ret)
3b097d64	378	dev_err(&pdev->dev, "Failed to register codec\n");
3b097d64	379
3b097d64 LPC	380	return ret;
	381	}
	382
7a79e94e	383	static int jz4740_codec_remove(struct platform_device *pdev)
3b097d64	384	{
f0fba2ad	385	snd_soc_unregister_codec(&pdev->dev);
3b097d64	386
3b097d64	387	platform_set_drvdata(pdev, NULL);
3b097d64 LPC	388
	389	return 0;
	390	}
	391
	392	static struct platform_driver jz4740_codec_driver = {
	393	.probe = jz4740_codec_probe,
7a79e94e	394	.remove = jz4740_codec_remove,
3b097d64 LPC	395	.driver = {
	396	.name = "jz4740-codec",
	397	.owner = THIS_MODULE,
	398	},
	399	};
	400
5bbcc3c0	401	module_platform_driver(jz4740_codec_driver);
3b097d64 LPC	402
	403	MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
	404	MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
	405	MODULE_LICENSE("GPL v2");
	406	MODULE_ALIAS("platform:jz4740-codec");