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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / intel8x0m.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA modem driver for Intel ICH (i8x0) chipsets
3 *
c1017a4c 4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
1da177e4 5 *
f01cc521 6 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version
1da177e4
LT		 7 * of ALSA ICH sound driver intel8x0.c .
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
1da177e4
LT		 26#include <asm/io.h>
27#include <linux/delay.h>
28#include <linux/interrupt.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/slab.h>
65a77217 32#include <linux/module.h>
1da177e4
LT		 33#include <sound/core.h>
34#include <sound/pcm.h>
35#include <sound/ac97_codec.h>
36#include <sound/info.h>
1da177e4
LT		 37#include <sound/initval.h>
38
c1017a4c 39MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
6b75a9d8
TI		 40MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "
41 "SiS 7013; NVidia MCP/2/2S/3 modems");
1da177e4
LT		 42MODULE_LICENSE("GPL");
43MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
44 "{Intel,82901AB-ICH0},"
45 "{Intel,82801BA-ICH2},"
46 "{Intel,82801CA-ICH3},"
47 "{Intel,82801DB-ICH4},"
48 "{Intel,ICH5},"
49 "{Intel,ICH6},"
50 "{Intel,ICH7},"
51 "{Intel,MX440},"
52 "{SiS,7013},"
53 "{NVidia,NForce Modem},"
54 "{NVidia,NForce2 Modem},"
55 "{NVidia,NForce2s Modem},"
56 "{NVidia,NForce3 Modem},"
57 "{AMD,AMD768}}");
58
b7fe4622
CL		 59static int index = -2; /* Exclude the first card */
60static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
6581f4e7 61static int ac97_clock;
1da177e4 62
b7fe4622 63module_param(index, int, 0444);
1da177e4 64MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
b7fe4622 65module_param(id, charp, 0444);
1da177e4 66MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
b7fe4622 67module_param(ac97_clock, int, 0444);
1da177e4
LT		 68MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
69
2b3e584b 70/* just for backward compatibility */
a67ff6a5 71static bool enable;
698444f3 72module_param(enable, bool, 0444);
2b3e584b 73
1da177e4
LT		 74/*
75 * Direct registers
76 */
1da177e4
LT		 77enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
78
79#define ICHREG(x) ICH_REG_##x
80
81#define DEFINE_REGSET(name,base) \
82enum { \
83 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
84 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
85 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
86 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
87 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
88 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
89 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
90};
91
92/* busmaster blocks */
93DEFINE_REGSET(OFF, 0); /* offset */
94
95/* values for each busmaster block */
96
97/* LVI */
98#define ICH_REG_LVI_MASK 0x1f
99
100/* SR */
101#define ICH_FIFOE 0x10 /* FIFO error */
102#define ICH_BCIS 0x08 /* buffer completion interrupt status */
103#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
104#define ICH_CELV 0x02 /* current equals last valid */
105#define ICH_DCH 0x01 /* DMA controller halted */
106
107/* PIV */
108#define ICH_REG_PIV_MASK 0x1f /* mask */
109
110/* CR */
111#define ICH_IOCE 0x10 /* interrupt on completion enable */
112#define ICH_FEIE 0x08 /* fifo error interrupt enable */
113#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
114#define ICH_RESETREGS 0x02 /* reset busmaster registers */
115#define ICH_STARTBM 0x01 /* start busmaster operation */
116
117
118/* global block */
119#define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
120#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
121#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
122#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
123#define ICH_ACLINK 0x00000008 /* AClink shut off */
124#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
125#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
126#define ICH_GIE 0x00000001 /* GPI interrupt enable */
127#define ICH_REG_GLOB_STA 0x40 /* dword - global status */
128#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
129#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
130#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
131#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
132#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
133#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
134#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
135#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
136#define ICH_MD3 0x00020000 /* modem power down semaphore */
137#define ICH_AD3 0x00010000 /* audio power down semaphore */
138#define ICH_RCS 0x00008000 /* read completion status */
139#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
140#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
141#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
142#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
143#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
144#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
145#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
146#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
147#define ICH_POINT 0x00000040 /* playback interrupt */
148#define ICH_PIINT 0x00000020 /* capture interrupt */
149#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
150#define ICH_MOINT 0x00000004 /* modem playback interrupt */
151#define ICH_MIINT 0x00000002 /* modem capture interrupt */
152#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
153#define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
154#define ICH_CAS 0x01 /* codec access semaphore */
155
156#define ICH_MAX_FRAGS 32 /* max hw frags */
157
158
159/*
160 *
161 */
162
163enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
164enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
165
6b75a9d8 166#define get_ichdev(substream) (substream->runtime->private_data)
1da177e4 167
6b75a9d8 168struct ichdev {
1da177e4
LT		 169 unsigned int ichd; /* ich device number */
170 unsigned long reg_offset; /* offset to bmaddr */
171 u32 *bdbar; /* CPU address (32bit) */
172 unsigned int bdbar_addr; /* PCI bus address (32bit) */
6b75a9d8 173 struct snd_pcm_substream *substream;
1da177e4
LT		 174 unsigned int physbuf; /* physical address (32bit) */
175 unsigned int size;
176 unsigned int fragsize;
177 unsigned int fragsize1;
178 unsigned int position;
179 int frags;
180 int lvi;
181 int lvi_frag;
182 int civ;
183 int ack;
184 int ack_reload;
185 unsigned int ack_bit;
186 unsigned int roff_sr;
187 unsigned int roff_picb;
188 unsigned int int_sta_mask; /* interrupt status mask */
189 unsigned int ali_slot; /* ALI DMA slot */
6b75a9d8
TI		 190 struct snd_ac97 *ac97;
191};
1da177e4 192
6b75a9d8 193struct intel8x0m {
1da177e4
LT		 194 unsigned int device_type;
195
196 int irq;
197
3388c37e
TI		 198 void __iomem *addr;
199 void __iomem *bmaddr;
1da177e4
LT		 200
201 struct pci_dev *pci;
6b75a9d8 202 struct snd_card *card;
1da177e4
LT		 203
204 int pcm_devs;
6b75a9d8
TI		 205 struct snd_pcm *pcm[2];
206 struct ichdev ichd[2];
1da177e4
LT		 207
208 unsigned int in_ac97_init: 1;
209
6b75a9d8
TI		 210 struct snd_ac97_bus *ac97_bus;
211 struct snd_ac97 *ac97;
1da177e4
LT		 212
213 spinlock_t reg_lock;
214
215 struct snd_dma_buffer bdbars;
216 u32 bdbars_count;
217 u32 int_sta_reg; /* interrupt status register */
218 u32 int_sta_mask; /* interrupt status mask */
219 unsigned int pcm_pos_shift;
220};
221
cebe41d4 222static DEFINE_PCI_DEVICE_TABLE(snd_intel8x0m_ids) = {
28d27aae
JP		 223 { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL }, /* 82801AA */
224 { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL }, /* 82901AB */
225 { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL }, /* 82801BA */
226 { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL }, /* ICH3 */
227 { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */
228 { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */
229 { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL }, /* ICH6 */
230 { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL }, /* ICH7 */
231 { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL }, /* 440MX */
232 { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */
233 { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */
234 { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */
235 { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */
236 { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */
237 { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */
df1fe132 238 { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL }, /* AMD8111 */
1da177e4 239#if 0
28d27aae 240 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
1da177e4
LT		 241#endif
242 { 0, }
243};
1da177e4
LT		 244
245MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
246
1da177e4
LT		 247/*
248 * Lowlevel I/O - busmaster
249 */
250
3388c37e 251static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)
1da177e4 252{
3388c37e 253 return ioread8(chip->bmaddr + offset);
1da177e4
LT		 254}
255
3388c37e 256static inline u16 igetword(struct intel8x0m *chip, u32 offset)
1da177e4 257{
3388c37e 258 return ioread16(chip->bmaddr + offset);
1da177e4
LT		 259}
260
3388c37e 261static inline u32 igetdword(struct intel8x0m *chip, u32 offset)
1da177e4 262{
3388c37e 263 return ioread32(chip->bmaddr + offset);
1da177e4
LT		 264}
265
3388c37e 266static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)
1da177e4 267{
3388c37e 268 iowrite8(val, chip->bmaddr + offset);
1da177e4
LT		 269}
270
3388c37e 271static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)
1da177e4 272{
3388c37e 273 iowrite16(val, chip->bmaddr + offset);
1da177e4
LT		 274}
275
3388c37e 276static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)
1da177e4 277{
3388c37e 278 iowrite32(val, chip->bmaddr + offset);
1da177e4
LT		 279}
280
281/*
282 * Lowlevel I/O - AC'97 registers
283 */
284
3388c37e 285static inline u16 iagetword(struct intel8x0m *chip, u32 offset)
1da177e4 286{
3388c37e 287 return ioread16(chip->addr + offset);
1da177e4
LT		 288}
289
3388c37e 290static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
1da177e4 291{
3388c37e 292 iowrite16(val, chip->addr + offset);
1da177e4
LT		 293}
294
295/*
296 * Basic I/O
297 */
298
299/*
300 * access to AC97 codec via normal i/o (for ICH and SIS7013)
301 */
302
303/* return the GLOB_STA bit for the corresponding codec */
6b75a9d8 304static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)
1da177e4
LT		 305{
306 static unsigned int codec_bit[3] = {
307 ICH_PCR, ICH_SCR, ICH_TCR
308 };
da3cec35
TI		 309 if (snd_BUG_ON(codec >= 3))
310 return ICH_PCR;
1da177e4
LT		 311 return codec_bit[codec];
312}
313
6b75a9d8 314static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)
1da177e4
LT		 315{
316 int time;
317
318 if (codec > 1)
319 return -EIO;
320 codec = get_ich_codec_bit(chip, codec);
321
322 /* codec ready ? */
323 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
324 return -EIO;
325
326 /* Anyone holding a semaphore for 1 msec should be shot... */
327 time = 100;
328 do {
329 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
330 return 0;
331 udelay(10);
332 } while (time--);
333
25985edc 334 /* access to some forbidden (non existent) ac97 registers will not
1da177e4
LT		 335 * reset the semaphore. So even if you don't get the semaphore, still
336 * continue the access. We don't need the semaphore anyway. */
99b359ba 337 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
1da177e4
LT		 338 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
339 iagetword(chip, 0); /* clear semaphore flag */
340 /* I don't care about the semaphore */
341 return -EBUSY;
342}
343
a6e8509f
PB		 344static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97,
345 unsigned short reg,
346 unsigned short val)
1da177e4 347{
6b75a9d8 348 struct intel8x0m *chip = ac97->private_data;
1da177e4
LT		 349
350 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
351 if (! chip->in_ac97_init)
99b359ba 352 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 353 }
354 iaputword(chip, reg + ac97->num * 0x80, val);
355}
356
a6e8509f
PB		 357static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97,
358 unsigned short reg)
1da177e4 359{
6b75a9d8 360 struct intel8x0m *chip = ac97->private_data;
1da177e4
LT		 361 unsigned short res;
362 unsigned int tmp;
363
364 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
365 if (! chip->in_ac97_init)
99b359ba 366 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 367 res = 0xffff;
368 } else {
369 res = iagetword(chip, reg + ac97->num * 0x80);
370 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
371 /* reset RCS and preserve other R/WC bits */
6b75a9d8
TI		 372 iputdword(chip, ICHREG(GLOB_STA),
373 tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
1da177e4 374 if (! chip->in_ac97_init)
99b359ba 375 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 376 res = 0xffff;
377 }
378 }
2c56c47f
SK		 379 if (reg == AC97_GPIO_STATUS)
380 iagetword(chip, 0); /* clear semaphore */
1da177e4
LT		 381 return res;
382}
383
384
385/*
386 * DMA I/O
387 */
a6e8509f 388static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)
1da177e4
LT		 389{
390 int idx;
391 u32 *bdbar = ichdev->bdbar;
392 unsigned long port = ichdev->reg_offset;
393
394 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
395 if (ichdev->size == ichdev->fragsize) {
396 ichdev->ack_reload = ichdev->ack = 2;
397 ichdev->fragsize1 = ichdev->fragsize >> 1;
398 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
399 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
400 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
401 ichdev->fragsize1 >> chip->pcm_pos_shift);
402 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
403 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
404 ichdev->fragsize1 >> chip->pcm_pos_shift);
405 }
406 ichdev->frags = 2;
407 } else {
408 ichdev->ack_reload = ichdev->ack = 1;
409 ichdev->fragsize1 = ichdev->fragsize;
410 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
411 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
412 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
413 ichdev->fragsize >> chip->pcm_pos_shift);
14ab0861
TI		 414 /*
415 printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
416 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
417 */
1da177e4
LT		 418 }
419 ichdev->frags = ichdev->size / ichdev->fragsize;
420 }
421 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
422 ichdev->civ = 0;
423 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
424 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
425 ichdev->position = 0;
426#if 0
14ab0861
TI		 427 printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
428 "period_size1 = 0x%x\n",
429 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
430 ichdev->fragsize1);
1da177e4
LT		 431#endif
432 /* clear interrupts */
433 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
434}
435
436/*
437 * Interrupt handler
438 */
439
a6e8509f 440static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev)
1da177e4
LT		 441{
442 unsigned long port = ichdev->reg_offset;
443 int civ, i, step;
444 int ack = 0;
445
446 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
447 if (civ == ichdev->civ) {
448 // snd_printd("civ same %d\n", civ);
449 step = 1;
450 ichdev->civ++;
451 ichdev->civ &= ICH_REG_LVI_MASK;
452 } else {
453 step = civ - ichdev->civ;
454 if (step < 0)
455 step += ICH_REG_LVI_MASK + 1;
456 // if (step != 1)
457 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
458 ichdev->civ = civ;
459 }
460
461 ichdev->position += step * ichdev->fragsize1;
462 ichdev->position %= ichdev->size;
463 ichdev->lvi += step;
464 ichdev->lvi &= ICH_REG_LVI_MASK;
465 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
466 for (i = 0; i < step; i++) {
467 ichdev->lvi_frag++;
468 ichdev->lvi_frag %= ichdev->frags;
6b75a9d8
TI		 469 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +
470 ichdev->lvi_frag *
471 ichdev->fragsize1);
472#if 0
14ab0861
TI		 473 printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], "
474 "prefetch = %i, all = 0x%x, 0x%x\n",
6b75a9d8
TI		 475 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
476 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
477 inl(port + 4), inb(port + ICH_REG_OFF_CR));
478#endif
1da177e4
LT		 479 if (--ichdev->ack == 0) {
480 ichdev->ack = ichdev->ack_reload;
481 ack = 1;
482 }
483 }
484 if (ack && ichdev->substream) {
485 spin_unlock(&chip->reg_lock);
486 snd_pcm_period_elapsed(ichdev->substream);
487 spin_lock(&chip->reg_lock);
488 }
489 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
490}
491
a6e8509f 492static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id)
1da177e4 493{
6b75a9d8
TI		 494 struct intel8x0m *chip = dev_id;
495 struct ichdev *ichdev;
1da177e4
LT		 496 unsigned int status;
497 unsigned int i;
498
499 spin_lock(&chip->reg_lock);
500 status = igetdword(chip, chip->int_sta_reg);
501 if (status == 0xffffffff) { /* we are not yet resumed */
502 spin_unlock(&chip->reg_lock);
503 return IRQ_NONE;
504 }
505 if ((status & chip->int_sta_mask) == 0) {
506 if (status)
507 iputdword(chip, chip->int_sta_reg, status);
508 spin_unlock(&chip->reg_lock);
509 return IRQ_NONE;
510 }
511
512 for (i = 0; i < chip->bdbars_count; i++) {
513 ichdev = &chip->ichd[i];
514 if (status & ichdev->int_sta_mask)
a6e8509f 515 snd_intel8x0m_update(chip, ichdev);
1da177e4
LT		 516 }
517
518 /* ack them */
519 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
520 spin_unlock(&chip->reg_lock);
521
522 return IRQ_HANDLED;
523}
524
525/*
526 * PCM part
527 */
528
a6e8509f 529static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 530{
6b75a9d8
TI		 531 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
532 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 533 unsigned char val = 0;
534 unsigned long port = ichdev->reg_offset;
535
536 switch (cmd) {
537 case SNDRV_PCM_TRIGGER_START:
538 case SNDRV_PCM_TRIGGER_RESUME:
539 val = ICH_IOCE | ICH_STARTBM;
540 break;
541 case SNDRV_PCM_TRIGGER_STOP:
542 case SNDRV_PCM_TRIGGER_SUSPEND:
543 val = 0;
544 break;
545 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
546 val = ICH_IOCE;
547 break;
548 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
549 val = ICH_IOCE | ICH_STARTBM;
550 break;
551 default:
552 return -EINVAL;
553 }
554 iputbyte(chip, port + ICH_REG_OFF_CR, val);
555 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
556 /* wait until DMA stopped */
557 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
558 /* reset whole DMA things */
559 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
560 }
561 return 0;
562}
563
a6e8509f 564static int snd_intel8x0m_hw_params(struct snd_pcm_substream *substream,
6b75a9d8 565 struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 566{
567 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
568}
569
a6e8509f 570static int snd_intel8x0m_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 571{
572 return snd_pcm_lib_free_pages(substream);
573}
574
a6e8509f 575static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 576{
6b75a9d8
TI		 577 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
578 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 579 size_t ptr1, ptr;
580
581 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
582 if (ptr1 != 0)
583 ptr = ichdev->fragsize1 - ptr1;
584 else
585 ptr = 0;
586 ptr += ichdev->position;
587 if (ptr >= ichdev->size)
588 return 0;
589 return bytes_to_frames(substream->runtime, ptr);
590}
591
6b75a9d8 592static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 593{
6b75a9d8
TI		 594 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
595 struct snd_pcm_runtime *runtime = substream->runtime;
596 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 597
598 ichdev->physbuf = runtime->dma_addr;
599 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
600 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
601 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
602 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
a6e8509f 603 snd_intel8x0m_setup_periods(chip, ichdev);
1da177e4
LT		 604 return 0;
605}
606
6b75a9d8 607static struct snd_pcm_hardware snd_intel8x0m_stream =
1da177e4
LT		 608{
609 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
610 SNDRV_PCM_INFO_BLOCK_TRANSFER |
611 SNDRV_PCM_INFO_MMAP_VALID |
612 SNDRV_PCM_INFO_PAUSE |
613 SNDRV_PCM_INFO_RESUME),
614 .formats = SNDRV_PCM_FMTBIT_S16_LE,
615 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
616 .rate_min = 8000,
617 .rate_max = 16000,
618 .channels_min = 1,
619 .channels_max = 1,
620 .buffer_bytes_max = 64 * 1024,
621 .period_bytes_min = 32,
622 .period_bytes_max = 64 * 1024,
623 .periods_min = 1,
624 .periods_max = 1024,
625 .fifo_size = 0,
626};
627
628
6b75a9d8 629static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1da177e4
LT		 630{
631 static unsigned int rates[] = { 8000, 9600, 12000, 16000 };
6b75a9d8 632 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1da177e4
LT		 633 .count = ARRAY_SIZE(rates),
634 .list = rates,
635 .mask = 0,
636 };
6b75a9d8 637 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 638 int err;
639
640 ichdev->substream = substream;
641 runtime->hw = snd_intel8x0m_stream;
6b75a9d8
TI		 642 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
643 &hw_constraints_rates);
1da177e4
LT		 644 if ( err < 0 )
645 return err;
646 runtime->private_data = ichdev;
647 return 0;
648}
649
6b75a9d8 650static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)
1da177e4 651{
6b75a9d8 652 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 653
654 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
655}
656
6b75a9d8 657static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)
1da177e4 658{
6b75a9d8 659 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 660
661 chip->ichd[ICHD_MDMOUT].substream = NULL;
662 return 0;
663}
664
6b75a9d8 665static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)
1da177e4 666{
6b75a9d8 667 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 668
669 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
670}
671
6b75a9d8 672static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)
1da177e4 673{
6b75a9d8 674 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 675
676 chip->ichd[ICHD_MDMIN].substream = NULL;
677 return 0;
678}
679
680
6b75a9d8 681static struct snd_pcm_ops snd_intel8x0m_playback_ops = {
1da177e4
LT		 682 .open = snd_intel8x0m_playback_open,
683 .close = snd_intel8x0m_playback_close,
684 .ioctl = snd_pcm_lib_ioctl,
a6e8509f
PB		 685 .hw_params = snd_intel8x0m_hw_params,
686 .hw_free = snd_intel8x0m_hw_free,
1da177e4 687 .prepare = snd_intel8x0m_pcm_prepare,
a6e8509f
PB		 688 .trigger = snd_intel8x0m_pcm_trigger,
689 .pointer = snd_intel8x0m_pcm_pointer,
1da177e4
LT		 690};
691
6b75a9d8 692static struct snd_pcm_ops snd_intel8x0m_capture_ops = {
1da177e4
LT		 693 .open = snd_intel8x0m_capture_open,
694 .close = snd_intel8x0m_capture_close,
695 .ioctl = snd_pcm_lib_ioctl,
a6e8509f
PB		 696 .hw_params = snd_intel8x0m_hw_params,
697 .hw_free = snd_intel8x0m_hw_free,
1da177e4 698 .prepare = snd_intel8x0m_pcm_prepare,
a6e8509f
PB		 699 .trigger = snd_intel8x0m_pcm_trigger,
700 .pointer = snd_intel8x0m_pcm_pointer,
1da177e4
LT		 701};
702
703
704struct ich_pcm_table {
705 char *suffix;
6b75a9d8
TI		 706 struct snd_pcm_ops *playback_ops;
707 struct snd_pcm_ops *capture_ops;
1da177e4
LT		 708 size_t prealloc_size;
709 size_t prealloc_max_size;
710 int ac97_idx;
711};
712
e23e7a14
BP		 713static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device,
714 struct ich_pcm_table *rec)
1da177e4 715{
6b75a9d8 716 struct snd_pcm *pcm;
1da177e4
LT		 717 int err;
718 char name[32];
719
720 if (rec->suffix)
721 sprintf(name, "Intel ICH - %s", rec->suffix);
722 else
723 strcpy(name, "Intel ICH");
724 err = snd_pcm_new(chip->card, name, device,
725 rec->playback_ops ? 1 : 0,
726 rec->capture_ops ? 1 : 0, &pcm);
727 if (err < 0)
728 return err;
729
730 if (rec->playback_ops)
731 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
732 if (rec->capture_ops)
733 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
734
735 pcm->private_data = chip;
736 pcm->info_flags = 0;
6632d198 737 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1da177e4
LT		 738 if (rec->suffix)
739 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
740 else
741 strcpy(pcm->name, chip->card->shortname);
742 chip->pcm[device] = pcm;
743
744 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
745 snd_dma_pci_data(chip->pci),
746 rec->prealloc_size,
747 rec->prealloc_max_size);
748
749 return 0;
750}
751
e23e7a14 752static struct ich_pcm_table intel_pcms[] = {
1da177e4
LT		 753 {
754 .suffix = "Modem",
755 .playback_ops = &snd_intel8x0m_playback_ops,
756 .capture_ops = &snd_intel8x0m_capture_ops,
757 .prealloc_size = 32 * 1024,
758 .prealloc_max_size = 64 * 1024,
759 },
760};
761
e23e7a14 762static int snd_intel8x0m_pcm(struct intel8x0m *chip)
1da177e4
LT		 763{
764 int i, tblsize, device, err;
765 struct ich_pcm_table *tbl, *rec;
766
767#if 1
768 tbl = intel_pcms;
769 tblsize = 1;
770#else
771 switch (chip->device_type) {
772 case DEVICE_NFORCE:
773 tbl = nforce_pcms;
774 tblsize = ARRAY_SIZE(nforce_pcms);
775 break;
776 case DEVICE_ALI:
777 tbl = ali_pcms;
778 tblsize = ARRAY_SIZE(ali_pcms);
779 break;
780 default:
781 tbl = intel_pcms;
782 tblsize = 2;
783 break;
784 }
785#endif
786 device = 0;
787 for (i = 0; i < tblsize; i++) {
788 rec = tbl + i;
789 if (i > 0 && rec->ac97_idx) {
790 /* activate PCM only when associated AC'97 codec */
791 if (! chip->ichd[rec->ac97_idx].ac97)
792 continue;
793 }
a6e8509f 794 err = snd_intel8x0m_pcm1(chip, device, rec);
1da177e4
LT		 795 if (err < 0)
796 return err;
797 device++;
798 }
799
800 chip->pcm_devs = device;
801 return 0;
802}
803
804
805/*
806 * Mixer part
807 */
808
a6e8509f 809static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 810{
6b75a9d8 811 struct intel8x0m *chip = bus->private_data;
1da177e4
LT		 812 chip->ac97_bus = NULL;
813}
814
a6e8509f 815static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 816{
6b75a9d8 817 struct intel8x0m *chip = ac97->private_data;
1da177e4
LT		 818 chip->ac97 = NULL;
819}
820
821
e23e7a14 822static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock)
1da177e4 823{
6b75a9d8
TI		 824 struct snd_ac97_bus *pbus;
825 struct snd_ac97_template ac97;
826 struct snd_ac97 *x97;
1da177e4
LT		 827 int err;
828 unsigned int glob_sta = 0;
6b75a9d8 829 static struct snd_ac97_bus_ops ops = {
a6e8509f
PB		 830 .write = snd_intel8x0m_codec_write,
831 .read = snd_intel8x0m_codec_read,
1da177e4
LT		 832 };
833
834 chip->in_ac97_init = 1;
835
836 memset(&ac97, 0, sizeof(ac97));
837 ac97.private_data = chip;
a6e8509f 838 ac97.private_free = snd_intel8x0m_mixer_free_ac97;
f1a63a38 839 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
1da177e4
LT		 840
841 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
842
843 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
844 goto __err;
a6e8509f 845 pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus;
1da177e4
LT		 846 if (ac97_clock >= 8000 && ac97_clock <= 48000)
847 pbus->clock = ac97_clock;
848 chip->ac97_bus = pbus;
849
850 ac97.pci = chip->pci;
851 ac97.num = glob_sta & ICH_SCR ? 1 : 0;
852 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
853 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
854 if (ac97.num == 0)
855 goto __err;
856 return err;
857 }
858 chip->ac97 = x97;
859 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
860 chip->ichd[ICHD_MDMIN].ac97 = x97;
861 chip->ichd[ICHD_MDMOUT].ac97 = x97;
862 }
1da177e4
LT		 863
864 chip->in_ac97_init = 0;
865 return 0;
866
867 __err:
868 /* clear the cold-reset bit for the next chance */
869 if (chip->device_type != DEVICE_ALI)
6b75a9d8
TI		 870 iputdword(chip, ICHREG(GLOB_CNT),
871 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1da177e4
LT		 872 return err;
873}
874
875
876/*
877 *
878 */
879
6b75a9d8 880static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)
1da177e4
LT		 881{
882 unsigned long end_time;
883 unsigned int cnt, status, nstatus;
884
885 /* put logic to right state */
886 /* first clear status bits */
887 status = ICH_RCS | ICH_MIINT | ICH_MOINT;
888 cnt = igetdword(chip, ICHREG(GLOB_STA));
889 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
890
891 /* ACLink on, 2 channels */
892 cnt = igetdword(chip, ICHREG(GLOB_CNT));
893 cnt &= ~(ICH_ACLINK);
894 /* finish cold or do warm reset */
895 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
896 iputdword(chip, ICHREG(GLOB_CNT), cnt);
5cd2ad81
PB		 897 usleep_range(500, 1000); /* give warm reset some time */
898 end_time = jiffies + HZ / 4;
1da177e4
LT		 899 do {
900 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
901 goto __ok;
954bea35 902 schedule_timeout_uninterruptible(1);
1da177e4 903 } while (time_after_eq(end_time, jiffies));
6b75a9d8
TI		 904 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
905 igetdword(chip, ICHREG(GLOB_CNT)));
1da177e4
LT		 906 return -EIO;
907
908 __ok:
909 if (probing) {
910 /* wait for any codec ready status.
911 * Once it becomes ready it should remain ready
912 * as long as we do not disable the ac97 link.
913 */
914 end_time = jiffies + HZ;
915 do {
6b75a9d8
TI		 916 status = igetdword(chip, ICHREG(GLOB_STA)) &
917 (ICH_PCR | ICH_SCR | ICH_TCR);
1da177e4
LT		 918 if (status)
919 break;
954bea35 920 schedule_timeout_uninterruptible(1);
1da177e4
LT		 921 } while (time_after_eq(end_time, jiffies));
922 if (! status) {
923 /* no codec is found */
6b75a9d8
TI		 924 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
925 igetdword(chip, ICHREG(GLOB_STA)));
1da177e4
LT		 926 return -EIO;
927 }
928
929 /* up to two codecs (modem cannot be tertiary with ICH4) */
930 nstatus = ICH_PCR | ICH_SCR;
931
932 /* wait for other codecs ready status. */
933 end_time = jiffies + HZ / 4;
934 while (status != nstatus && time_after_eq(end_time, jiffies)) {
954bea35 935 schedule_timeout_uninterruptible(1);
1da177e4
LT		 936 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
937 }
938
939 } else {
940 /* resume phase */
941 status = 0;
942 if (chip->ac97)
943 status |= get_ich_codec_bit(chip, chip->ac97->num);
944 /* wait until all the probed codecs are ready */
945 end_time = jiffies + HZ;
946 do {
6b75a9d8
TI		 947 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
948 (ICH_PCR | ICH_SCR | ICH_TCR);
1da177e4
LT		 949 if (status == nstatus)
950 break;
954bea35 951 schedule_timeout_uninterruptible(1);
1da177e4
LT		 952 } while (time_after_eq(end_time, jiffies));
953 }
954
955 if (chip->device_type == DEVICE_SIS) {
956 /* unmute the output on SIS7012 */
957 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
958 }
959
960 return 0;
961}
962
a6e8509f 963static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing)
1da177e4
LT		 964{
965 unsigned int i;
966 int err;
967
968 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
969 return err;
970 iagetword(chip, 0); /* clear semaphore flag */
971
972 /* disable interrupts */
973 for (i = 0; i < chip->bdbars_count; i++)
974 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
975 /* reset channels */
976 for (i = 0; i < chip->bdbars_count; i++)
977 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
978 /* initialize Buffer Descriptor Lists */
979 for (i = 0; i < chip->bdbars_count; i++)
980 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
981 return 0;
982}
983
a6e8509f 984static int snd_intel8x0m_free(struct intel8x0m *chip)
1da177e4
LT		 985{
986 unsigned int i;
987
988 if (chip->irq < 0)
989 goto __hw_end;
990 /* disable interrupts */
991 for (i = 0; i < chip->bdbars_count; i++)
992 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
993 /* reset channels */
994 for (i = 0; i < chip->bdbars_count; i++)
995 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
ebf029da 996 __hw_end:
f000fd80 997 if (chip->irq >= 0)
ebf029da 998 free_irq(chip->irq, chip);
1da177e4
LT		 999 if (chip->bdbars.area)
1000 snd_dma_free_pages(&chip->bdbars);
3388c37e
TI		 1001 if (chip->addr)
1002 pci_iounmap(chip->pci, chip->addr);
1003 if (chip->bmaddr)
1004 pci_iounmap(chip->pci, chip->bmaddr);
1da177e4
LT		 1005 pci_release_regions(chip->pci);
1006 pci_disable_device(chip->pci);
1007 kfree(chip);
1008 return 0;
1009}
1010
c7561cd8 1011#ifdef CONFIG_PM_SLEEP
1da177e4
LT		 1012/*
1013 * power management
1014 */
68cb2b55 1015static int intel8x0m_suspend(struct device *dev)
1da177e4 1016{
68cb2b55
TI		 1017 struct pci_dev *pci = to_pci_dev(dev);
1018 struct snd_card *card = dev_get_drvdata(dev);
5809c6c4 1019 struct intel8x0m *chip = card->private_data;
1da177e4
LT		 1020 int i;
1021
5809c6c4 1022 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 1023 for (i = 0; i < chip->pcm_devs; i++)
1024 snd_pcm_suspend_all(chip->pcm[i]);
5809c6c4 1025 snd_ac97_suspend(chip->ac97);
30b35399 1026 if (chip->irq >= 0) {
f0063c44 1027 free_irq(chip->irq, chip);
30b35399
TI		 1028 chip->irq = -1;
1029 }
5809c6c4
TI		 1030 pci_disable_device(pci);
1031 pci_save_state(pci);
68cb2b55 1032 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 1033 return 0;
1034}
1035
68cb2b55 1036static int intel8x0m_resume(struct device *dev)
1da177e4 1037{
68cb2b55
TI		 1038 struct pci_dev *pci = to_pci_dev(dev);
1039 struct snd_card *card = dev_get_drvdata(dev);
5809c6c4
TI		 1040 struct intel8x0m *chip = card->private_data;
1041
30b35399 1042 pci_set_power_state(pci, PCI_D0);
5809c6c4 1043 pci_restore_state(pci);
30b35399
TI		 1044 if (pci_enable_device(pci) < 0) {
1045 printk(KERN_ERR "intel8x0m: pci_enable_device failed, "
1046 "disabling device\n");
1047 snd_card_disconnect(card);
1048 return -EIO;
1049 }
5809c6c4 1050 pci_set_master(pci);
a6e8509f 1051 if (request_irq(pci->irq, snd_intel8x0m_interrupt,
934c2b6d 1052 IRQF_SHARED, KBUILD_MODNAME, chip)) {
30b35399
TI		 1053 printk(KERN_ERR "intel8x0m: unable to grab IRQ %d, "
1054 "disabling device\n", pci->irq);
1055 snd_card_disconnect(card);
1056 return -EIO;
1057 }
f0063c44 1058 chip->irq = pci->irq;
a6e8509f 1059 snd_intel8x0m_chip_init(chip, 0);
5809c6c4 1060 snd_ac97_resume(chip->ac97);
1da177e4 1061
5809c6c4 1062 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 1063 return 0;
1064}
68cb2b55
TI		 1065
1066static SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume);
1067#define INTEL8X0M_PM_OPS &intel8x0m_pm
1068#else
1069#define INTEL8X0M_PM_OPS NULL
c7561cd8 1070#endif /* CONFIG_PM_SLEEP */
1da177e4 1071
adf1b3d2 1072#ifdef CONFIG_PROC_FS
6b75a9d8
TI		 1073static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,
1074 struct snd_info_buffer *buffer)
1da177e4 1075{
6b75a9d8 1076 struct intel8x0m *chip = entry->private_data;
1da177e4
LT		 1077 unsigned int tmp;
1078
1079 snd_iprintf(buffer, "Intel8x0m\n\n");
1080 if (chip->device_type == DEVICE_ALI)
1081 return;
1082 tmp = igetdword(chip, ICHREG(GLOB_STA));
6b75a9d8
TI		 1083 snd_iprintf(buffer, "Global control : 0x%08x\n",
1084 igetdword(chip, ICHREG(GLOB_CNT)));
1da177e4
LT		 1085 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
1086 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
1087 tmp & ICH_PCR ? " primary" : "",
1088 tmp & ICH_SCR ? " secondary" : "",
1089 tmp & ICH_TCR ? " tertiary" : "",
1090 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1091}
1092
e23e7a14 1093static void snd_intel8x0m_proc_init(struct intel8x0m *chip)
1da177e4 1094{
6b75a9d8 1095 struct snd_info_entry *entry;
1da177e4
LT		 1096
1097 if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
bf850204 1098 snd_info_set_text_ops(entry, chip, snd_intel8x0m_proc_read);
1da177e4 1099}
adf1b3d2
TI		 1100#else /* !CONFIG_PROC_FS */
1101#define snd_intel8x0m_proc_init(chip)
1102#endif /* CONFIG_PROC_FS */
1103
1da177e4 1104
a6e8509f 1105static int snd_intel8x0m_dev_free(struct snd_device *device)
1da177e4 1106{
6b75a9d8 1107 struct intel8x0m *chip = device->device_data;
a6e8509f 1108 return snd_intel8x0m_free(chip);
1da177e4
LT		 1109}
1110
1111struct ich_reg_info {
1112 unsigned int int_sta_mask;
1113 unsigned int offset;
1114};
1115
e23e7a14
BP		 1116static int snd_intel8x0m_create(struct snd_card *card,
1117 struct pci_dev *pci,
1118 unsigned long device_type,
1119 struct intel8x0m **r_intel8x0m)
1da177e4 1120{
6b75a9d8 1121 struct intel8x0m *chip;
1da177e4
LT		 1122 int err;
1123 unsigned int i;
1124 unsigned int int_sta_masks;
6b75a9d8
TI		 1125 struct ichdev *ichdev;
1126 static struct snd_device_ops ops = {
a6e8509f 1127 .dev_free = snd_intel8x0m_dev_free,
1da177e4
LT		 1128 };
1129 static struct ich_reg_info intel_regs[2] = {
1130 { ICH_MIINT, 0 },
1131 { ICH_MOINT, 0x10 },
1132 };
1133 struct ich_reg_info *tbl;
1134
966a7f0d 1135 *r_intel8x0m = NULL;
1da177e4
LT		 1136
1137 if ((err = pci_enable_device(pci)) < 0)
1138 return err;
1139
e560d8d8 1140 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1141 if (chip == NULL) {
1142 pci_disable_device(pci);
1143 return -ENOMEM;
1144 }
1145 spin_lock_init(&chip->reg_lock);
1146 chip->device_type = device_type;
1147 chip->card = card;
1148 chip->pci = pci;
1149 chip->irq = -1;
1150
1151 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
1152 kfree(chip);
1153 pci_disable_device(pci);
1154 return err;
1155 }
1156
1157 if (device_type == DEVICE_ALI) {
1158 /* ALI5455 has no ac97 region */
3388c37e 1159 chip->bmaddr = pci_iomap(pci, 0, 0);
1da177e4
LT		 1160 goto port_inited;
1161 }
1162
3388c37e
TI		 1163 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
1164 chip->addr = pci_iomap(pci, 2, 0);
1165 else
1166 chip->addr = pci_iomap(pci, 0, 0);
1167 if (!chip->addr) {
1168 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
a6e8509f 1169 snd_intel8x0m_free(chip);
3388c37e 1170 return -EIO;
1da177e4 1171 }
3388c37e
TI		 1172 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
1173 chip->bmaddr = pci_iomap(pci, 3, 0);
1174 else
1175 chip->bmaddr = pci_iomap(pci, 1, 0);
1176 if (!chip->bmaddr) {
1177 snd_printk(KERN_ERR "Controller space ioremap problem\n");
a6e8509f 1178 snd_intel8x0m_free(chip);
3388c37e 1179 return -EIO;
1da177e4
LT		 1180 }
1181
1182 port_inited:
a6e8509f 1183 if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED,
934c2b6d 1184 KBUILD_MODNAME, chip)) {
99b359ba 1185 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
a6e8509f 1186 snd_intel8x0m_free(chip);
1da177e4
LT		 1187 return -EBUSY;
1188 }
1189 chip->irq = pci->irq;
1190 pci_set_master(pci);
1191 synchronize_irq(chip->irq);
1192
1193 /* initialize offsets */
1194 chip->bdbars_count = 2;
1195 tbl = intel_regs;
1196
1197 for (i = 0; i < chip->bdbars_count; i++) {
1198 ichdev = &chip->ichd[i];
1199 ichdev->ichd = i;
1200 ichdev->reg_offset = tbl[i].offset;
1201 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1202 if (device_type == DEVICE_SIS) {
1203 /* SiS 7013 swaps the registers */
1204 ichdev->roff_sr = ICH_REG_OFF_PICB;
1205 ichdev->roff_picb = ICH_REG_OFF_SR;
1206 } else {
1207 ichdev->roff_sr = ICH_REG_OFF_SR;
1208 ichdev->roff_picb = ICH_REG_OFF_PICB;
1209 }
1210 if (device_type == DEVICE_ALI)
1211 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1212 }
1213 /* SIS7013 handles the pcm data in bytes, others are in words */
1214 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1215
1216 /* allocate buffer descriptor lists */
1217 /* the start of each lists must be aligned to 8 bytes */
1218 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1219 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
1220 &chip->bdbars) < 0) {
a6e8509f 1221 snd_intel8x0m_free(chip);
1da177e4
LT		 1222 return -ENOMEM;
1223 }
1224 /* tables must be aligned to 8 bytes here, but the kernel pages
1225 are much bigger, so we don't care (on i386) */
1226 int_sta_masks = 0;
1227 for (i = 0; i < chip->bdbars_count; i++) {
1228 ichdev = &chip->ichd[i];
1229 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1230 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1231 int_sta_masks |= ichdev->int_sta_mask;
1232 }
1233 chip->int_sta_reg = ICH_REG_GLOB_STA;
1234 chip->int_sta_mask = int_sta_masks;
1235
a6e8509f
PB		 1236 if ((err = snd_intel8x0m_chip_init(chip, 1)) < 0) {
1237 snd_intel8x0m_free(chip);
1da177e4
LT		 1238 return err;
1239 }
1240
1da177e4 1241 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
a6e8509f 1242 snd_intel8x0m_free(chip);
1da177e4
LT		 1243 return err;
1244 }
1245
1246 snd_card_set_dev(card, &pci->dev);
1247
966a7f0d 1248 *r_intel8x0m = chip;
1da177e4
LT		 1249 return 0;
1250}
1251
1252static struct shortname_table {
1253 unsigned int id;
1254 const char *s;
e23e7a14 1255} shortnames[] = {
8cdfd251
TI		 1256 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
1257 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
1da177e4
LT		 1258 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1259 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
8cdfd251
TI		 1260 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
1261 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
1262 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
1263 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
1264 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
1da177e4
LT		 1265 { 0x7446, "AMD AMD768" },
1266 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
8cdfd251 1267 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
1da177e4
LT		 1268 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1269 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1270 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
df1fe132 1271 { 0x746e, "AMD AMD8111" },
1da177e4
LT		 1272#if 0
1273 { 0x5455, "ALi M5455" },
1da177e4
LT		 1274#endif
1275 { 0 },
1276};
1277
e23e7a14
BP		 1278static int snd_intel8x0m_probe(struct pci_dev *pci,
1279 const struct pci_device_id *pci_id)
1da177e4 1280{
6b75a9d8
TI		 1281 struct snd_card *card;
1282 struct intel8x0m *chip;
1da177e4
LT		 1283 int err;
1284 struct shortname_table *name;
1285
e58de7ba
TI		 1286 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
1287 if (err < 0)
1288 return err;
1da177e4
LT		 1289
1290 strcpy(card->driver, "ICH-MODEM");
1291 strcpy(card->shortname, "Intel ICH");
1292 for (name = shortnames; name->id; name++) {
1293 if (pci->device == name->id) {
1294 strcpy(card->shortname, name->s);
1295 break;
1296 }
1297 }
1298 strcat(card->shortname," Modem");
1299
1300 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1301 snd_card_free(card);
1302 return err;
1303 }
5809c6c4 1304 card->private_data = chip;
1da177e4 1305
a6e8509f 1306 if ((err = snd_intel8x0m_mixer(chip, ac97_clock)) < 0) {
1da177e4
LT		 1307 snd_card_free(card);
1308 return err;
1309 }
a6e8509f 1310 if ((err = snd_intel8x0m_pcm(chip)) < 0) {
1da177e4
LT		 1311 snd_card_free(card);
1312 return err;
1313 }
1314
1315 snd_intel8x0m_proc_init(chip);
1316
3388c37e
TI		 1317 sprintf(card->longname, "%s at irq %i",
1318 card->shortname, chip->irq);
1da177e4
LT		 1319
1320 if ((err = snd_card_register(card)) < 0) {
1321 snd_card_free(card);
1322 return err;
1323 }
1324 pci_set_drvdata(pci, card);
1da177e4
LT		 1325 return 0;
1326}
1327
e23e7a14 1328static void snd_intel8x0m_remove(struct pci_dev *pci)
1da177e4
LT		 1329{
1330 snd_card_free(pci_get_drvdata(pci));
1331 pci_set_drvdata(pci, NULL);
1332}
1333
e9f66d9b 1334static struct pci_driver intel8x0m_driver = {
3733e424 1335 .name = KBUILD_MODNAME,
1da177e4
LT		 1336 .id_table = snd_intel8x0m_ids,
1337 .probe = snd_intel8x0m_probe,
e23e7a14 1338 .remove = snd_intel8x0m_remove,
68cb2b55
TI		 1339 .driver = {
1340 .pm = INTEL8X0M_PM_OPS,
1341 },
1da177e4
LT		 1342};
1343
e9f66d9b 1344module_pci_driver(intel8x0m_driver);
kernel source for telekom puls (alcatel/mediatek)