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[ALSA] Add dB scale information to cs4281 driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / fm801.c
CommitLineData
1da177e4
LT		 1/*
2 * The driver for the ForteMedia FM801 based soundcards
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
4 *
e0a5d82a 5 * Support FM only card by Andy Shevchenko <andy@smile.org.ua>
1da177e4
LT		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#include <sound/driver.h>
24#include <linux/delay.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/moduleparam.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/ac97_codec.h>
33#include <sound/mpu401.h>
34#include <sound/opl3.h>
35#include <sound/initval.h>
36
37#include <asm/io.h>
38
efce4bb9 39#ifdef CONFIG_SND_FM801_TEA575X_BOOL
1da177e4
LT		 40#include <sound/tea575x-tuner.h>
41#define TEA575X_RADIO 1
42#endif
43
44MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
45MODULE_DESCRIPTION("ForteMedia FM801");
46MODULE_LICENSE("GPL");
47MODULE_SUPPORTED_DEVICE("{{ForteMedia,FM801},"
48 "{Genius,SoundMaker Live 5.1}}");
49
50static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
51static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
52static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
53/*
54 * Enable TEA575x tuner
55 * 1 = MediaForte 256-PCS
56 * 2 = MediaForte 256-PCPR
57 * 3 = MediaForte 64-PCR
e0a5d82a 58 * 16 = setup tuner only (this is additional bit), i.e. SF-64-PCR FM card
1da177e4
LT		 59 * High 16-bits are video (radio) device number + 1
60 */
6581f4e7 61static int tea575x_tuner[SNDRV_CARDS];
1da177e4
LT		 62
63module_param_array(index, int, NULL, 0444);
64MODULE_PARM_DESC(index, "Index value for the FM801 soundcard.");
65module_param_array(id, charp, NULL, 0444);
66MODULE_PARM_DESC(id, "ID string for the FM801 soundcard.");
67module_param_array(enable, bool, NULL, 0444);
68MODULE_PARM_DESC(enable, "Enable FM801 soundcard.");
69module_param_array(tea575x_tuner, int, NULL, 0444);
70MODULE_PARM_DESC(tea575x_tuner, "Enable TEA575x tuner.");
71
72/*
73 * Direct registers
74 */
75
76#define FM801_REG(chip, reg) (chip->port + FM801_##reg)
77
78#define FM801_PCM_VOL 0x00 /* PCM Output Volume */
79#define FM801_FM_VOL 0x02 /* FM Output Volume */
80#define FM801_I2S_VOL 0x04 /* I2S Volume */
81#define FM801_REC_SRC 0x06 /* Record Source */
82#define FM801_PLY_CTRL 0x08 /* Playback Control */
83#define FM801_PLY_COUNT 0x0a /* Playback Count */
84#define FM801_PLY_BUF1 0x0c /* Playback Bufer I */
85#define FM801_PLY_BUF2 0x10 /* Playback Buffer II */
86#define FM801_CAP_CTRL 0x14 /* Capture Control */
87#define FM801_CAP_COUNT 0x16 /* Capture Count */
88#define FM801_CAP_BUF1 0x18 /* Capture Buffer I */
89#define FM801_CAP_BUF2 0x1c /* Capture Buffer II */
90#define FM801_CODEC_CTRL 0x22 /* Codec Control */
91#define FM801_I2S_MODE 0x24 /* I2S Mode Control */
92#define FM801_VOLUME 0x26 /* Volume Up/Down/Mute Status */
93#define FM801_I2C_CTRL 0x29 /* I2C Control */
94#define FM801_AC97_CMD 0x2a /* AC'97 Command */
95#define FM801_AC97_DATA 0x2c /* AC'97 Data */
96#define FM801_MPU401_DATA 0x30 /* MPU401 Data */
97#define FM801_MPU401_CMD 0x31 /* MPU401 Command */
98#define FM801_GPIO_CTRL 0x52 /* General Purpose I/O Control */
99#define FM801_GEN_CTRL 0x54 /* General Control */
100#define FM801_IRQ_MASK 0x56 /* Interrupt Mask */
101#define FM801_IRQ_STATUS 0x5a /* Interrupt Status */
102#define FM801_OPL3_BANK0 0x68 /* OPL3 Status Read / Bank 0 Write */
103#define FM801_OPL3_DATA0 0x69 /* OPL3 Data 0 Write */
104#define FM801_OPL3_BANK1 0x6a /* OPL3 Bank 1 Write */
105#define FM801_OPL3_DATA1 0x6b /* OPL3 Bank 1 Write */
106#define FM801_POWERDOWN 0x70 /* Blocks Power Down Control */
107
b1e9ed26
TI		 108/* codec access */
109#define FM801_AC97_READ (1<<7) /* read=1, write=0 */
110#define FM801_AC97_VALID (1<<8) /* port valid=1 */
111#define FM801_AC97_BUSY (1<<9) /* busy=1 */
112#define FM801_AC97_ADDR_SHIFT 10 /* codec id (2bit) */
1da177e4
LT		 113
114/* playback and record control register bits */
115#define FM801_BUF1_LAST (1<<1)
116#define FM801_BUF2_LAST (1<<2)
117#define FM801_START (1<<5)
118#define FM801_PAUSE (1<<6)
119#define FM801_IMMED_STOP (1<<7)
120#define FM801_RATE_SHIFT 8
121#define FM801_RATE_MASK (15 << FM801_RATE_SHIFT)
122#define FM801_CHANNELS_4 (1<<12) /* playback only */
123#define FM801_CHANNELS_6 (2<<12) /* playback only */
124#define FM801_CHANNELS_6MS (3<<12) /* playback only */
125#define FM801_CHANNELS_MASK (3<<12)
126#define FM801_16BIT (1<<14)
127#define FM801_STEREO (1<<15)
128
129/* IRQ status bits */
130#define FM801_IRQ_PLAYBACK (1<<8)
131#define FM801_IRQ_CAPTURE (1<<9)
132#define FM801_IRQ_VOLUME (1<<14)
133#define FM801_IRQ_MPU (1<<15)
134
135/* GPIO control register */
136#define FM801_GPIO_GP0 (1<<0) /* read/write */
137#define FM801_GPIO_GP1 (1<<1)
138#define FM801_GPIO_GP2 (1<<2)
139#define FM801_GPIO_GP3 (1<<3)
140#define FM801_GPIO_GP(x) (1<<(0+(x)))
141#define FM801_GPIO_GD0 (1<<8) /* directions: 1 = input, 0 = output*/
142#define FM801_GPIO_GD1 (1<<9)
143#define FM801_GPIO_GD2 (1<<10)
144#define FM801_GPIO_GD3 (1<<11)
145#define FM801_GPIO_GD(x) (1<<(8+(x)))
146#define FM801_GPIO_GS0 (1<<12) /* function select: */
147#define FM801_GPIO_GS1 (1<<13) /* 1 = GPIO */
148#define FM801_GPIO_GS2 (1<<14) /* 0 = other (S/PDIF, VOL) */
149#define FM801_GPIO_GS3 (1<<15)
150#define FM801_GPIO_GS(x) (1<<(12+(x)))
151
152/*
153
154 */
155
a5f22156 156struct fm801 {
1da177e4
LT		 157 int irq;
158
159 unsigned long port; /* I/O port number */
160 unsigned int multichannel: 1, /* multichannel support */
161 secondary: 1; /* secondary codec */
162 unsigned char secondary_addr; /* address of the secondary codec */
6bbe13ec 163 unsigned int tea575x_tuner; /* tuner flags */
1da177e4
LT		 164
165 unsigned short ply_ctrl; /* playback control */
166 unsigned short cap_ctrl; /* capture control */
167
168 unsigned long ply_buffer;
169 unsigned int ply_buf;
170 unsigned int ply_count;
171 unsigned int ply_size;
172 unsigned int ply_pos;
173
174 unsigned long cap_buffer;
175 unsigned int cap_buf;
176 unsigned int cap_count;
177 unsigned int cap_size;
178 unsigned int cap_pos;
179
a5f22156
TI		 180 struct snd_ac97_bus *ac97_bus;
181 struct snd_ac97 *ac97;
182 struct snd_ac97 *ac97_sec;
1da177e4
LT		 183
184 struct pci_dev *pci;
a5f22156
TI		 185 struct snd_card *card;
186 struct snd_pcm *pcm;
187 struct snd_rawmidi *rmidi;
188 struct snd_pcm_substream *playback_substream;
189 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 190 unsigned int p_dma_size;
191 unsigned int c_dma_size;
192
193 spinlock_t reg_lock;
a5f22156 194 struct snd_info_entry *proc_entry;
1da177e4
LT		 195
196#ifdef TEA575X_RADIO
a5f22156 197 struct snd_tea575x tea;
1da177e4 198#endif
b1e9ed26
TI		 199
200#ifdef CONFIG_PM
201 u16 saved_regs[0x20];
202#endif
1da177e4
LT		 203};
204
f40b6890 205static struct pci_device_id snd_fm801_ids[] = {
1da177e4 206 { 0x1319, 0x0801, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* FM801 */
26be8659 207 { 0x5213, 0x0510, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* Gallant Odyssey Sound 4 */
1da177e4
LT		 208 { 0, }
209};
210
211MODULE_DEVICE_TABLE(pci, snd_fm801_ids);
212
213/*
214 * common I/O routines
215 */
216
a5f22156 217static int snd_fm801_update_bits(struct fm801 *chip, unsigned short reg,
1da177e4
LT		 218 unsigned short mask, unsigned short value)
219{
220 int change;
221 unsigned long flags;
222 unsigned short old, new;
223
224 spin_lock_irqsave(&chip->reg_lock, flags);
225 old = inw(chip->port + reg);
226 new = (old & ~mask) | value;
227 change = old != new;
228 if (change)
229 outw(new, chip->port + reg);
230 spin_unlock_irqrestore(&chip->reg_lock, flags);
231 return change;
232}
233
a5f22156 234static void snd_fm801_codec_write(struct snd_ac97 *ac97,
1da177e4
LT		 235 unsigned short reg,
236 unsigned short val)
237{
a5f22156 238 struct fm801 *chip = ac97->private_data;
1da177e4
LT		 239 int idx;
240
241 /*
242 * Wait until the codec interface is not ready..
243 */
244 for (idx = 0; idx < 100; idx++) {
b1e9ed26 245 if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
1da177e4
LT		 246 goto ok1;
247 udelay(10);
248 }
99b359ba 249 snd_printk(KERN_ERR "AC'97 interface is busy (1)\n");
1da177e4
LT		 250 return;
251
252 ok1:
253 /* write data and address */
254 outw(val, FM801_REG(chip, AC97_DATA));
255 outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT), FM801_REG(chip, AC97_CMD));
256 /*
257 * Wait until the write command is not completed..
258 */
259 for (idx = 0; idx < 1000; idx++) {
b1e9ed26 260 if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
1da177e4
LT		 261 return;
262 udelay(10);
263 }
99b359ba 264 snd_printk(KERN_ERR "AC'97 interface #%d is busy (2)\n", ac97->num);
1da177e4
LT		 265}
266
a5f22156 267static unsigned short snd_fm801_codec_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4 268{
a5f22156 269 struct fm801 *chip = ac97->private_data;
1da177e4
LT		 270 int idx;
271
272 /*
273 * Wait until the codec interface is not ready..
274 */
275 for (idx = 0; idx < 100; idx++) {
b1e9ed26 276 if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
1da177e4
LT		 277 goto ok1;
278 udelay(10);
279 }
99b359ba 280 snd_printk(KERN_ERR "AC'97 interface is busy (1)\n");
1da177e4
LT		 281 return 0;
282
283 ok1:
284 /* read command */
b1e9ed26
TI		 285 outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT) | FM801_AC97_READ,
286 FM801_REG(chip, AC97_CMD));
1da177e4 287 for (idx = 0; idx < 100; idx++) {
b1e9ed26 288 if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
1da177e4
LT		 289 goto ok2;
290 udelay(10);
291 }
99b359ba 292 snd_printk(KERN_ERR "AC'97 interface #%d is busy (2)\n", ac97->num);
1da177e4
LT		 293 return 0;
294
295 ok2:
296 for (idx = 0; idx < 1000; idx++) {
b1e9ed26 297 if (inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_VALID)
1da177e4
LT		 298 goto ok3;
299 udelay(10);
300 }
99b359ba 301 snd_printk(KERN_ERR "AC'97 interface #%d is not valid (2)\n", ac97->num);
1da177e4
LT		 302 return 0;
303
304 ok3:
305 return inw(FM801_REG(chip, AC97_DATA));
306}
307
308static unsigned int rates[] = {
309 5500, 8000, 9600, 11025,
310 16000, 19200, 22050, 32000,
311 38400, 44100, 48000
312};
313
a5f22156 314static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1da177e4
LT		 315 .count = ARRAY_SIZE(rates),
316 .list = rates,
317 .mask = 0,
318};
319
320static unsigned int channels[] = {
321 2, 4, 6
322};
323
a5f22156 324static struct snd_pcm_hw_constraint_list hw_constraints_channels = {
5e4968e2 325 .count = ARRAY_SIZE(channels),
1da177e4
LT		 326 .list = channels,
327 .mask = 0,
328};
329
330/*
331 * Sample rate routines
332 */
333
334static unsigned short snd_fm801_rate_bits(unsigned int rate)
335{
336 unsigned int idx;
337
338 for (idx = 0; idx < ARRAY_SIZE(rates); idx++)
339 if (rates[idx] == rate)
340 return idx;
341 snd_BUG();
342 return ARRAY_SIZE(rates) - 1;
343}
344
345/*
346 * PCM part
347 */
348
a5f22156 349static int snd_fm801_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 350 int cmd)
351{
a5f22156 352 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 353
354 spin_lock(&chip->reg_lock);
355 switch (cmd) {
356 case SNDRV_PCM_TRIGGER_START:
357 chip->ply_ctrl &= ~(FM801_BUF1_LAST |
358 FM801_BUF2_LAST |
359 FM801_PAUSE);
360 chip->ply_ctrl |= FM801_START |
361 FM801_IMMED_STOP;
362 break;
363 case SNDRV_PCM_TRIGGER_STOP:
364 chip->ply_ctrl &= ~(FM801_START | FM801_PAUSE);
365 break;
366 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b1e9ed26 367 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 368 chip->ply_ctrl |= FM801_PAUSE;
369 break;
370 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b1e9ed26 371 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4
LT		 372 chip->ply_ctrl &= ~FM801_PAUSE;
373 break;
374 default:
375 spin_unlock(&chip->reg_lock);
376 snd_BUG();
377 return -EINVAL;
378 }
379 outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
380 spin_unlock(&chip->reg_lock);
381 return 0;
382}
383
a5f22156 384static int snd_fm801_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 385 int cmd)
386{
a5f22156 387 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 388
389 spin_lock(&chip->reg_lock);
390 switch (cmd) {
391 case SNDRV_PCM_TRIGGER_START:
392 chip->cap_ctrl &= ~(FM801_BUF1_LAST |
393 FM801_BUF2_LAST |
394 FM801_PAUSE);
395 chip->cap_ctrl |= FM801_START |
396 FM801_IMMED_STOP;
397 break;
398 case SNDRV_PCM_TRIGGER_STOP:
399 chip->cap_ctrl &= ~(FM801_START | FM801_PAUSE);
400 break;
401 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b1e9ed26 402 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 403 chip->cap_ctrl |= FM801_PAUSE;
404 break;
405 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b1e9ed26 406 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4
LT		 407 chip->cap_ctrl &= ~FM801_PAUSE;
408 break;
409 default:
410 spin_unlock(&chip->reg_lock);
411 snd_BUG();
412 return -EINVAL;
413 }
414 outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
415 spin_unlock(&chip->reg_lock);
416 return 0;
417}
418
a5f22156
TI		 419static int snd_fm801_hw_params(struct snd_pcm_substream *substream,
420 struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 421{
422 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
423}
424
a5f22156 425static int snd_fm801_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 426{
427 return snd_pcm_lib_free_pages(substream);
428}
429
a5f22156 430static int snd_fm801_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 431{
a5f22156
TI		 432 struct fm801 *chip = snd_pcm_substream_chip(substream);
433 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 434
435 chip->ply_size = snd_pcm_lib_buffer_bytes(substream);
436 chip->ply_count = snd_pcm_lib_period_bytes(substream);
437 spin_lock_irq(&chip->reg_lock);
438 chip->ply_ctrl &= ~(FM801_START | FM801_16BIT |
439 FM801_STEREO | FM801_RATE_MASK |
440 FM801_CHANNELS_MASK);
441 if (snd_pcm_format_width(runtime->format) == 16)
442 chip->ply_ctrl |= FM801_16BIT;
443 if (runtime->channels > 1) {
444 chip->ply_ctrl |= FM801_STEREO;
445 if (runtime->channels == 4)
446 chip->ply_ctrl |= FM801_CHANNELS_4;
447 else if (runtime->channels == 6)
448 chip->ply_ctrl |= FM801_CHANNELS_6;
449 }
450 chip->ply_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
451 chip->ply_buf = 0;
452 outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
453 outw(chip->ply_count - 1, FM801_REG(chip, PLY_COUNT));
454 chip->ply_buffer = runtime->dma_addr;
455 chip->ply_pos = 0;
456 outl(chip->ply_buffer, FM801_REG(chip, PLY_BUF1));
457 outl(chip->ply_buffer + (chip->ply_count % chip->ply_size), FM801_REG(chip, PLY_BUF2));
458 spin_unlock_irq(&chip->reg_lock);
459 return 0;
460}
461
a5f22156 462static int snd_fm801_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 463{
a5f22156
TI		 464 struct fm801 *chip = snd_pcm_substream_chip(substream);
465 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 466
467 chip->cap_size = snd_pcm_lib_buffer_bytes(substream);
468 chip->cap_count = snd_pcm_lib_period_bytes(substream);
469 spin_lock_irq(&chip->reg_lock);
470 chip->cap_ctrl &= ~(FM801_START | FM801_16BIT |
471 FM801_STEREO | FM801_RATE_MASK);
472 if (snd_pcm_format_width(runtime->format) == 16)
473 chip->cap_ctrl |= FM801_16BIT;
474 if (runtime->channels > 1)
475 chip->cap_ctrl |= FM801_STEREO;
476 chip->cap_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
477 chip->cap_buf = 0;
478 outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
479 outw(chip->cap_count - 1, FM801_REG(chip, CAP_COUNT));
480 chip->cap_buffer = runtime->dma_addr;
481 chip->cap_pos = 0;
482 outl(chip->cap_buffer, FM801_REG(chip, CAP_BUF1));
483 outl(chip->cap_buffer + (chip->cap_count % chip->cap_size), FM801_REG(chip, CAP_BUF2));
484 spin_unlock_irq(&chip->reg_lock);
485 return 0;
486}
487
a5f22156 488static snd_pcm_uframes_t snd_fm801_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 489{
a5f22156 490 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 491 size_t ptr;
492
493 if (!(chip->ply_ctrl & FM801_START))
494 return 0;
495 spin_lock(&chip->reg_lock);
496 ptr = chip->ply_pos + (chip->ply_count - 1) - inw(FM801_REG(chip, PLY_COUNT));
497 if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_PLAYBACK) {
498 ptr += chip->ply_count;
499 ptr %= chip->ply_size;
500 }
501 spin_unlock(&chip->reg_lock);
502 return bytes_to_frames(substream->runtime, ptr);
503}
504
a5f22156 505static snd_pcm_uframes_t snd_fm801_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 506{
a5f22156 507 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 508 size_t ptr;
509
510 if (!(chip->cap_ctrl & FM801_START))
511 return 0;
512 spin_lock(&chip->reg_lock);
513 ptr = chip->cap_pos + (chip->cap_count - 1) - inw(FM801_REG(chip, CAP_COUNT));
514 if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_CAPTURE) {
515 ptr += chip->cap_count;
516 ptr %= chip->cap_size;
517 }
518 spin_unlock(&chip->reg_lock);
519 return bytes_to_frames(substream->runtime, ptr);
520}
521
522static irqreturn_t snd_fm801_interrupt(int irq, void *dev_id, struct pt_regs *regs)
523{
a5f22156 524 struct fm801 *chip = dev_id;
1da177e4
LT		 525 unsigned short status;
526 unsigned int tmp;
527
528 status = inw(FM801_REG(chip, IRQ_STATUS));
529 status &= FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU|FM801_IRQ_VOLUME;
530 if (! status)
531 return IRQ_NONE;
532 /* ack first */
533 outw(status, FM801_REG(chip, IRQ_STATUS));
534 if (chip->pcm && (status & FM801_IRQ_PLAYBACK) && chip->playback_substream) {
535 spin_lock(&chip->reg_lock);
536 chip->ply_buf++;
537 chip->ply_pos += chip->ply_count;
538 chip->ply_pos %= chip->ply_size;
539 tmp = chip->ply_pos + chip->ply_count;
540 tmp %= chip->ply_size;
541 outl(chip->ply_buffer + tmp,
542 (chip->ply_buf & 1) ?
543 FM801_REG(chip, PLY_BUF1) :
544 FM801_REG(chip, PLY_BUF2));
545 spin_unlock(&chip->reg_lock);
546 snd_pcm_period_elapsed(chip->playback_substream);
547 }
548 if (chip->pcm && (status & FM801_IRQ_CAPTURE) && chip->capture_substream) {
549 spin_lock(&chip->reg_lock);
550 chip->cap_buf++;
551 chip->cap_pos += chip->cap_count;
552 chip->cap_pos %= chip->cap_size;
553 tmp = chip->cap_pos + chip->cap_count;
554 tmp %= chip->cap_size;
555 outl(chip->cap_buffer + tmp,
556 (chip->cap_buf & 1) ?
557 FM801_REG(chip, CAP_BUF1) :
558 FM801_REG(chip, CAP_BUF2));
559 spin_unlock(&chip->reg_lock);
560 snd_pcm_period_elapsed(chip->capture_substream);
561 }
562 if (chip->rmidi && (status & FM801_IRQ_MPU))
563 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
564 if (status & FM801_IRQ_VOLUME)
565 ;/* TODO */
566
567 return IRQ_HANDLED;
568}
569
a5f22156 570static struct snd_pcm_hardware snd_fm801_playback =
1da177e4
LT		 571{
572 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
573 SNDRV_PCM_INFO_BLOCK_TRANSFER |
b1e9ed26 574 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 575 SNDRV_PCM_INFO_MMAP_VALID),
576 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
577 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
578 .rate_min = 5500,
579 .rate_max = 48000,
580 .channels_min = 1,
581 .channels_max = 2,
582 .buffer_bytes_max = (128*1024),
583 .period_bytes_min = 64,
584 .period_bytes_max = (128*1024),
585 .periods_min = 1,
586 .periods_max = 1024,
587 .fifo_size = 0,
588};
589
a5f22156 590static struct snd_pcm_hardware snd_fm801_capture =
1da177e4
LT		 591{
592 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
593 SNDRV_PCM_INFO_BLOCK_TRANSFER |
b1e9ed26 594 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 595 SNDRV_PCM_INFO_MMAP_VALID),
596 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
597 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
598 .rate_min = 5500,
599 .rate_max = 48000,
600 .channels_min = 1,
601 .channels_max = 2,
602 .buffer_bytes_max = (128*1024),
603 .period_bytes_min = 64,
604 .period_bytes_max = (128*1024),
605 .periods_min = 1,
606 .periods_max = 1024,
607 .fifo_size = 0,
608};
609
a5f22156 610static int snd_fm801_playback_open(struct snd_pcm_substream *substream)
1da177e4 611{
a5f22156
TI		 612 struct fm801 *chip = snd_pcm_substream_chip(substream);
613 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 614 int err;
615
616 chip->playback_substream = substream;
617 runtime->hw = snd_fm801_playback;
a5f22156
TI		 618 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
619 &hw_constraints_rates);
1da177e4
LT		 620 if (chip->multichannel) {
621 runtime->hw.channels_max = 6;
a5f22156
TI		 622 snd_pcm_hw_constraint_list(runtime, 0,
623 SNDRV_PCM_HW_PARAM_CHANNELS,
624 &hw_constraints_channels);
1da177e4
LT		 625 }
626 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
627 return err;
628 return 0;
629}
630
a5f22156 631static int snd_fm801_capture_open(struct snd_pcm_substream *substream)
1da177e4 632{
a5f22156
TI		 633 struct fm801 *chip = snd_pcm_substream_chip(substream);
634 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 635 int err;
636
637 chip->capture_substream = substream;
638 runtime->hw = snd_fm801_capture;
a5f22156
TI		 639 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
640 &hw_constraints_rates);
1da177e4
LT		 641 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
642 return err;
643 return 0;
644}
645
a5f22156 646static int snd_fm801_playback_close(struct snd_pcm_substream *substream)
1da177e4 647{
a5f22156 648 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 649
650 chip->playback_substream = NULL;
651 return 0;
652}
653
a5f22156 654static int snd_fm801_capture_close(struct snd_pcm_substream *substream)
1da177e4 655{
a5f22156 656 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 657
658 chip->capture_substream = NULL;
659 return 0;
660}
661
a5f22156 662static struct snd_pcm_ops snd_fm801_playback_ops = {
1da177e4
LT		 663 .open = snd_fm801_playback_open,
664 .close = snd_fm801_playback_close,
665 .ioctl = snd_pcm_lib_ioctl,
666 .hw_params = snd_fm801_hw_params,
667 .hw_free = snd_fm801_hw_free,
668 .prepare = snd_fm801_playback_prepare,
669 .trigger = snd_fm801_playback_trigger,
670 .pointer = snd_fm801_playback_pointer,
671};
672
a5f22156 673static struct snd_pcm_ops snd_fm801_capture_ops = {
1da177e4
LT		 674 .open = snd_fm801_capture_open,
675 .close = snd_fm801_capture_close,
676 .ioctl = snd_pcm_lib_ioctl,
677 .hw_params = snd_fm801_hw_params,
678 .hw_free = snd_fm801_hw_free,
679 .prepare = snd_fm801_capture_prepare,
680 .trigger = snd_fm801_capture_trigger,
681 .pointer = snd_fm801_capture_pointer,
682};
683
a5f22156 684static int __devinit snd_fm801_pcm(struct fm801 *chip, int device, struct snd_pcm ** rpcm)
1da177e4 685{
a5f22156 686 struct snd_pcm *pcm;
1da177e4
LT		 687 int err;
688
689 if (rpcm)
690 *rpcm = NULL;
691 if ((err = snd_pcm_new(chip->card, "FM801", device, 1, 1, &pcm)) < 0)
692 return err;
693
694 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_fm801_playback_ops);
695 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_fm801_capture_ops);
696
697 pcm->private_data = chip;
1da177e4
LT		 698 pcm->info_flags = 0;
699 strcpy(pcm->name, "FM801");
700 chip->pcm = pcm;
701
702 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
703 snd_dma_pci_data(chip->pci),
704 chip->multichannel ? 128*1024 : 64*1024, 128*1024);
705
706 if (rpcm)
707 *rpcm = pcm;
708 return 0;
709}
710
711/*
712 * TEA5757 radio
713 */
714
715#ifdef TEA575X_RADIO
716
717/* 256PCS GPIO numbers */
718#define TEA_256PCS_DATA 1
719#define TEA_256PCS_WRITE_ENABLE 2 /* inverted */
720#define TEA_256PCS_BUS_CLOCK 3
721
a5f22156 722static void snd_fm801_tea575x_256pcs_write(struct snd_tea575x *tea, unsigned int val)
1da177e4 723{
a5f22156 724 struct fm801 *chip = tea->private_data;
1da177e4
LT		 725 unsigned short reg;
726 int i = 25;
727
728 spin_lock_irq(&chip->reg_lock);
729 reg = inw(FM801_REG(chip, GPIO_CTRL));
730 /* use GPIO lines and set write enable bit */
731 reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
732 FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
733 FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK);
734 /* all of lines are in the write direction */
735 /* clear data and clock lines */
736 reg &= ~(FM801_GPIO_GD(TEA_256PCS_DATA) |
737 FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
738 FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
739 FM801_GPIO_GP(TEA_256PCS_DATA) |
740 FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK) |
741 FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE));
742 outw(reg, FM801_REG(chip, GPIO_CTRL));
743 udelay(1);
744
745 while (i--) {
746 if (val & (1 << i))
747 reg |= FM801_GPIO_GP(TEA_256PCS_DATA);
748 else
749 reg &= ~FM801_GPIO_GP(TEA_256PCS_DATA);
750 outw(reg, FM801_REG(chip, GPIO_CTRL));
751 udelay(1);
752 reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
753 outw(reg, FM801_REG(chip, GPIO_CTRL));
754 reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
755 outw(reg, FM801_REG(chip, GPIO_CTRL));
756 udelay(1);
757 }
758
759 /* and reset the write enable bit */
760 reg |= FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE) |
761 FM801_GPIO_GP(TEA_256PCS_DATA);
762 outw(reg, FM801_REG(chip, GPIO_CTRL));
763 spin_unlock_irq(&chip->reg_lock);
764}
765
a5f22156 766static unsigned int snd_fm801_tea575x_256pcs_read(struct snd_tea575x *tea)
1da177e4 767{
a5f22156 768 struct fm801 *chip = tea->private_data;
1da177e4
LT		 769 unsigned short reg;
770 unsigned int val = 0;
771 int i;
772
773 spin_lock_irq(&chip->reg_lock);
774 reg = inw(FM801_REG(chip, GPIO_CTRL));
775 /* use GPIO lines, set data direction to input */
776 reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
777 FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
778 FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK) |
779 FM801_GPIO_GD(TEA_256PCS_DATA) |
780 FM801_GPIO_GP(TEA_256PCS_DATA) |
781 FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE);
782 /* all of lines are in the write direction, except data */
783 /* clear data, write enable and clock lines */
784 reg &= ~(FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
785 FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
786 FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK));
787
788 for (i = 0; i < 24; i++) {
789 reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
790 outw(reg, FM801_REG(chip, GPIO_CTRL));
791 udelay(1);
792 reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
793 outw(reg, FM801_REG(chip, GPIO_CTRL));
794 udelay(1);
795 val <<= 1;
796 if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCS_DATA))
797 val |= 1;
798 }
799
800 spin_unlock_irq(&chip->reg_lock);
801
802 return val;
803}
804
805/* 256PCPR GPIO numbers */
806#define TEA_256PCPR_BUS_CLOCK 0
807#define TEA_256PCPR_DATA 1
808#define TEA_256PCPR_WRITE_ENABLE 2 /* inverted */
809
a5f22156 810static void snd_fm801_tea575x_256pcpr_write(struct snd_tea575x *tea, unsigned int val)
1da177e4 811{
a5f22156 812 struct fm801 *chip = tea->private_data;
1da177e4
LT		 813 unsigned short reg;
814 int i = 25;
815
816 spin_lock_irq(&chip->reg_lock);
817 reg = inw(FM801_REG(chip, GPIO_CTRL));
818 /* use GPIO lines and set write enable bit */
819 reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
820 FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
821 FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK);
822 /* all of lines are in the write direction */
823 /* clear data and clock lines */
824 reg &= ~(FM801_GPIO_GD(TEA_256PCPR_DATA) |
825 FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
826 FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
827 FM801_GPIO_GP(TEA_256PCPR_DATA) |
828 FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK) |
829 FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE));
830 outw(reg, FM801_REG(chip, GPIO_CTRL));
831 udelay(1);
832
833 while (i--) {
834 if (val & (1 << i))
835 reg |= FM801_GPIO_GP(TEA_256PCPR_DATA);
836 else
837 reg &= ~FM801_GPIO_GP(TEA_256PCPR_DATA);
838 outw(reg, FM801_REG(chip, GPIO_CTRL));
839 udelay(1);
840 reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
841 outw(reg, FM801_REG(chip, GPIO_CTRL));
842 reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
843 outw(reg, FM801_REG(chip, GPIO_CTRL));
844 udelay(1);
845 }
846
847 /* and reset the write enable bit */
848 reg |= FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE) |
849 FM801_GPIO_GP(TEA_256PCPR_DATA);
850 outw(reg, FM801_REG(chip, GPIO_CTRL));
851 spin_unlock_irq(&chip->reg_lock);
852}
853
a5f22156 854static unsigned int snd_fm801_tea575x_256pcpr_read(struct snd_tea575x *tea)
1da177e4 855{
a5f22156 856 struct fm801 *chip = tea->private_data;
1da177e4
LT		 857 unsigned short reg;
858 unsigned int val = 0;
859 int i;
860
861 spin_lock_irq(&chip->reg_lock);
862 reg = inw(FM801_REG(chip, GPIO_CTRL));
863 /* use GPIO lines, set data direction to input */
864 reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
865 FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
866 FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK) |
867 FM801_GPIO_GD(TEA_256PCPR_DATA) |
868 FM801_GPIO_GP(TEA_256PCPR_DATA) |
869 FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE);
870 /* all of lines are in the write direction, except data */
871 /* clear data, write enable and clock lines */
872 reg &= ~(FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
873 FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
874 FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK));
875
876 for (i = 0; i < 24; i++) {
877 reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
878 outw(reg, FM801_REG(chip, GPIO_CTRL));
879 udelay(1);
880 reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
881 outw(reg, FM801_REG(chip, GPIO_CTRL));
882 udelay(1);
883 val <<= 1;
884 if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCPR_DATA))
885 val |= 1;
886 }
887
888 spin_unlock_irq(&chip->reg_lock);
889
890 return val;
891}
892
893/* 64PCR GPIO numbers */
894#define TEA_64PCR_BUS_CLOCK 0
895#define TEA_64PCR_WRITE_ENABLE 1 /* inverted */
896#define TEA_64PCR_DATA 2
897
a5f22156 898static void snd_fm801_tea575x_64pcr_write(struct snd_tea575x *tea, unsigned int val)
1da177e4 899{
a5f22156 900 struct fm801 *chip = tea->private_data;
1da177e4
LT		 901 unsigned short reg;
902 int i = 25;
903
904 spin_lock_irq(&chip->reg_lock);
905 reg = inw(FM801_REG(chip, GPIO_CTRL));
906 /* use GPIO lines and set write enable bit */
907 reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
908 FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
909 FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK);
910 /* all of lines are in the write direction */
911 /* clear data and clock lines */
912 reg &= ~(FM801_GPIO_GD(TEA_64PCR_DATA) |
913 FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
914 FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
915 FM801_GPIO_GP(TEA_64PCR_DATA) |
916 FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK) |
917 FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE));
918 outw(reg, FM801_REG(chip, GPIO_CTRL));
919 udelay(1);
920
921 while (i--) {
922 if (val & (1 << i))
923 reg |= FM801_GPIO_GP(TEA_64PCR_DATA);
924 else
925 reg &= ~FM801_GPIO_GP(TEA_64PCR_DATA);
926 outw(reg, FM801_REG(chip, GPIO_CTRL));
927 udelay(1);
928 reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
929 outw(reg, FM801_REG(chip, GPIO_CTRL));
930 reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
931 outw(reg, FM801_REG(chip, GPIO_CTRL));
932 udelay(1);
933 }
934
935 /* and reset the write enable bit */
936 reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE) |
937 FM801_GPIO_GP(TEA_64PCR_DATA);
938 outw(reg, FM801_REG(chip, GPIO_CTRL));
939 spin_unlock_irq(&chip->reg_lock);
940}
941
a5f22156 942static unsigned int snd_fm801_tea575x_64pcr_read(struct snd_tea575x *tea)
1da177e4 943{
a5f22156 944 struct fm801 *chip = tea->private_data;
1da177e4
LT		 945 unsigned short reg;
946 unsigned int val = 0;
947 int i;
948
949 spin_lock_irq(&chip->reg_lock);
950 reg = inw(FM801_REG(chip, GPIO_CTRL));
951 /* use GPIO lines, set data direction to input */
952 reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
953 FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
954 FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK) |
955 FM801_GPIO_GD(TEA_64PCR_DATA) |
956 FM801_GPIO_GP(TEA_64PCR_DATA) |
957 FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
958 /* all of lines are in the write direction, except data */
959 /* clear data, write enable and clock lines */
960 reg &= ~(FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
961 FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
962 FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK));
963
964 for (i = 0; i < 24; i++) {
965 reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
966 outw(reg, FM801_REG(chip, GPIO_CTRL));
967 udelay(1);
968 reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
969 outw(reg, FM801_REG(chip, GPIO_CTRL));
970 udelay(1);
971 val <<= 1;
972 if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_64PCR_DATA))
973 val |= 1;
974 }
975
976 spin_unlock_irq(&chip->reg_lock);
977
978 return val;
979}
980
981static struct snd_tea575x_ops snd_fm801_tea_ops[3] = {
982 {
983 /* 1 = MediaForte 256-PCS */
984 .write = snd_fm801_tea575x_256pcs_write,
985 .read = snd_fm801_tea575x_256pcs_read,
986 },
987 {
988 /* 2 = MediaForte 256-PCPR */
989 .write = snd_fm801_tea575x_256pcpr_write,
990 .read = snd_fm801_tea575x_256pcpr_read,
991 },
992 {
993 /* 3 = MediaForte 64-PCR */
994 .write = snd_fm801_tea575x_64pcr_write,
995 .read = snd_fm801_tea575x_64pcr_read,
996 }
997};
998#endif
999
1000/*
1001 * Mixer routines
1002 */
1003
1004#define FM801_SINGLE(xname, reg, shift, mask, invert) \
1005{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_single, \
1006 .get = snd_fm801_get_single, .put = snd_fm801_put_single, \
1007 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
1008
a5f22156
TI		 1009static int snd_fm801_info_single(struct snd_kcontrol *kcontrol,
1010 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1011{
1012 int mask = (kcontrol->private_value >> 16) & 0xff;
1013
1014 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1015 uinfo->count = 1;
1016 uinfo->value.integer.min = 0;
1017 uinfo->value.integer.max = mask;
1018 return 0;
1019}
1020
a5f22156
TI		 1021static int snd_fm801_get_single(struct snd_kcontrol *kcontrol,
1022 struct snd_ctl_elem_value *ucontrol)
1da177e4 1023{
a5f22156 1024 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1025 int reg = kcontrol->private_value & 0xff;
1026 int shift = (kcontrol->private_value >> 8) & 0xff;
1027 int mask = (kcontrol->private_value >> 16) & 0xff;
1028 int invert = (kcontrol->private_value >> 24) & 0xff;
1029
1030 ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift) & mask;
1031 if (invert)
1032 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1033 return 0;
1034}
1035
a5f22156
TI		 1036static int snd_fm801_put_single(struct snd_kcontrol *kcontrol,
1037 struct snd_ctl_elem_value *ucontrol)
1da177e4 1038{
a5f22156 1039 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1040 int reg = kcontrol->private_value & 0xff;
1041 int shift = (kcontrol->private_value >> 8) & 0xff;
1042 int mask = (kcontrol->private_value >> 16) & 0xff;
1043 int invert = (kcontrol->private_value >> 24) & 0xff;
1044 unsigned short val;
1045
1046 val = (ucontrol->value.integer.value[0] & mask);
1047 if (invert)
1048 val = mask - val;
1049 return snd_fm801_update_bits(chip, reg, mask << shift, val << shift);
1050}
1051
1052#define FM801_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \
1053{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_double, \
1054 .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
1055 .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) }
1056
a5f22156
TI		 1057static int snd_fm801_info_double(struct snd_kcontrol *kcontrol,
1058 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1059{
1060 int mask = (kcontrol->private_value >> 16) & 0xff;
1061
1062 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1063 uinfo->count = 2;
1064 uinfo->value.integer.min = 0;
1065 uinfo->value.integer.max = mask;
1066 return 0;
1067}
1068
a5f22156
TI		 1069static int snd_fm801_get_double(struct snd_kcontrol *kcontrol,
1070 struct snd_ctl_elem_value *ucontrol)
1da177e4 1071{
a5f22156 1072 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1073 int reg = kcontrol->private_value & 0xff;
1074 int shift_left = (kcontrol->private_value >> 8) & 0x0f;
1075 int shift_right = (kcontrol->private_value >> 12) & 0x0f;
1076 int mask = (kcontrol->private_value >> 16) & 0xff;
1077 int invert = (kcontrol->private_value >> 24) & 0xff;
1078
1079 spin_lock_irq(&chip->reg_lock);
1080 ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift_left) & mask;
1081 ucontrol->value.integer.value[1] = (inw(chip->port + reg) >> shift_right) & mask;
1082 spin_unlock_irq(&chip->reg_lock);
1083 if (invert) {
1084 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1085 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
1086 }
1087 return 0;
1088}
1089
a5f22156
TI		 1090static int snd_fm801_put_double(struct snd_kcontrol *kcontrol,
1091 struct snd_ctl_elem_value *ucontrol)
1da177e4 1092{
a5f22156 1093 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1094 int reg = kcontrol->private_value & 0xff;
1095 int shift_left = (kcontrol->private_value >> 8) & 0x0f;
1096 int shift_right = (kcontrol->private_value >> 12) & 0x0f;
1097 int mask = (kcontrol->private_value >> 16) & 0xff;
1098 int invert = (kcontrol->private_value >> 24) & 0xff;
1099 unsigned short val1, val2;
1100
1101 val1 = ucontrol->value.integer.value[0] & mask;
1102 val2 = ucontrol->value.integer.value[1] & mask;
1103 if (invert) {
1104 val1 = mask - val1;
1105 val2 = mask - val2;
1106 }
1107 return snd_fm801_update_bits(chip, reg,
1108 (mask << shift_left) | (mask << shift_right),
1109 (val1 << shift_left ) | (val2 << shift_right));
1110}
1111
a5f22156
TI		 1112static int snd_fm801_info_mux(struct snd_kcontrol *kcontrol,
1113 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1114{
1115 static char *texts[5] = {
1116 "AC97 Primary", "FM", "I2S", "PCM", "AC97 Secondary"
1117 };
1118
1119 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1120 uinfo->count = 1;
1121 uinfo->value.enumerated.items = 5;
1122 if (uinfo->value.enumerated.item > 4)
1123 uinfo->value.enumerated.item = 4;
1124 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1125 return 0;
1126}
1127
a5f22156
TI		 1128static int snd_fm801_get_mux(struct snd_kcontrol *kcontrol,
1129 struct snd_ctl_elem_value *ucontrol)
1da177e4 1130{
a5f22156 1131 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1132 unsigned short val;
1133
1134 val = inw(FM801_REG(chip, REC_SRC)) & 7;
1135 if (val > 4)
1136 val = 4;
1137 ucontrol->value.enumerated.item[0] = val;
1138 return 0;
1139}
1140
a5f22156
TI		 1141static int snd_fm801_put_mux(struct snd_kcontrol *kcontrol,
1142 struct snd_ctl_elem_value *ucontrol)
1da177e4 1143{
a5f22156 1144 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1145 unsigned short val;
1146
1147 if ((val = ucontrol->value.enumerated.item[0]) > 4)
1148 return -EINVAL;
1149 return snd_fm801_update_bits(chip, FM801_REC_SRC, 7, val);
1150}
1151
a5f22156 1152#define FM801_CONTROLS ARRAY_SIZE(snd_fm801_controls)
1da177e4 1153
a5f22156 1154static struct snd_kcontrol_new snd_fm801_controls[] __devinitdata = {
1da177e4
LT		 1155FM801_DOUBLE("Wave Playback Volume", FM801_PCM_VOL, 0, 8, 31, 1),
1156FM801_SINGLE("Wave Playback Switch", FM801_PCM_VOL, 15, 1, 1),
1157FM801_DOUBLE("I2S Playback Volume", FM801_I2S_VOL, 0, 8, 31, 1),
1158FM801_SINGLE("I2S Playback Switch", FM801_I2S_VOL, 15, 1, 1),
1159FM801_DOUBLE("FM Playback Volume", FM801_FM_VOL, 0, 8, 31, 1),
1160FM801_SINGLE("FM Playback Switch", FM801_FM_VOL, 15, 1, 1),
1161{
1162 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1163 .name = "Digital Capture Source",
1164 .info = snd_fm801_info_mux,
1165 .get = snd_fm801_get_mux,
1166 .put = snd_fm801_put_mux,
1167}
1168};
1169
a5f22156 1170#define FM801_CONTROLS_MULTI ARRAY_SIZE(snd_fm801_controls_multi)
1da177e4 1171
a5f22156 1172static struct snd_kcontrol_new snd_fm801_controls_multi[] __devinitdata = {
1da177e4
LT		 1173FM801_SINGLE("AC97 2ch->4ch Copy Switch", FM801_CODEC_CTRL, 7, 1, 0),
1174FM801_SINGLE("AC97 18-bit Switch", FM801_CODEC_CTRL, 10, 1, 0),
10e8d78a
CL		 1175FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), FM801_I2S_MODE, 8, 1, 0),
1176FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",PLAYBACK,SWITCH), FM801_I2S_MODE, 9, 1, 0),
1177FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",CAPTURE,SWITCH), FM801_I2S_MODE, 10, 1, 0),
1178FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), FM801_GEN_CTRL, 2, 1, 0),
1da177e4
LT		 1179};
1180
a5f22156 1181static void snd_fm801_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1182{
a5f22156 1183 struct fm801 *chip = bus->private_data;
1da177e4
LT		 1184 chip->ac97_bus = NULL;
1185}
1186
a5f22156 1187static void snd_fm801_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1188{
a5f22156 1189 struct fm801 *chip = ac97->private_data;
1da177e4
LT		 1190 if (ac97->num == 0) {
1191 chip->ac97 = NULL;
1192 } else {
1193 chip->ac97_sec = NULL;
1194 }
1195}
1196
a5f22156 1197static int __devinit snd_fm801_mixer(struct fm801 *chip)
1da177e4 1198{
a5f22156 1199 struct snd_ac97_template ac97;
1da177e4
LT		 1200 unsigned int i;
1201 int err;
a5f22156 1202 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1203 .write = snd_fm801_codec_write,
1204 .read = snd_fm801_codec_read,
1205 };
1206
1207 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1208 return err;
1209 chip->ac97_bus->private_free = snd_fm801_mixer_free_ac97_bus;
1210
1211 memset(&ac97, 0, sizeof(ac97));
1212 ac97.private_data = chip;
1213 ac97.private_free = snd_fm801_mixer_free_ac97;
1214 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1215 return err;
1216 if (chip->secondary) {
1217 ac97.num = 1;
1218 ac97.addr = chip->secondary_addr;
1219 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_sec)) < 0)
1220 return err;
1221 }
1222 for (i = 0; i < FM801_CONTROLS; i++)
1223 snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls[i], chip));
1224 if (chip->multichannel) {
1225 for (i = 0; i < FM801_CONTROLS_MULTI; i++)
1226 snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls_multi[i], chip));
1227 }
1228 return 0;
1229}
1230
1231/*
1232 * initialization routines
1233 */
1234
b1e9ed26
TI		 1235static int wait_for_codec(struct fm801 *chip, unsigned int codec_id,
1236 unsigned short reg, unsigned long waits)
1237{
1238 unsigned long timeout = jiffies + waits;
1239
1240 outw(FM801_AC97_READ | (codec_id << FM801_AC97_ADDR_SHIFT) | reg,
1241 FM801_REG(chip, AC97_CMD));
1242 udelay(5);
1243 do {
1244 if ((inw(FM801_REG(chip, AC97_CMD)) & (FM801_AC97_VALID|FM801_AC97_BUSY))
1245 == FM801_AC97_VALID)
1246 return 0;
1247 schedule_timeout_uninterruptible(1);
1248 } while (time_after(timeout, jiffies));
1249 return -EIO;
1250}
1251
1252static int snd_fm801_chip_init(struct fm801 *chip, int resume)
1253{
1254 int id;
1255 unsigned short cmdw;
1256
6bbe13ec 1257 if (chip->tea575x_tuner & 0x0010)
e0a5d82a
AS		 1258 goto __ac97_ok;
1259
b1e9ed26
TI		 1260 /* codec cold reset + AC'97 warm reset */
1261 outw((1<<5) | (1<<6), FM801_REG(chip, CODEC_CTRL));
1262 inw(FM801_REG(chip, CODEC_CTRL)); /* flush posting data */
1263 udelay(100);
1264 outw(0, FM801_REG(chip, CODEC_CTRL));
1265
1266 if (wait_for_codec(chip, 0, AC97_RESET, msecs_to_jiffies(750)) < 0) {
1267 snd_printk(KERN_ERR "Primary AC'97 codec not found\n");
1268 if (! resume)
1269 return -EIO;
1270 }
1271
1272 if (chip->multichannel) {
1273 if (chip->secondary_addr) {
1274 wait_for_codec(chip, chip->secondary_addr,
1275 AC97_VENDOR_ID1, msecs_to_jiffies(50));
1276 } else {
1277 /* my card has the secondary codec */
1278 /* at address #3, so the loop is inverted */
1279 for (id = 3; id > 0; id--) {
1280 if (! wait_for_codec(chip, id, AC97_VENDOR_ID1,
1281 msecs_to_jiffies(50))) {
1282 cmdw = inw(FM801_REG(chip, AC97_DATA));
1283 if (cmdw != 0xffff && cmdw != 0) {
1284 chip->secondary = 1;
1285 chip->secondary_addr = id;
1286 break;
1287 }
1288 }
1289 }
1290 }
1291
1292 /* the recovery phase, it seems that probing for non-existing codec might */
1293 /* cause timeout problems */
1294 wait_for_codec(chip, 0, AC97_VENDOR_ID1, msecs_to_jiffies(750));
1295 }
1296
6bbe13ec
JK		 1297 __ac97_ok:
1298
b1e9ed26
TI		 1299 /* init volume */
1300 outw(0x0808, FM801_REG(chip, PCM_VOL));
1301 outw(0x9f1f, FM801_REG(chip, FM_VOL));
1302 outw(0x8808, FM801_REG(chip, I2S_VOL));
1303
1304 /* I2S control - I2S mode */
1305 outw(0x0003, FM801_REG(chip, I2S_MODE));
1306
6bbe13ec 1307 /* interrupt setup */
b1e9ed26 1308 cmdw = inw(FM801_REG(chip, IRQ_MASK));
6bbe13ec
JK		 1309 if (chip->irq < 0)
1310 cmdw |= 0x00c3; /* mask everything, no PCM nor MPU */
1311 else
1312 cmdw &= ~0x0083; /* unmask MPU, PLAYBACK & CAPTURE */
b1e9ed26
TI		 1313 outw(cmdw, FM801_REG(chip, IRQ_MASK));
1314
1315 /* interrupt clear */
1316 outw(FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU, FM801_REG(chip, IRQ_STATUS));
1317
1318 return 0;
1319}
1320
1321
a5f22156 1322static int snd_fm801_free(struct fm801 *chip)
1da177e4
LT		 1323{
1324 unsigned short cmdw;
1325
1326 if (chip->irq < 0)
1327 goto __end_hw;
1328
1329 /* interrupt setup - mask everything */
1330 cmdw = inw(FM801_REG(chip, IRQ_MASK));
1331 cmdw |= 0x00c3;
1332 outw(cmdw, FM801_REG(chip, IRQ_MASK));
1333
1334 __end_hw:
1335#ifdef TEA575X_RADIO
1336 snd_tea575x_exit(&chip->tea);
1337#endif
1338 if (chip->irq >= 0)
a5f22156 1339 free_irq(chip->irq, chip);
1da177e4
LT		 1340 pci_release_regions(chip->pci);
1341 pci_disable_device(chip->pci);
1342
1343 kfree(chip);
1344 return 0;
1345}
1346
a5f22156 1347static int snd_fm801_dev_free(struct snd_device *device)
1da177e4 1348{
a5f22156 1349 struct fm801 *chip = device->device_data;
1da177e4
LT		 1350 return snd_fm801_free(chip);
1351}
1352
a5f22156 1353static int __devinit snd_fm801_create(struct snd_card *card,
1da177e4
LT		 1354 struct pci_dev * pci,
1355 int tea575x_tuner,
a5f22156 1356 struct fm801 ** rchip)
1da177e4 1357{
a5f22156 1358 struct fm801 *chip;
b1e9ed26 1359 unsigned char rev;
1da177e4 1360 int err;
a5f22156 1361 static struct snd_device_ops ops = {
1da177e4
LT		 1362 .dev_free = snd_fm801_dev_free,
1363 };
1364
1365 *rchip = NULL;
1366 if ((err = pci_enable_device(pci)) < 0)
1367 return err;
e560d8d8 1368 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1369 if (chip == NULL) {
1370 pci_disable_device(pci);
1371 return -ENOMEM;
1372 }
1373 spin_lock_init(&chip->reg_lock);
1374 chip->card = card;
1375 chip->pci = pci;
1376 chip->irq = -1;
6bbe13ec 1377 chip->tea575x_tuner = tea575x_tuner;
1da177e4
LT		 1378 if ((err = pci_request_regions(pci, "FM801")) < 0) {
1379 kfree(chip);
1380 pci_disable_device(pci);
1381 return err;
1382 }
1383 chip->port = pci_resource_start(pci, 0);
6bbe13ec
JK		 1384 if ((tea575x_tuner & 0x0010) == 0) {
1385 if (request_irq(pci->irq, snd_fm801_interrupt, IRQF_DISABLED|IRQF_SHARED,
1386 "FM801", chip)) {
1387 snd_printk(KERN_ERR "unable to grab IRQ %d\n", chip->irq);
1388 snd_fm801_free(chip);
1389 return -EBUSY;
1390 }
1391 chip->irq = pci->irq;
1392 pci_set_master(pci);
1da177e4 1393 }
1da177e4
LT		 1394
1395 pci_read_config_byte(pci, PCI_REVISION_ID, &rev);
1396 if (rev >= 0xb1) /* FM801-AU */
1397 chip->multichannel = 1;
1398
b1e9ed26 1399 snd_fm801_chip_init(chip, 0);
1da177e4
LT		 1400
1401 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1402 snd_fm801_free(chip);
1403 return err;
1404 }
1405
1406 snd_card_set_dev(card, &pci->dev);
1407
1408#ifdef TEA575X_RADIO
e0a5d82a 1409 if (tea575x_tuner > 0 && (tea575x_tuner & 0x000f) < 4) {
1da177e4
LT		 1410 chip->tea.dev_nr = tea575x_tuner >> 16;
1411 chip->tea.card = card;
1412 chip->tea.freq_fixup = 10700;
1413 chip->tea.private_data = chip;
e0a5d82a 1414 chip->tea.ops = &snd_fm801_tea_ops[(tea575x_tuner & 0x000f) - 1];
1da177e4
LT		 1415 snd_tea575x_init(&chip->tea);
1416 }
1417#endif
1418
1419 *rchip = chip;
1420 return 0;
1421}
1422
1423static int __devinit snd_card_fm801_probe(struct pci_dev *pci,
1424 const struct pci_device_id *pci_id)
1425{
1426 static int dev;
a5f22156
TI		 1427 struct snd_card *card;
1428 struct fm801 *chip;
1429 struct snd_opl3 *opl3;
1da177e4
LT		 1430 int err;
1431
1432 if (dev >= SNDRV_CARDS)
1433 return -ENODEV;
1434 if (!enable[dev]) {
1435 dev++;
1436 return -ENOENT;
1437 }
1438
1439 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1440 if (card == NULL)
1441 return -ENOMEM;
1442 if ((err = snd_fm801_create(card, pci, tea575x_tuner[dev], &chip)) < 0) {
1443 snd_card_free(card);
1444 return err;
1445 }
b1e9ed26 1446 card->private_data = chip;
1da177e4
LT		 1447
1448 strcpy(card->driver, "FM801");
1449 strcpy(card->shortname, "ForteMedia FM801-");
1450 strcat(card->shortname, chip->multichannel ? "AU" : "AS");
1451 sprintf(card->longname, "%s at 0x%lx, irq %i",
1452 card->shortname, chip->port, chip->irq);
1453
e0a5d82a
AS		 1454 if (tea575x_tuner[dev] & 0x0010)
1455 goto __fm801_tuner_only;
1456
1da177e4
LT		 1457 if ((err = snd_fm801_pcm(chip, 0, NULL)) < 0) {
1458 snd_card_free(card);
1459 return err;
1460 }
1461 if ((err = snd_fm801_mixer(chip)) < 0) {
1462 snd_card_free(card);
1463 return err;
1464 }
1465 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_FM801,
302e4c2f
TI		 1466 FM801_REG(chip, MPU401_DATA),
1467 MPU401_INFO_INTEGRATED,
1da177e4
LT		 1468 chip->irq, 0, &chip->rmidi)) < 0) {
1469 snd_card_free(card);
1470 return err;
1471 }
1472 if ((err = snd_opl3_create(card, FM801_REG(chip, OPL3_BANK0),
1473 FM801_REG(chip, OPL3_BANK1),
1474 OPL3_HW_OPL3_FM801, 1, &opl3)) < 0) {
1475 snd_card_free(card);
1476 return err;
1477 }
1478 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1479 snd_card_free(card);
1480 return err;
1481 }
1482
e0a5d82a 1483 __fm801_tuner_only:
1da177e4
LT		 1484 if ((err = snd_card_register(card)) < 0) {
1485 snd_card_free(card);
1486 return err;
1487 }
1488 pci_set_drvdata(pci, card);
1489 dev++;
1490 return 0;
1491}
1492
1493static void __devexit snd_card_fm801_remove(struct pci_dev *pci)
1494{
1495 snd_card_free(pci_get_drvdata(pci));
1496 pci_set_drvdata(pci, NULL);
1497}
1498
b1e9ed26
TI		 1499#ifdef CONFIG_PM
1500static unsigned char saved_regs[] = {
1501 FM801_PCM_VOL, FM801_I2S_VOL, FM801_FM_VOL, FM801_REC_SRC,
1502 FM801_PLY_CTRL, FM801_PLY_COUNT, FM801_PLY_BUF1, FM801_PLY_BUF2,
1503 FM801_CAP_CTRL, FM801_CAP_COUNT, FM801_CAP_BUF1, FM801_CAP_BUF2,
1504 FM801_CODEC_CTRL, FM801_I2S_MODE, FM801_VOLUME, FM801_GEN_CTRL,
1505};
1506
1507static int snd_fm801_suspend(struct pci_dev *pci, pm_message_t state)
1508{
1509 struct snd_card *card = pci_get_drvdata(pci);
1510 struct fm801 *chip = card->private_data;
1511 int i;
1512
1513 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1514 snd_pcm_suspend_all(chip->pcm);
1515 snd_ac97_suspend(chip->ac97);
1516 snd_ac97_suspend(chip->ac97_sec);
1517 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1518 chip->saved_regs[i] = inw(chip->port + saved_regs[i]);
1519 /* FIXME: tea575x suspend */
1520
1521 pci_set_power_state(pci, PCI_D3hot);
1522 pci_disable_device(pci);
1523 pci_save_state(pci);
1524 return 0;
1525}
1526
1527static int snd_fm801_resume(struct pci_dev *pci)
1528{
1529 struct snd_card *card = pci_get_drvdata(pci);
1530 struct fm801 *chip = card->private_data;
1531 int i;
1532
1533 pci_restore_state(pci);
1534 pci_enable_device(pci);
1535 pci_set_power_state(pci, PCI_D0);
1536 pci_set_master(pci);
1537
1538 snd_fm801_chip_init(chip, 1);
1539 snd_ac97_resume(chip->ac97);
1540 snd_ac97_resume(chip->ac97_sec);
1541 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1542 outw(chip->saved_regs[i], chip->port + saved_regs[i]);
1543
1544 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1545 return 0;
1546}
1547#endif
1548
1da177e4
LT		 1549static struct pci_driver driver = {
1550 .name = "FM801",
1551 .id_table = snd_fm801_ids,
1552 .probe = snd_card_fm801_probe,
1553 .remove = __devexit_p(snd_card_fm801_remove),
b1e9ed26
TI		 1554#ifdef CONFIG_PM
1555 .suspend = snd_fm801_suspend,
1556 .resume = snd_fm801_resume,
1557#endif
1da177e4
LT		 1558};
1559
1560static int __init alsa_card_fm801_init(void)
1561{
01d25d46 1562 return pci_register_driver(&driver);
1da177e4
LT		 1563}
1564
1565static void __exit alsa_card_fm801_exit(void)
1566{
1567 pci_unregister_driver(&driver);
1568}
1569
1570module_init(alsa_card_fm801_init)
1571module_exit(alsa_card_fm801_exit)
kernel source for telekom puls (alcatel/mediatek)