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ALSA: ctxfi - Allow 64bit DMA
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / ctxfi / cthw20k1.c
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8cc72361
WYC		 1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthw20k1.c
9 *
10 * @Brief
11 * This file contains the implementation of hardware access methord for 20k1.
12 *
13 * @Author Liu Chun
14 * @Date Jun 24 2008
15 *
16 */
17
8cc72361
WYC		 18#include <linux/types.h>
19#include <linux/slab.h>
20#include <linux/pci.h>
21#include <linux/io.h>
22#include <linux/string.h>
23#include <linux/spinlock.h>
24#include <linux/kernel.h>
25#include <linux/interrupt.h>
d0da727e 26#include <linux/delay.h>
6d74b86d
TI		 27#include "cthw20k1.h"
28#include "ct20k1reg.h"
8cc72361 29
6d74b86d
TI		 30#if BITS_PER_LONG == 32
31#define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bit PTE */
32#else
33#define CT_XFI_DMA_MASK DMA_BIT_MASK(64) /* 64 bit PTE */
34#endif
8cc72361
WYC		 35
36struct hw20k1 {
37 struct hw hw;
38 spinlock_t reg_20k1_lock;
39 spinlock_t reg_pci_lock;
40};
41
42static u32 hw_read_20kx(struct hw *hw, u32 reg);
43static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
44static u32 hw_read_pci(struct hw *hw, u32 reg);
45static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
46
47/*
48 * Type definition block.
49 * The layout of control structures can be directly applied on 20k2 chip.
50 */
51
52/*
53 * SRC control block definitions.
54 */
55
56/* SRC resource control block */
57#define SRCCTL_STATE 0x00000007
58#define SRCCTL_BM 0x00000008
59#define SRCCTL_RSR 0x00000030
60#define SRCCTL_SF 0x000001C0
61#define SRCCTL_WR 0x00000200
62#define SRCCTL_PM 0x00000400
63#define SRCCTL_ROM 0x00001800
64#define SRCCTL_VO 0x00002000
65#define SRCCTL_ST 0x00004000
66#define SRCCTL_IE 0x00008000
67#define SRCCTL_ILSZ 0x000F0000
68#define SRCCTL_BP 0x00100000
69
70#define SRCCCR_CISZ 0x000007FF
71#define SRCCCR_CWA 0x001FF800
72#define SRCCCR_D 0x00200000
73#define SRCCCR_RS 0x01C00000
74#define SRCCCR_NAL 0x3E000000
75#define SRCCCR_RA 0xC0000000
76
77#define SRCCA_CA 0x03FFFFFF
78#define SRCCA_RS 0x1C000000
79#define SRCCA_NAL 0xE0000000
80
81#define SRCSA_SA 0x03FFFFFF
82
83#define SRCLA_LA 0x03FFFFFF
84
85/* Mixer Parameter Ring ram Low and Hight register.
86 * Fixed-point value in 8.24 format for parameter channel */
87#define MPRLH_PITCH 0xFFFFFFFF
88
89/* SRC resource register dirty flags */
90union src_dirty {
91 struct {
92 u16 ctl:1;
93 u16 ccr:1;
94 u16 sa:1;
95 u16 la:1;
96 u16 ca:1;
97 u16 mpr:1;
98 u16 czbfs:1; /* Clear Z-Buffers */
99 u16 rsv:9;
100 } bf;
101 u16 data;
102};
103
104struct src_rsc_ctrl_blk {
105 unsigned int ctl;
106 unsigned int ccr;
107 unsigned int ca;
108 unsigned int sa;
109 unsigned int la;
110 unsigned int mpr;
111 union src_dirty dirty;
112};
113
114/* SRC manager control block */
115union src_mgr_dirty {
116 struct {
117 u16 enb0:1;
118 u16 enb1:1;
119 u16 enb2:1;
120 u16 enb3:1;
121 u16 enb4:1;
122 u16 enb5:1;
123 u16 enb6:1;
124 u16 enb7:1;
125 u16 enbsa:1;
126 u16 rsv:7;
127 } bf;
128 u16 data;
129};
130
131struct src_mgr_ctrl_blk {
132 unsigned int enbsa;
133 unsigned int enb[8];
134 union src_mgr_dirty dirty;
135};
136
137/* SRCIMP manager control block */
138#define SRCAIM_ARC 0x00000FFF
139#define SRCAIM_NXT 0x00FF0000
140#define SRCAIM_SRC 0xFF000000
141
142struct srcimap {
143 unsigned int srcaim;
144 unsigned int idx;
145};
146
147/* SRCIMP manager register dirty flags */
148union srcimp_mgr_dirty {
149 struct {
150 u16 srcimap:1;
151 u16 rsv:15;
152 } bf;
153 u16 data;
154};
155
156struct srcimp_mgr_ctrl_blk {
157 struct srcimap srcimap;
158 union srcimp_mgr_dirty dirty;
159};
160
161/*
162 * Function implementation block.
163 */
164
165static int src_get_rsc_ctrl_blk(void **rblk)
166{
167 struct src_rsc_ctrl_blk *blk;
168
169 *rblk = NULL;
170 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
171 if (NULL == blk)
172 return -ENOMEM;
173
174 *rblk = blk;
175
176 return 0;
177}
178
179static int src_put_rsc_ctrl_blk(void *blk)
180{
181 kfree((struct src_rsc_ctrl_blk *)blk);
182
183 return 0;
184}
185
186static int src_set_state(void *blk, unsigned int state)
187{
188 struct src_rsc_ctrl_blk *ctl = blk;
189
190 set_field(&ctl->ctl, SRCCTL_STATE, state);
191 ctl->dirty.bf.ctl = 1;
192 return 0;
193}
194
195static int src_set_bm(void *blk, unsigned int bm)
196{
197 struct src_rsc_ctrl_blk *ctl = blk;
198
199 set_field(&ctl->ctl, SRCCTL_BM, bm);
200 ctl->dirty.bf.ctl = 1;
201 return 0;
202}
203
204static int src_set_rsr(void *blk, unsigned int rsr)
205{
206 struct src_rsc_ctrl_blk *ctl = blk;
207
208 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
209 ctl->dirty.bf.ctl = 1;
210 return 0;
211}
212
213static int src_set_sf(void *blk, unsigned int sf)
214{
215 struct src_rsc_ctrl_blk *ctl = blk;
216
217 set_field(&ctl->ctl, SRCCTL_SF, sf);
218 ctl->dirty.bf.ctl = 1;
219 return 0;
220}
221
222static int src_set_wr(void *blk, unsigned int wr)
223{
224 struct src_rsc_ctrl_blk *ctl = blk;
225
226 set_field(&ctl->ctl, SRCCTL_WR, wr);
227 ctl->dirty.bf.ctl = 1;
228 return 0;
229}
230
231static int src_set_pm(void *blk, unsigned int pm)
232{
233 struct src_rsc_ctrl_blk *ctl = blk;
234
235 set_field(&ctl->ctl, SRCCTL_PM, pm);
236 ctl->dirty.bf.ctl = 1;
237 return 0;
238}
239
240static int src_set_rom(void *blk, unsigned int rom)
241{
242 struct src_rsc_ctrl_blk *ctl = blk;
243
244 set_field(&ctl->ctl, SRCCTL_ROM, rom);
245 ctl->dirty.bf.ctl = 1;
246 return 0;
247}
248
249static int src_set_vo(void *blk, unsigned int vo)
250{
251 struct src_rsc_ctrl_blk *ctl = blk;
252
253 set_field(&ctl->ctl, SRCCTL_VO, vo);
254 ctl->dirty.bf.ctl = 1;
255 return 0;
256}
257
258static int src_set_st(void *blk, unsigned int st)
259{
260 struct src_rsc_ctrl_blk *ctl = blk;
261
262 set_field(&ctl->ctl, SRCCTL_ST, st);
263 ctl->dirty.bf.ctl = 1;
264 return 0;
265}
266
267static int src_set_ie(void *blk, unsigned int ie)
268{
269 struct src_rsc_ctrl_blk *ctl = blk;
270
271 set_field(&ctl->ctl, SRCCTL_IE, ie);
272 ctl->dirty.bf.ctl = 1;
273 return 0;
274}
275
276static int src_set_ilsz(void *blk, unsigned int ilsz)
277{
278 struct src_rsc_ctrl_blk *ctl = blk;
279
280 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
281 ctl->dirty.bf.ctl = 1;
282 return 0;
283}
284
285static int src_set_bp(void *blk, unsigned int bp)
286{
287 struct src_rsc_ctrl_blk *ctl = blk;
288
289 set_field(&ctl->ctl, SRCCTL_BP, bp);
290 ctl->dirty.bf.ctl = 1;
291 return 0;
292}
293
294static int src_set_cisz(void *blk, unsigned int cisz)
295{
296 struct src_rsc_ctrl_blk *ctl = blk;
297
298 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
299 ctl->dirty.bf.ccr = 1;
300 return 0;
301}
302
303static int src_set_ca(void *blk, unsigned int ca)
304{
305 struct src_rsc_ctrl_blk *ctl = blk;
306
307 set_field(&ctl->ca, SRCCA_CA, ca);
308 ctl->dirty.bf.ca = 1;
309 return 0;
310}
311
312static int src_set_sa(void *blk, unsigned int sa)
313{
314 struct src_rsc_ctrl_blk *ctl = blk;
315
316 set_field(&ctl->sa, SRCSA_SA, sa);
317 ctl->dirty.bf.sa = 1;
318 return 0;
319}
320
321static int src_set_la(void *blk, unsigned int la)
322{
323 struct src_rsc_ctrl_blk *ctl = blk;
324
325 set_field(&ctl->la, SRCLA_LA, la);
326 ctl->dirty.bf.la = 1;
327 return 0;
328}
329
330static int src_set_pitch(void *blk, unsigned int pitch)
331{
332 struct src_rsc_ctrl_blk *ctl = blk;
333
334 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
335 ctl->dirty.bf.mpr = 1;
336 return 0;
337}
338
339static int src_set_clear_zbufs(void *blk, unsigned int clear)
340{
341 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
342 return 0;
343}
344
345static int src_set_dirty(void *blk, unsigned int flags)
346{
347 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
348 return 0;
349}
350
351static int src_set_dirty_all(void *blk)
352{
353 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
354 return 0;
355}
356
357#define AR_SLOT_SIZE 4096
358#define AR_SLOT_BLOCK_SIZE 16
359#define AR_PTS_PITCH 6
360#define AR_PARAM_SRC_OFFSET 0x60
361
362static unsigned int src_param_pitch_mixer(unsigned int src_idx)
363{
364 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
365 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
366
367}
368
369static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
370{
371 struct src_rsc_ctrl_blk *ctl = blk;
372 int i = 0;
373
374 if (ctl->dirty.bf.czbfs) {
375 /* Clear Z-Buffer registers */
376 for (i = 0; i < 8; i++)
377 hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0);
378
379 for (i = 0; i < 4; i++)
380 hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0);
381
382 for (i = 0; i < 8; i++)
383 hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0);
384
385 ctl->dirty.bf.czbfs = 0;
386 }
387 if (ctl->dirty.bf.mpr) {
388 /* Take the parameter mixer resource in the same group as that
389 * the idx src is in for simplicity. Unlike src, all conjugate
390 * parameter mixer resources must be programmed for
391 * corresponding conjugate src resources. */
392 unsigned int pm_idx = src_param_pitch_mixer(idx);
393 hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
394 hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3);
395 hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0);
396 ctl->dirty.bf.mpr = 0;
397 }
398 if (ctl->dirty.bf.sa) {
399 hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
400 ctl->dirty.bf.sa = 0;
401 }
402 if (ctl->dirty.bf.la) {
403 hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
404 ctl->dirty.bf.la = 0;
405 }
406 if (ctl->dirty.bf.ca) {
407 hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
408 ctl->dirty.bf.ca = 0;
409 }
410
411 /* Write srccf register */
412 hw_write_20kx(hw, SRCCF+idx*0x100, 0x0);
413
414 if (ctl->dirty.bf.ccr) {
415 hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
416 ctl->dirty.bf.ccr = 0;
417 }
418 if (ctl->dirty.bf.ctl) {
419 hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
420 ctl->dirty.bf.ctl = 0;
421 }
422
423 return 0;
424}
425
426static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
427{
428 struct src_rsc_ctrl_blk *ctl = blk;
429
430 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
431 ctl->dirty.bf.ca = 0;
432
433 return get_field(ctl->ca, SRCCA_CA);
434}
435
436static unsigned int src_get_dirty(void *blk)
437{
438 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
439}
440
441static unsigned int src_dirty_conj_mask(void)
442{
443 return 0x20;
444}
445
446static int src_mgr_enbs_src(void *blk, unsigned int idx)
447{
448 ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
449 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
450 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
451 return 0;
452}
453
454static int src_mgr_enb_src(void *blk, unsigned int idx)
455{
456 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
457 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
458 return 0;
459}
460
461static int src_mgr_dsb_src(void *blk, unsigned int idx)
462{
463 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
464 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
465 return 0;
466}
467
468static int src_mgr_commit_write(struct hw *hw, void *blk)
469{
470 struct src_mgr_ctrl_blk *ctl = blk;
471 int i = 0;
472 unsigned int ret = 0;
473
474 if (ctl->dirty.bf.enbsa) {
475 do {
476 ret = hw_read_20kx(hw, SRCENBSTAT);
477 } while (ret & 0x1);
478 hw_write_20kx(hw, SRCENBS, ctl->enbsa);
479 ctl->dirty.bf.enbsa = 0;
480 }
481 for (i = 0; i < 8; i++) {
482 if ((ctl->dirty.data & (0x1 << i))) {
483 hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
484 ctl->dirty.data &= ~(0x1 << i);
485 }
486 }
487
488 return 0;
489}
490
491static int src_mgr_get_ctrl_blk(void **rblk)
492{
493 struct src_mgr_ctrl_blk *blk;
494
495 *rblk = NULL;
496 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
497 if (NULL == blk)
498 return -ENOMEM;
499
500 *rblk = blk;
501
502 return 0;
503}
504
505static int src_mgr_put_ctrl_blk(void *blk)
506{
507 kfree((struct src_mgr_ctrl_blk *)blk);
508
509 return 0;
510}
511
512static int srcimp_mgr_get_ctrl_blk(void **rblk)
513{
514 struct srcimp_mgr_ctrl_blk *blk;
515
516 *rblk = NULL;
517 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
518 if (NULL == blk)
519 return -ENOMEM;
520
521 *rblk = blk;
522
523 return 0;
524}
525
526static int srcimp_mgr_put_ctrl_blk(void *blk)
527{
528 kfree((struct srcimp_mgr_ctrl_blk *)blk);
529
530 return 0;
531}
532
533static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
534{
535 struct srcimp_mgr_ctrl_blk *ctl = blk;
536
537 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
538 ctl->dirty.bf.srcimap = 1;
539 return 0;
540}
541
542static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
543{
544 struct srcimp_mgr_ctrl_blk *ctl = blk;
545
546 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
547 ctl->dirty.bf.srcimap = 1;
548 return 0;
549}
550
551static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
552{
553 struct srcimp_mgr_ctrl_blk *ctl = blk;
554
555 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
556 ctl->dirty.bf.srcimap = 1;
557 return 0;
558}
559
560static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
561{
562 struct srcimp_mgr_ctrl_blk *ctl = blk;
563
564 ctl->srcimap.idx = addr;
565 ctl->dirty.bf.srcimap = 1;
566 return 0;
567}
568
569static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
570{
571 struct srcimp_mgr_ctrl_blk *ctl = blk;
572
573 if (ctl->dirty.bf.srcimap) {
574 hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
575 ctl->srcimap.srcaim);
576 ctl->dirty.bf.srcimap = 0;
577 }
578
579 return 0;
580}
581
582/*
583 * AMIXER control block definitions.
584 */
585
586#define AMOPLO_M 0x00000003
587#define AMOPLO_X 0x0003FFF0
588#define AMOPLO_Y 0xFFFC0000
589
590#define AMOPHI_SADR 0x000000FF
591#define AMOPHI_SE 0x80000000
592
593/* AMIXER resource register dirty flags */
594union amixer_dirty {
595 struct {
596 u16 amoplo:1;
597 u16 amophi:1;
598 u16 rsv:14;
599 } bf;
600 u16 data;
601};
602
603/* AMIXER resource control block */
604struct amixer_rsc_ctrl_blk {
605 unsigned int amoplo;
606 unsigned int amophi;
607 union amixer_dirty dirty;
608};
609
610static int amixer_set_mode(void *blk, unsigned int mode)
611{
612 struct amixer_rsc_ctrl_blk *ctl = blk;
613
614 set_field(&ctl->amoplo, AMOPLO_M, mode);
615 ctl->dirty.bf.amoplo = 1;
616 return 0;
617}
618
619static int amixer_set_iv(void *blk, unsigned int iv)
620{
621 /* 20k1 amixer does not have this field */
622 return 0;
623}
624
625static int amixer_set_x(void *blk, unsigned int x)
626{
627 struct amixer_rsc_ctrl_blk *ctl = blk;
628
629 set_field(&ctl->amoplo, AMOPLO_X, x);
630 ctl->dirty.bf.amoplo = 1;
631 return 0;
632}
633
634static int amixer_set_y(void *blk, unsigned int y)
635{
636 struct amixer_rsc_ctrl_blk *ctl = blk;
637
638 set_field(&ctl->amoplo, AMOPLO_Y, y);
639 ctl->dirty.bf.amoplo = 1;
640 return 0;
641}
642
643static int amixer_set_sadr(void *blk, unsigned int sadr)
644{
645 struct amixer_rsc_ctrl_blk *ctl = blk;
646
647 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
648 ctl->dirty.bf.amophi = 1;
649 return 0;
650}
651
652static int amixer_set_se(void *blk, unsigned int se)
653{
654 struct amixer_rsc_ctrl_blk *ctl = blk;
655
656 set_field(&ctl->amophi, AMOPHI_SE, se);
657 ctl->dirty.bf.amophi = 1;
658 return 0;
659}
660
661static int amixer_set_dirty(void *blk, unsigned int flags)
662{
663 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
664 return 0;
665}
666
667static int amixer_set_dirty_all(void *blk)
668{
669 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
670 return 0;
671}
672
673static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
674{
675 struct amixer_rsc_ctrl_blk *ctl = blk;
676
677 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
678 hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
679 ctl->dirty.bf.amoplo = 0;
680 hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
681 ctl->dirty.bf.amophi = 0;
682 }
683
684 return 0;
685}
686
687static int amixer_get_y(void *blk)
688{
689 struct amixer_rsc_ctrl_blk *ctl = blk;
690
691 return get_field(ctl->amoplo, AMOPLO_Y);
692}
693
694static unsigned int amixer_get_dirty(void *blk)
695{
696 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
697}
698
699static int amixer_rsc_get_ctrl_blk(void **rblk)
700{
701 struct amixer_rsc_ctrl_blk *blk;
702
703 *rblk = NULL;
704 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
705 if (NULL == blk)
706 return -ENOMEM;
707
708 *rblk = blk;
709
710 return 0;
711}
712
713static int amixer_rsc_put_ctrl_blk(void *blk)
714{
715 kfree((struct amixer_rsc_ctrl_blk *)blk);
716
717 return 0;
718}
719
720static int amixer_mgr_get_ctrl_blk(void **rblk)
721{
722 /*amixer_mgr_ctrl_blk_t *blk;*/
723
724 *rblk = NULL;
725 /*blk = kzalloc(sizeof(*blk), GFP_KERNEL);
726 if (NULL == blk)
727 return -ENOMEM;
728
729 *rblk = blk;*/
730
731 return 0;
732}
733
734static int amixer_mgr_put_ctrl_blk(void *blk)
735{
736 /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/
737
738 return 0;
739}
740
741/*
742 * DAIO control block definitions.
743 */
744
745/* Receiver Sample Rate Tracker Control register */
746#define SRTCTL_SRCR 0x000000FF
747#define SRTCTL_SRCL 0x0000FF00
748#define SRTCTL_RSR 0x00030000
749#define SRTCTL_DRAT 0x000C0000
750#define SRTCTL_RLE 0x10000000
751#define SRTCTL_RLP 0x20000000
752#define SRTCTL_EC 0x40000000
753#define SRTCTL_ET 0x80000000
754
755/* DAIO Receiver register dirty flags */
756union dai_dirty {
757 struct {
758 u16 srtctl:1;
759 u16 rsv:15;
760 } bf;
761 u16 data;
762};
763
764/* DAIO Receiver control block */
765struct dai_ctrl_blk {
766 unsigned int srtctl;
767 union dai_dirty dirty;
768};
769
770/* S/PDIF Transmitter register dirty flags */
771union dao_dirty {
772 struct {
773 u16 spos:1;
774 u16 rsv:15;
775 } bf;
776 u16 data;
777};
778
779/* S/PDIF Transmitter control block */
780struct dao_ctrl_blk {
781 unsigned int spos; /* S/PDIF Output Channel Status Register */
782 union dao_dirty dirty;
783};
784
785/* Audio Input Mapper RAM */
786#define AIM_ARC 0x00000FFF
787#define AIM_NXT 0x007F0000
788
789struct daoimap {
790 unsigned int aim;
791 unsigned int idx;
792};
793
794/* I2S Transmitter/Receiver Control register */
795#define I2SCTL_EA 0x00000004
796#define I2SCTL_EI 0x00000010
797
798/* S/PDIF Transmitter Control register */
799#define SPOCTL_OE 0x00000001
800#define SPOCTL_OS 0x0000000E
801#define SPOCTL_RIV 0x00000010
802#define SPOCTL_LIV 0x00000020
803#define SPOCTL_SR 0x000000C0
804
805/* S/PDIF Receiver Control register */
806#define SPICTL_EN 0x00000001
807#define SPICTL_I24 0x00000002
808#define SPICTL_IB 0x00000004
809#define SPICTL_SM 0x00000008
810#define SPICTL_VM 0x00000010
811
812/* DAIO manager register dirty flags */
813union daio_mgr_dirty {
814 struct {
815 u32 i2soctl:4;
816 u32 i2sictl:4;
817 u32 spoctl:4;
818 u32 spictl:4;
819 u32 daoimap:1;
820 u32 rsv:15;
821 } bf;
822 u32 data;
823};
824
825/* DAIO manager control block */
826struct daio_mgr_ctrl_blk {
827 unsigned int i2sctl;
828 unsigned int spoctl;
829 unsigned int spictl;
830 struct daoimap daoimap;
831 union daio_mgr_dirty dirty;
832};
833
834static int dai_srt_set_srcr(void *blk, unsigned int src)
835{
836 struct dai_ctrl_blk *ctl = blk;
837
838 set_field(&ctl->srtctl, SRTCTL_SRCR, src);
839 ctl->dirty.bf.srtctl = 1;
840 return 0;
841}
842
843static int dai_srt_set_srcl(void *blk, unsigned int src)
844{
845 struct dai_ctrl_blk *ctl = blk;
846
847 set_field(&ctl->srtctl, SRTCTL_SRCL, src);
848 ctl->dirty.bf.srtctl = 1;
849 return 0;
850}
851
852static int dai_srt_set_rsr(void *blk, unsigned int rsr)
853{
854 struct dai_ctrl_blk *ctl = blk;
855
856 set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
857 ctl->dirty.bf.srtctl = 1;
858 return 0;
859}
860
861static int dai_srt_set_drat(void *blk, unsigned int drat)
862{
863 struct dai_ctrl_blk *ctl = blk;
864
865 set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
866 ctl->dirty.bf.srtctl = 1;
867 return 0;
868}
869
870static int dai_srt_set_ec(void *blk, unsigned int ec)
871{
872 struct dai_ctrl_blk *ctl = blk;
873
874 set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
875 ctl->dirty.bf.srtctl = 1;
876 return 0;
877}
878
879static int dai_srt_set_et(void *blk, unsigned int et)
880{
881 struct dai_ctrl_blk *ctl = blk;
882
883 set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
884 ctl->dirty.bf.srtctl = 1;
885 return 0;
886}
887
888static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
889{
890 struct dai_ctrl_blk *ctl = blk;
891
892 if (ctl->dirty.bf.srtctl) {
893 if (idx < 4) {
894 /* S/PDIF SRTs */
895 hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
896 } else {
897 /* I2S SRT */
898 hw_write_20kx(hw, SRTICTL, ctl->srtctl);
899 }
900 ctl->dirty.bf.srtctl = 0;
901 }
902
903 return 0;
904}
905
906static int dai_get_ctrl_blk(void **rblk)
907{
908 struct dai_ctrl_blk *blk;
909
910 *rblk = NULL;
911 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
912 if (NULL == blk)
913 return -ENOMEM;
914
915 *rblk = blk;
916
917 return 0;
918}
919
920static int dai_put_ctrl_blk(void *blk)
921{
922 kfree((struct dai_ctrl_blk *)blk);
923
924 return 0;
925}
926
927static int dao_set_spos(void *blk, unsigned int spos)
928{
929 ((struct dao_ctrl_blk *)blk)->spos = spos;
930 ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
931 return 0;
932}
933
934static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
935{
936 struct dao_ctrl_blk *ctl = blk;
937
938 if (ctl->dirty.bf.spos) {
939 if (idx < 4) {
940 /* S/PDIF SPOSx */
941 hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
942 }
943 ctl->dirty.bf.spos = 0;
944 }
945
946 return 0;
947}
948
949static int dao_get_spos(void *blk, unsigned int *spos)
950{
951 *spos = ((struct dao_ctrl_blk *)blk)->spos;
952 return 0;
953}
954
955static int dao_get_ctrl_blk(void **rblk)
956{
957 struct dao_ctrl_blk *blk;
958
959 *rblk = NULL;
960 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
961 if (NULL == blk)
962 return -ENOMEM;
963
964 *rblk = blk;
965
966 return 0;
967}
968
969static int dao_put_ctrl_blk(void *blk)
970{
971 kfree((struct dao_ctrl_blk *)blk);
972
973 return 0;
974}
975
976static int daio_mgr_enb_dai(void *blk, unsigned int idx)
977{
978 struct daio_mgr_ctrl_blk *ctl = blk;
979
980 if (idx < 4) {
981 /* S/PDIF input */
982 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
983 ctl->dirty.bf.spictl |= (0x1 << idx);
984 } else {
985 /* I2S input */
986 idx %= 4;
987 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
988 ctl->dirty.bf.i2sictl |= (0x1 << idx);
989 }
990 return 0;
991}
992
993static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
994{
995 struct daio_mgr_ctrl_blk *ctl = blk;
996
997 if (idx < 4) {
998 /* S/PDIF input */
999 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
1000 ctl->dirty.bf.spictl |= (0x1 << idx);
1001 } else {
1002 /* I2S input */
1003 idx %= 4;
1004 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
1005 ctl->dirty.bf.i2sictl |= (0x1 << idx);
1006 }
1007 return 0;
1008}
1009
1010static int daio_mgr_enb_dao(void *blk, unsigned int idx)
1011{
1012 struct daio_mgr_ctrl_blk *ctl = blk;
1013
1014 if (idx < 4) {
1015 /* S/PDIF output */
1016 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
1017 ctl->dirty.bf.spoctl |= (0x1 << idx);
1018 } else {
1019 /* I2S output */
1020 idx %= 4;
1021 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
1022 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1023 }
1024 return 0;
1025}
1026
1027static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
1028{
1029 struct daio_mgr_ctrl_blk *ctl = blk;
1030
1031 if (idx < 4) {
1032 /* S/PDIF output */
1033 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
1034 ctl->dirty.bf.spoctl |= (0x1 << idx);
1035 } else {
1036 /* I2S output */
1037 idx %= 4;
1038 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
1039 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1040 }
1041 return 0;
1042}
1043
1044static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
1045{
1046 struct daio_mgr_ctrl_blk *ctl = blk;
1047
1048 if (idx < 4) {
1049 /* S/PDIF output */
1050 switch ((conf & 0x7)) {
1051 case 0:
1052 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
1053 break; /* CDIF */
1054 case 1:
1055 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
1056 break;
1057 case 2:
1058 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
1059 break;
1060 case 4:
1061 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
1062 break;
1063 default:
1064 break;
1065 }
1066 set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
1067 (conf >> 4) & 0x1); /* Non-audio */
1068 set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
1069 (conf >> 4) & 0x1); /* Non-audio */
1070 set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
1071 ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */
1072
1073 ctl->dirty.bf.spoctl |= (0x1 << idx);
1074 } else {
1075 /* I2S output */
1076 /*idx %= 4; */
1077 }
1078 return 0;
1079}
1080
1081static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1082{
1083 struct daio_mgr_ctrl_blk *ctl = blk;
1084
1085 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1086 ctl->dirty.bf.daoimap = 1;
1087 return 0;
1088}
1089
1090static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1091{
1092 struct daio_mgr_ctrl_blk *ctl = blk;
1093
1094 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1095 ctl->dirty.bf.daoimap = 1;
1096 return 0;
1097}
1098
1099static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1100{
1101 struct daio_mgr_ctrl_blk *ctl = blk;
1102
1103 ctl->daoimap.idx = addr;
1104 ctl->dirty.bf.daoimap = 1;
1105 return 0;
1106}
1107
1108static int daio_mgr_commit_write(struct hw *hw, void *blk)
1109{
1110 struct daio_mgr_ctrl_blk *ctl = blk;
1111 int i = 0;
1112
1113 if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
1114 for (i = 0; i < 4; i++) {
1115 if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
1116 ctl->dirty.bf.i2sictl &= ~(0x1 << i);
1117
1118 if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
1119 ctl->dirty.bf.i2soctl &= ~(0x1 << i);
1120 }
1121 hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
1122 mdelay(1);
1123 }
1124 if (ctl->dirty.bf.spoctl) {
1125 for (i = 0; i < 4; i++) {
1126 if ((ctl->dirty.bf.spoctl & (0x1 << i)))
1127 ctl->dirty.bf.spoctl &= ~(0x1 << i);
1128 }
1129 hw_write_20kx(hw, SPOCTL, ctl->spoctl);
1130 mdelay(1);
1131 }
1132 if (ctl->dirty.bf.spictl) {
1133 for (i = 0; i < 4; i++) {
1134 if ((ctl->dirty.bf.spictl & (0x1 << i)))
1135 ctl->dirty.bf.spictl &= ~(0x1 << i);
1136 }
1137 hw_write_20kx(hw, SPICTL, ctl->spictl);
1138 mdelay(1);
1139 }
1140 if (ctl->dirty.bf.daoimap) {
1141 hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
1142 ctl->daoimap.aim);
1143 ctl->dirty.bf.daoimap = 0;
1144 }
1145
1146 return 0;
1147}
1148
1149static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1150{
1151 struct daio_mgr_ctrl_blk *blk;
1152
1153 *rblk = NULL;
1154 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1155 if (NULL == blk)
1156 return -ENOMEM;
1157
1158 blk->i2sctl = hw_read_20kx(hw, I2SCTL);
1159 blk->spoctl = hw_read_20kx(hw, SPOCTL);
1160 blk->spictl = hw_read_20kx(hw, SPICTL);
1161
1162 *rblk = blk;
1163
1164 return 0;
1165}
1166
1167static int daio_mgr_put_ctrl_blk(void *blk)
1168{
1169 kfree((struct daio_mgr_ctrl_blk *)blk);
1170
1171 return 0;
1172}
1173
1174/* Card hardware initialization block */
1175struct dac_conf {
1176 unsigned int msr; /* master sample rate in rsrs */
1177};
1178
1179struct adc_conf {
1180 unsigned int msr; /* master sample rate in rsrs */
1181 unsigned char input; /* the input source of ADC */
1182 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1183};
1184
1185struct daio_conf {
1186 unsigned int msr; /* master sample rate in rsrs */
1187};
1188
1189struct trn_conf {
1190 unsigned long vm_pgt_phys;
1191};
1192
1193static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1194{
1195 u32 i2sorg = 0;
1196 u32 spdorg = 0;
1197
1198 /* Read I2S CTL. Keep original value. */
1199 /*i2sorg = hw_read_20kx(hw, I2SCTL);*/
1200 i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
1201 /* Program I2S with proper master sample rate and enable
1202 * the correct I2S channel. */
1203 i2sorg &= 0xfffffffc;
1204
1205 /* Enable S/PDIF-out-A in fixed 24-bit data
1206 * format and default to 48kHz. */
1207 /* Disable all before doing any changes. */
1208 hw_write_20kx(hw, SPOCTL, 0x0);
1209 spdorg = 0x05;
1210
1211 switch (info->msr) {
1212 case 1:
1213 i2sorg |= 1;
1214 spdorg |= (0x0 << 6);
1215 break;
1216 case 2:
1217 i2sorg |= 2;
1218 spdorg |= (0x1 << 6);
1219 break;
1220 case 4:
1221 i2sorg |= 3;
1222 spdorg |= (0x2 << 6);
1223 break;
1224 default:
1225 i2sorg |= 1;
1226 break;
1227 }
1228
1229 hw_write_20kx(hw, I2SCTL, i2sorg);
1230 hw_write_20kx(hw, SPOCTL, spdorg);
1231
1232 /* Enable S/PDIF-in-A in fixed 24-bit data format. */
1233 /* Disable all before doing any changes. */
1234 hw_write_20kx(hw, SPICTL, 0x0);
1235 mdelay(1);
1236 spdorg = 0x0a0a0a0a;
1237 hw_write_20kx(hw, SPICTL, spdorg);
1238 mdelay(1);
1239
1240 return 0;
1241}
1242
1243/* TRANSPORT operations */
1244static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1245{
1246 u32 trnctl = 0;
1247 unsigned long ptp_phys_low = 0, ptp_phys_high = 0;
1248
1249 /* Set up device page table */
1250 if ((~0UL) == info->vm_pgt_phys) {
1251 printk(KERN_ERR "Wrong device page table page address!\n");
1252 return -1;
1253 }
1254
1255 trnctl = 0x13; /* 32-bit, 4k-size page */
cd391e20
TI		 1256 ptp_phys_low = (u32)info->vm_pgt_phys;
1257 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1258 if (sizeof(void *) == 8) /* 64bit address */
1259 trnctl |= (1 << 2);
1260#if 0 /* Only 4k h/w pages for simplicitiy */
8cc72361
WYC		 1261#if PAGE_SIZE == 8192
1262 trnctl |= (1<<5);
cd391e20 1263#endif
8cc72361
WYC		 1264#endif
1265 hw_write_20kx(hw, PTPALX, ptp_phys_low);
1266 hw_write_20kx(hw, PTPAHX, ptp_phys_high);
1267 hw_write_20kx(hw, TRNCTL, trnctl);
1268 hw_write_20kx(hw, TRNIS, 0x200c01); /* realy needed? */
1269
1270 return 0;
1271}
1272
1273/* Card initialization */
1274#define GCTL_EAC 0x00000001
1275#define GCTL_EAI 0x00000002
1276#define GCTL_BEP 0x00000004
1277#define GCTL_BES 0x00000008
1278#define GCTL_DSP 0x00000010
1279#define GCTL_DBP 0x00000020
1280#define GCTL_ABP 0x00000040
1281#define GCTL_TBP 0x00000080
1282#define GCTL_SBP 0x00000100
1283#define GCTL_FBP 0x00000200
1284#define GCTL_XA 0x00000400
1285#define GCTL_ET 0x00000800
1286#define GCTL_PR 0x00001000
1287#define GCTL_MRL 0x00002000
1288#define GCTL_SDE 0x00004000
1289#define GCTL_SDI 0x00008000
1290#define GCTL_SM 0x00010000
1291#define GCTL_SR 0x00020000
1292#define GCTL_SD 0x00040000
1293#define GCTL_SE 0x00080000
1294#define GCTL_AID 0x00100000
1295
1296static int hw_pll_init(struct hw *hw, unsigned int rsr)
1297{
1298 unsigned int pllctl;
1299 int i = 0;
1300
1301 pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731;
1302 for (i = 0; i < 3; i++) {
1303 if (hw_read_20kx(hw, PLLCTL) == pllctl)
1304 break;
1305
1306 hw_write_20kx(hw, PLLCTL, pllctl);
1307 mdelay(40);
1308 }
1309 if (i >= 3) {
1310 printk(KERN_ALERT "PLL initialization failed!!!\n");
1311 return -EBUSY;
1312 }
1313
1314 return 0;
1315}
1316
1317static int hw_auto_init(struct hw *hw)
1318{
1319 unsigned int gctl;
1320 int i;
1321
1322 gctl = hw_read_20kx(hw, GCTL);
1323 set_field(&gctl, GCTL_EAI, 0);
1324 hw_write_20kx(hw, GCTL, gctl);
1325 set_field(&gctl, GCTL_EAI, 1);
1326 hw_write_20kx(hw, GCTL, gctl);
1327 mdelay(10);
1328 for (i = 0; i < 400000; i++) {
1329 gctl = hw_read_20kx(hw, GCTL);
1330 if (get_field(gctl, GCTL_AID))
1331 break;
1332 }
1333 if (!get_field(gctl, GCTL_AID)) {
1334 printk(KERN_ALERT "Card Auto-init failed!!!\n");
1335 return -EBUSY;
1336 }
1337
1338 return 0;
1339}
1340
1341static int i2c_unlock(struct hw *hw)
1342{
1343 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1344 return 0;
1345
1346 hw_write_pci(hw, 0xcc, 0x8c);
1347 hw_write_pci(hw, 0xcc, 0x0e);
1348 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1349 return 0;
1350
1351 hw_write_pci(hw, 0xcc, 0xee);
1352 hw_write_pci(hw, 0xcc, 0xaa);
1353 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1354 return 0;
1355
1356 return -1;
1357}
1358
1359static void i2c_lock(struct hw *hw)
1360{
1361 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1362 hw_write_pci(hw, 0xcc, 0x00);
1363}
1364
1365static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data)
1366{
1367 unsigned int ret = 0;
1368
1369 do {
1370 ret = hw_read_pci(hw, 0xEC);
1371 } while (!(ret & 0x800000));
1372 hw_write_pci(hw, 0xE0, device);
1373 hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff));
1374}
1375
1376/* DAC operations */
1377
1378static int hw_reset_dac(struct hw *hw)
1379{
1380 u32 i = 0;
1381 u16 gpioorg = 0;
1382 unsigned int ret = 0;
1383
1384 if (i2c_unlock(hw))
1385 return -1;
1386
1387 do {
1388 ret = hw_read_pci(hw, 0xEC);
1389 } while (!(ret & 0x800000));
1390 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1391
1392 /* To be effective, need to reset the DAC twice. */
1393 for (i = 0; i < 2; i++) {
1394 /* set gpio */
1395 mdelay(100);
1396 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1397 gpioorg &= 0xfffd;
1398 hw_write_20kx(hw, GPIO, gpioorg);
1399 mdelay(1);
1400 hw_write_20kx(hw, GPIO, gpioorg | 0x2);
1401 }
1402
1403 i2c_write(hw, 0x00180080, 0x01, 0x80);
1404 i2c_write(hw, 0x00180080, 0x02, 0x10);
1405
1406 i2c_lock(hw);
1407
1408 return 0;
1409}
1410
1411static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1412{
1413 u32 data = 0;
1414 u16 gpioorg = 0;
1415 u16 subsys_id = 0;
1416 unsigned int ret = 0;
1417
1418 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
1419 if ((subsys_id == 0x0022) || (subsys_id == 0x002F)) {
1420 /* SB055x, unmute outputs */
1421 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1422 gpioorg &= 0xffbf; /* set GPIO6 to low */
1423 gpioorg |= 2; /* set GPIO1 to high */
1424 hw_write_20kx(hw, GPIO, gpioorg);
1425 return 0;
1426 }
1427
1428 /* mute outputs */
1429 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1430 gpioorg &= 0xffbf;
1431 hw_write_20kx(hw, GPIO, gpioorg);
1432
1433 hw_reset_dac(hw);
1434
1435 if (i2c_unlock(hw))
1436 return -1;
1437
1438 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1439 do {
1440 ret = hw_read_pci(hw, 0xEC);
1441 } while (!(ret & 0x800000));
1442
1443 switch (info->msr) {
1444 case 1:
1445 data = 0x24;
1446 break;
1447 case 2:
1448 data = 0x25;
1449 break;
1450 case 4:
1451 data = 0x26;
1452 break;
1453 default:
1454 data = 0x24;
1455 break;
1456 }
1457
1458 i2c_write(hw, 0x00180080, 0x06, data);
1459 i2c_write(hw, 0x00180080, 0x09, data);
1460 i2c_write(hw, 0x00180080, 0x0c, data);
1461 i2c_write(hw, 0x00180080, 0x0f, data);
1462
1463 i2c_lock(hw);
1464
1465 /* unmute outputs */
1466 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1467 gpioorg = gpioorg | 0x40;
1468 hw_write_20kx(hw, GPIO, gpioorg);
1469
1470 return 0;
1471}
1472
1473/* ADC operations */
1474
1475static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type)
1476{
1477 u32 data = 0;
1478 return data;
1479}
1480
1481static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type)
1482{
1483 u32 data = 0;
1484
1485 data = hw_read_20kx(hw, GPIO);
1486 switch (type) {
1487 case ADC_MICIN:
1488 data = ((data & (0x1<<7)) && (data & (0x1<<8)));
1489 break;
1490 case ADC_LINEIN:
1491 data = (!(data & (0x1<<7)) && (data & (0x1<<8)));
1492 break;
1493 case ADC_NONE: /* Digital I/O */
1494 data = (!(data & (0x1<<8)));
1495 break;
1496 default:
1497 data = 0;
1498 }
1499 return data;
1500}
1501
1502static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type)
1503{
1504 u32 data = 0;
1505
1506 data = hw_read_20kx(hw, GPIO);
1507 switch (type) {
1508 case ADC_MICIN:
1509 data = (data & (0x1 << 7)) ? 1 : 0;
1510 break;
1511 case ADC_LINEIN:
1512 data = (data & (0x1 << 7)) ? 0 : 1;
1513 break;
1514 default:
1515 data = 0;
1516 }
1517 return data;
1518}
1519
1520static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1521{
1522 u16 subsys_id = 0;
1523
1524 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
1525 if ((subsys_id == 0x0022) || (subsys_id == 0x002F)) {
1526 /* SB055x cards */
1527 return is_adc_input_selected_SB055x(hw, type);
1528 } else if ((subsys_id == 0x0029) || (subsys_id == 0x0031)) {
1529 /* SB073x cards */
1530 return is_adc_input_selected_hendrix(hw, type);
1531 } else if ((subsys_id & 0xf000) == 0x6000) {
1532 /* Vista compatible cards */
1533 return is_adc_input_selected_hendrix(hw, type);
1534 } else {
1535 return is_adc_input_selected_SBx(hw, type);
1536 }
1537}
1538
1539static int
1540adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost)
1541{
1542 u32 data = 0;
1543
1544 /*
1545 * check and set the following GPIO bits accordingly
1546 * ADC_Gain = GPIO2
1547 * DRM_off = GPIO3
1548 * Mic_Pwr_on = GPIO7
1549 * Digital_IO_Sel = GPIO8
1550 * Mic_Sw = GPIO9
1551 * Aux/MicLine_Sw = GPIO12
1552 */
1553 data = hw_read_20kx(hw, GPIO);
1554 data &= 0xec73;
1555 switch (type) {
1556 case ADC_MICIN:
1557 data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ;
1558 data |= boost ? (0x1<<2) : 0;
1559 break;
1560 case ADC_LINEIN:
1561 data |= (0x1<<8);
1562 break;
1563 case ADC_AUX:
1564 data |= (0x1<<8) | (0x1<<12);
1565 break;
1566 case ADC_NONE:
1567 data |= (0x1<<12); /* set to digital */
1568 break;
1569 default:
1570 return -1;
1571 }
1572
1573 hw_write_20kx(hw, GPIO, data);
1574
1575 return 0;
1576}
1577
1578
1579static int
1580adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost)
1581{
1582 u32 data = 0;
1583 u32 i2c_data = 0;
1584 unsigned int ret = 0;
1585
1586 if (i2c_unlock(hw))
1587 return -1;
1588
1589 do {
1590 ret = hw_read_pci(hw, 0xEC);
1591 } while (!(ret & 0x800000)); /* i2c ready poll */
1592 /* set i2c access mode as Direct Control */
1593 hw_write_pci(hw, 0xEC, 0x05);
1594
1595 data = hw_read_20kx(hw, GPIO);
1596 switch (type) {
1597 case ADC_MICIN:
1598 data |= ((0x1 << 7) | (0x1 << 8));
1599 i2c_data = 0x1; /* Mic-in */
1600 break;
1601 case ADC_LINEIN:
1602 data &= ~(0x1 << 7);
1603 data |= (0x1 << 8);
1604 i2c_data = 0x2; /* Line-in */
1605 break;
1606 case ADC_NONE:
1607 data &= ~(0x1 << 8);
1608 i2c_data = 0x0; /* set to Digital */
1609 break;
1610 default:
1611 i2c_lock(hw);
1612 return -1;
1613 }
1614 hw_write_20kx(hw, GPIO, data);
1615 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1616 if (boost) {
1617 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1618 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1619 } else {
1620 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1621 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1622 }
1623
1624 i2c_lock(hw);
1625
1626 return 0;
1627}
1628
1629static int
1630adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost)
1631{
1632 u32 data = 0;
1633 u32 i2c_data = 0;
1634 unsigned int ret = 0;
1635
1636 if (i2c_unlock(hw))
1637 return -1;
1638
1639 do {
1640 ret = hw_read_pci(hw, 0xEC);
1641 } while (!(ret & 0x800000)); /* i2c ready poll */
1642 /* set i2c access mode as Direct Control */
1643 hw_write_pci(hw, 0xEC, 0x05);
1644
1645 data = hw_read_20kx(hw, GPIO);
1646 switch (type) {
1647 case ADC_MICIN:
1648 data |= (0x1 << 7);
1649 i2c_data = 0x1; /* Mic-in */
1650 break;
1651 case ADC_LINEIN:
1652 data &= ~(0x1 << 7);
1653 i2c_data = 0x2; /* Line-in */
1654 break;
1655 default:
1656 i2c_lock(hw);
1657 return -1;
1658 }
1659 hw_write_20kx(hw, GPIO, data);
1660 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1661 if (boost) {
1662 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1663 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1664 } else {
1665 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1666 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1667 }
1668
1669 i2c_lock(hw);
1670
1671 return 0;
1672}
1673
1674static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1675{
1676 u16 subsys_id = 0;
1677
1678 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
1679 if ((subsys_id == 0x0022) || (subsys_id == 0x002F)) {
1680 /* SB055x cards */
1681 return adc_input_select_SB055x(hw, type, (ADC_MICIN == type));
1682 } else if ((subsys_id == 0x0029) || (subsys_id == 0x0031)) {
1683 /* SB073x cards */
1684 return adc_input_select_hendrix(hw, type, (ADC_MICIN == type));
1685 } else if ((subsys_id & 0xf000) == 0x6000) {
1686 /* Vista compatible cards */
1687 return adc_input_select_hendrix(hw, type, (ADC_MICIN == type));
1688 } else {
1689 return adc_input_select_SBx(hw, type, (ADC_MICIN == type));
1690 }
1691}
1692
1693static int adc_init_SB055x(struct hw *hw, int input, int mic20db)
1694{
1695 return adc_input_select_SB055x(hw, input, mic20db);
1696}
1697
1698static int adc_init_SBx(struct hw *hw, int input, int mic20db)
1699{
1700 u16 gpioorg;
1701 u16 input_source;
1702 u32 adcdata = 0;
1703 unsigned int ret = 0;
1704
1705 input_source = 0x100; /* default to analog */
1706 switch (input) {
1707 case ADC_MICIN:
1708 adcdata = 0x1;
1709 input_source = 0x180; /* set GPIO7 to select Mic */
1710 break;
1711 case ADC_LINEIN:
1712 adcdata = 0x2;
1713 break;
1714 case ADC_VIDEO:
1715 adcdata = 0x4;
1716 break;
1717 case ADC_AUX:
1718 adcdata = 0x8;
1719 break;
1720 case ADC_NONE:
1721 adcdata = 0x0;
1722 input_source = 0x0; /* set to Digital */
1723 break;
1724 default:
1725 break;
1726 }
1727
1728 if (i2c_unlock(hw))
1729 return -1;
1730
1731 do {
1732 ret = hw_read_pci(hw, 0xEC);
1733 } while (!(ret & 0x800000)); /* i2c ready poll */
1734 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1735
1736 i2c_write(hw, 0x001a0080, 0x0e, 0x08);
1737 i2c_write(hw, 0x001a0080, 0x18, 0x0a);
1738 i2c_write(hw, 0x001a0080, 0x28, 0x86);
1739 i2c_write(hw, 0x001a0080, 0x2a, adcdata);
1740
1741 if (mic20db) {
1742 i2c_write(hw, 0x001a0080, 0x1c, 0xf7);
1743 i2c_write(hw, 0x001a0080, 0x1e, 0xf7);
1744 } else {
1745 i2c_write(hw, 0x001a0080, 0x1c, 0xcf);
1746 i2c_write(hw, 0x001a0080, 0x1e, 0xcf);
1747 }
1748
1749 if (!(hw_read_20kx(hw, ID0) & 0x100))
1750 i2c_write(hw, 0x001a0080, 0x16, 0x26);
1751
1752 i2c_lock(hw);
1753
1754 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1755 gpioorg &= 0xfe7f;
1756 gpioorg |= input_source;
1757 hw_write_20kx(hw, GPIO, gpioorg);
1758
1759 return 0;
1760}
1761
1762static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1763{
1764 int err = 0;
1765 u16 subsys_id = 0;
1766
1767 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
1768 if ((subsys_id == 0x0022) || (subsys_id == 0x002F)) {
1769 /* Sb055x card */
1770 err = adc_init_SB055x(hw, info->input, info->mic20db);
1771 } else {
1772 err = adc_init_SBx(hw, info->input, info->mic20db);
1773 }
1774
1775 return err;
1776}
1777
1778static int hw_have_digit_io_switch(struct hw *hw)
1779{
1780 u16 subsys_id = 0;
1781
1782 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
1783 /* SB073x and Vista compatible cards have no digit IO switch */
1784 return !((subsys_id == 0x0029) || (subsys_id == 0x0031)
1785 || ((subsys_id & 0xf000) == 0x6000));
1786}
1787
1788#define UAA_CFG_PWRSTATUS 0x44
1789#define UAA_CFG_SPACE_FLAG 0xA0
1790#define UAA_CORE_CHANGE 0x3FFC
1791static int uaa_to_xfi(struct pci_dev *pci)
1792{
1793 unsigned int bar0, bar1, bar2, bar3, bar4, bar5;
1794 unsigned int cmd, irq, cl_size, l_timer, pwr;
1795 unsigned int CTLA, CTLZ, CTLL, CTLX, CTL_, CTLF, CTLi;
1796 unsigned int is_uaa = 0;
1797 unsigned int data[4] = {0};
1798 unsigned int io_base;
1799 void *mem_base;
1800 int i = 0;
1801
1802 /* By default, Hendrix card UAA Bar0 should be using memory... */
1803 io_base = pci_resource_start(pci, 0);
1804 mem_base = ioremap(io_base, pci_resource_len(pci, 0));
1805 if (NULL == mem_base)
1806 return -ENOENT;
1807
1808 CTLX = ___constant_swab32(*((unsigned int *)"CTLX"));
1809 CTL_ = ___constant_swab32(*((unsigned int *)"CTL-"));
1810 CTLF = ___constant_swab32(*((unsigned int *)"CTLF"));
1811 CTLi = ___constant_swab32(*((unsigned int *)"CTLi"));
1812 CTLA = ___constant_swab32(*((unsigned int *)"CTLA"));
1813 CTLZ = ___constant_swab32(*((unsigned int *)"CTLZ"));
1814 CTLL = ___constant_swab32(*((unsigned int *)"CTLL"));
1815
1816 /* Read current mode from Mode Change Register */
1817 for (i = 0; i < 4; i++)
1818 data[i] = readl(mem_base + UAA_CORE_CHANGE);
1819
1820 /* Determine current mode... */
1821 if (data[0] == CTLA) {
1822 is_uaa = ((data[1] == CTLZ && data[2] == CTLL
1823 && data[3] == CTLA) || (data[1] == CTLA
1824 && data[2] == CTLZ && data[3] == CTLL));
1825 } else if (data[0] == CTLZ) {
1826 is_uaa = (data[1] == CTLL
1827 && data[2] == CTLA && data[3] == CTLA);
1828 } else if (data[0] == CTLL) {
1829 is_uaa = (data[1] == CTLA
1830 && data[2] == CTLA && data[3] == CTLZ);
1831 } else {
1832 is_uaa = 0;
1833 }
1834
1835 if (!is_uaa) {
1836 /* Not in UAA mode currently. Return directly. */
1837 iounmap(mem_base);
1838 return 0;
1839 }
1840
1841 pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
1842 pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);
1843 pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
1844 pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);
1845 pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);
1846 pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);
1847 pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
1848 pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
1849 pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
1850 pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);
1851 pci_read_config_dword(pci, PCI_COMMAND, &cmd);
1852
1853 /* Set up X-Fi core PCI configuration space. */
1854 /* Switch to X-Fi config space with BAR0 exposed. */
1855 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);
1856 /* Copy UAA's BAR5 into X-Fi BAR0 */
1857 pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);
1858 /* Switch to X-Fi config space without BAR0 exposed. */
1859 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);
1860 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);
1861 pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);
1862 pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);
1863 pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);
1864 pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);
1865 pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);
1866 pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
1867 pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);
1868 pci_write_config_dword(pci, PCI_COMMAND, cmd);
1869
1870 /* Switch to X-Fi mode */
1871 writel(CTLX, (mem_base + UAA_CORE_CHANGE));
1872 writel(CTL_, (mem_base + UAA_CORE_CHANGE));
1873 writel(CTLF, (mem_base + UAA_CORE_CHANGE));
1874 writel(CTLi, (mem_base + UAA_CORE_CHANGE));
1875
1876 iounmap(mem_base);
1877
1878 return 0;
1879}
1880
1881static int hw_card_start(struct hw *hw)
1882{
1883 int err = 0;
1884 struct pci_dev *pci = hw->pci;
1885 u16 subsys_id = 0;
1886 unsigned int dma_mask = 0;
1887
1888 err = pci_enable_device(pci);
1889 if (err < 0)
1890 return err;
1891
1892 /* Set DMA transfer mask */
1893 dma_mask = CT_XFI_DMA_MASK;
1894 if (pci_set_dma_mask(pci, dma_mask) < 0 ||
1895 pci_set_consistent_dma_mask(pci, dma_mask) < 0) {
1896 printk(KERN_ERR "architecture does not support PCI "
1897 "busmaster DMA with mask 0x%x\n", dma_mask);
1898 err = -ENXIO;
1899 goto error1;
1900 }
1901
1902 err = pci_request_regions(pci, "XFi");
1903 if (err < 0)
1904 goto error1;
1905
1906 /* Switch to X-Fi mode from UAA mode if neeeded */
1907 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &subsys_id);
1908 if ((0x5 == pci->device) && (0x6000 == (subsys_id & 0x6000))) {
1909 err = uaa_to_xfi(pci);
1910 if (err)
1911 goto error2;
1912
1913 hw->io_base = pci_resource_start(pci, 5);
1914 } else {
1915 hw->io_base = pci_resource_start(pci, 0);
1916 }
1917
1918 /*if ((err = request_irq(pci->irq, ct_atc_interrupt, IRQF_SHARED,
1919 atc->chip_details->nm_card, hw))) {
1920 goto error2;
1921 }
1922 hw->irq = pci->irq;
1923 */
1924
1925 pci_set_master(pci);
1926
1927 return 0;
1928
1929error2:
1930 pci_release_regions(pci);
1931 hw->io_base = 0;
1932error1:
1933 pci_disable_device(pci);
1934 return err;
1935}
1936
1937static int hw_card_stop(struct hw *hw)
1938{
1939 /* TODO: Disable interrupt and so on... */
1940 return 0;
1941}
1942
1943static int hw_card_shutdown(struct hw *hw)
1944{
1945 if (hw->irq >= 0)
1946 free_irq(hw->irq, hw);
1947
1948 hw->irq = -1;
1949
1950 if (NULL != ((void *)hw->mem_base))
1951 iounmap((void *)hw->mem_base);
1952
1953 hw->mem_base = (unsigned long)NULL;
1954
1955 if (hw->io_base)
1956 pci_release_regions(hw->pci);
1957
1958 hw->io_base = 0;
1959
1960 pci_disable_device(hw->pci);
1961
1962 return 0;
1963}
1964
1965static int hw_card_init(struct hw *hw, struct card_conf *info)
1966{
1967 int err;
1968 unsigned int gctl;
1969 u16 subsys_id = 0;
1970 u32 data = 0;
1971 struct dac_conf dac_info = {0};
1972 struct adc_conf adc_info = {0};
1973 struct daio_conf daio_info = {0};
1974 struct trn_conf trn_info = {0};
1975
1976 /* Get PCI io port base address and do Hendrix switch if needed. */
1977 if (!hw->io_base) {
1978 err = hw_card_start(hw);
1979 if (err)
1980 return err;
1981 }
1982
1983 /* PLL init */
1984 err = hw_pll_init(hw, info->rsr);
1985 if (err < 0)
1986 return err;
1987
1988 /* kick off auto-init */
1989 err = hw_auto_init(hw);
1990 if (err < 0)
1991 return err;
1992
1993 /* Enable audio ring */
1994 gctl = hw_read_20kx(hw, GCTL);
1995 set_field(&gctl, GCTL_EAC, 1);
1996 set_field(&gctl, GCTL_DBP, 1);
1997 set_field(&gctl, GCTL_TBP, 1);
1998 set_field(&gctl, GCTL_FBP, 1);
1999 set_field(&gctl, GCTL_ET, 1);
2000 hw_write_20kx(hw, GCTL, gctl);
2001 mdelay(10);
2002
2003 /* Reset all global pending interrupts */
2004 hw_write_20kx(hw, GIE, 0);
2005 /* Reset all SRC pending interrupts */
2006 hw_write_20kx(hw, SRCIP, 0);
2007 mdelay(30);
2008
2009 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
2010 /* Detect the card ID and configure GPIO accordingly. */
2011 if ((subsys_id == 0x0022) || (subsys_id == 0x002F)) {
2012 /* SB055x cards */
2013 hw_write_20kx(hw, GPIOCTL, 0x13fe);
2014 } else if ((subsys_id == 0x0029) || (subsys_id == 0x0031)) {
2015 /* SB073x cards */
2016 hw_write_20kx(hw, GPIOCTL, 0x00e6);
2017 } else if ((subsys_id & 0xf000) == 0x6000) {
2018 /* Vista compatible cards */
2019 hw_write_20kx(hw, GPIOCTL, 0x00c2);
2020 } else {
2021 hw_write_20kx(hw, GPIOCTL, 0x01e6);
2022 }
2023
2024 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2025 err = hw_trn_init(hw, &trn_info);
2026 if (err < 0)
2027 return err;
2028
2029 daio_info.msr = info->msr;
2030 err = hw_daio_init(hw, &daio_info);
2031 if (err < 0)
2032 return err;
2033
2034 dac_info.msr = info->msr;
2035 err = hw_dac_init(hw, &dac_info);
2036 if (err < 0)
2037 return err;
2038
2039 adc_info.msr = info->msr;
2040 adc_info.input = ADC_LINEIN;
2041 adc_info.mic20db = 0;
2042 err = hw_adc_init(hw, &adc_info);
2043 if (err < 0)
2044 return err;
2045
2046 data = hw_read_20kx(hw, SRCMCTL);
2047 data |= 0x1; /* Enables input from the audio ring */
2048 hw_write_20kx(hw, SRCMCTL, data);
2049
2050 return 0;
2051}
2052
2053static u32 hw_read_20kx(struct hw *hw, u32 reg)
2054{
2055 u32 value;
2056 unsigned long flags;
2057
2058 spin_lock_irqsave(
2059 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2060 outl(reg, hw->io_base + 0x0);
2061 value = inl(hw->io_base + 0x4);
2062 spin_unlock_irqrestore(
2063 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2064
2065 return value;
2066}
2067
2068static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2069{
2070 unsigned long flags;
2071
2072 spin_lock_irqsave(
2073 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2074 outl(reg, hw->io_base + 0x0);
2075 outl(data, hw->io_base + 0x4);
2076 spin_unlock_irqrestore(
2077 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2078
2079}
2080
2081static u32 hw_read_pci(struct hw *hw, u32 reg)
2082{
2083 u32 value;
2084 unsigned long flags;
2085
2086 spin_lock_irqsave(
2087 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2088 outl(reg, hw->io_base + 0x10);
2089 value = inl(hw->io_base + 0x14);
2090 spin_unlock_irqrestore(
2091 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2092
2093 return value;
2094}
2095
2096static void hw_write_pci(struct hw *hw, u32 reg, u32 data)
2097{
2098 unsigned long flags;
2099
2100 spin_lock_irqsave(
2101 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2102 outl(reg, hw->io_base + 0x10);
2103 outl(data, hw->io_base + 0x14);
2104 spin_unlock_irqrestore(
2105 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2106}
2107
2108int create_20k1_hw_obj(struct hw **rhw)
2109{
2110 struct hw *hw;
2111 struct hw20k1 *hw20k1;
2112
2113 *rhw = NULL;
2114 hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL);
2115 if (NULL == hw20k1)
2116 return -ENOMEM;
2117
2118 spin_lock_init(&hw20k1->reg_20k1_lock);
2119 spin_lock_init(&hw20k1->reg_pci_lock);
2120
2121 hw = &hw20k1->hw;
2122
2123 hw->io_base = 0;
2124 hw->mem_base = (unsigned long)NULL;
2125 hw->irq = -1;
2126
2127 hw->card_init = hw_card_init;
2128 hw->card_stop = hw_card_stop;
2129 hw->pll_init = hw_pll_init;
2130 hw->is_adc_source_selected = hw_is_adc_input_selected;
2131 hw->select_adc_source = hw_adc_input_select;
2132 hw->have_digit_io_switch = hw_have_digit_io_switch;
2133
2134 hw->src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk;
2135 hw->src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk;
2136 hw->src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk;
2137 hw->src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk;
2138 hw->src_set_state = src_set_state;
2139 hw->src_set_bm = src_set_bm;
2140 hw->src_set_rsr = src_set_rsr;
2141 hw->src_set_sf = src_set_sf;
2142 hw->src_set_wr = src_set_wr;
2143 hw->src_set_pm = src_set_pm;
2144 hw->src_set_rom = src_set_rom;
2145 hw->src_set_vo = src_set_vo;
2146 hw->src_set_st = src_set_st;
2147 hw->src_set_ie = src_set_ie;
2148 hw->src_set_ilsz = src_set_ilsz;
2149 hw->src_set_bp = src_set_bp;
2150 hw->src_set_cisz = src_set_cisz;
2151 hw->src_set_ca = src_set_ca;
2152 hw->src_set_sa = src_set_sa;
2153 hw->src_set_la = src_set_la;
2154 hw->src_set_pitch = src_set_pitch;
2155 hw->src_set_dirty = src_set_dirty;
2156 hw->src_set_clear_zbufs = src_set_clear_zbufs;
2157 hw->src_set_dirty_all = src_set_dirty_all;
2158 hw->src_commit_write = src_commit_write;
2159 hw->src_get_ca = src_get_ca;
2160 hw->src_get_dirty = src_get_dirty;
2161 hw->src_dirty_conj_mask = src_dirty_conj_mask;
2162 hw->src_mgr_enbs_src = src_mgr_enbs_src;
2163 hw->src_mgr_enb_src = src_mgr_enb_src;
2164 hw->src_mgr_dsb_src = src_mgr_dsb_src;
2165 hw->src_mgr_commit_write = src_mgr_commit_write;
2166
2167 hw->srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk;
2168 hw->srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk;
2169 hw->srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc;
2170 hw->srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser;
2171 hw->srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt;
2172 hw->srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr;
2173 hw->srcimp_mgr_commit_write = srcimp_mgr_commit_write;
2174
2175 hw->amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk;
2176 hw->amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk;
2177 hw->amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk;
2178 hw->amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk;
2179 hw->amixer_set_mode = amixer_set_mode;
2180 hw->amixer_set_iv = amixer_set_iv;
2181 hw->amixer_set_x = amixer_set_x;
2182 hw->amixer_set_y = amixer_set_y;
2183 hw->amixer_set_sadr = amixer_set_sadr;
2184 hw->amixer_set_se = amixer_set_se;
2185 hw->amixer_set_dirty = amixer_set_dirty;
2186 hw->amixer_set_dirty_all = amixer_set_dirty_all;
2187 hw->amixer_commit_write = amixer_commit_write;
2188 hw->amixer_get_y = amixer_get_y;
2189 hw->amixer_get_dirty = amixer_get_dirty;
2190
2191 hw->dai_get_ctrl_blk = dai_get_ctrl_blk;
2192 hw->dai_put_ctrl_blk = dai_put_ctrl_blk;
2193 hw->dai_srt_set_srco = dai_srt_set_srcr;
2194 hw->dai_srt_set_srcm = dai_srt_set_srcl;
2195 hw->dai_srt_set_rsr = dai_srt_set_rsr;
2196 hw->dai_srt_set_drat = dai_srt_set_drat;
2197 hw->dai_srt_set_ec = dai_srt_set_ec;
2198 hw->dai_srt_set_et = dai_srt_set_et;
2199 hw->dai_commit_write = dai_commit_write;
2200
2201 hw->dao_get_ctrl_blk = dao_get_ctrl_blk;
2202 hw->dao_put_ctrl_blk = dao_put_ctrl_blk;
2203 hw->dao_set_spos = dao_set_spos;
2204 hw->dao_commit_write = dao_commit_write;
2205 hw->dao_get_spos = dao_get_spos;
2206
2207 hw->daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk;
2208 hw->daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk;
2209 hw->daio_mgr_enb_dai = daio_mgr_enb_dai;
2210 hw->daio_mgr_dsb_dai = daio_mgr_dsb_dai;
2211 hw->daio_mgr_enb_dao = daio_mgr_enb_dao;
2212 hw->daio_mgr_dsb_dao = daio_mgr_dsb_dao;
2213 hw->daio_mgr_dao_init = daio_mgr_dao_init;
2214 hw->daio_mgr_set_imaparc = daio_mgr_set_imaparc;
2215 hw->daio_mgr_set_imapnxt = daio_mgr_set_imapnxt;
2216 hw->daio_mgr_set_imapaddr = daio_mgr_set_imapaddr;
2217 hw->daio_mgr_commit_write = daio_mgr_commit_write;
2218
2219 *rhw = hw;
2220
2221 return 0;
2222}
2223
2224int destroy_20k1_hw_obj(struct hw *hw)
2225{
2226 if (hw->io_base)
2227 hw_card_shutdown(hw);
2228
2229 kfree(container_of(hw, struct hw20k1, hw));
2230 return 0;
2231}
kernel source for telekom puls (alcatel/mediatek)