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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / ad1889.c
CommitLineData
12bb5b78
CL		 1/* Analog Devices 1889 audio driver
2 *
3 * This is a driver for the AD1889 PCI audio chipset found
4 * on the HP PA-RISC [BCJ]-xxx0 workstations.
5 *
6 * Copyright (C) 2004-2005, Kyle McMartin <kyle@parisc-linux.org>
7 * Copyright (C) 2005, Thibaut Varene <varenet@parisc-linux.org>
8 * Based on the OSS AD1889 driver by Randolph Chung <tausq@debian.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 * TODO:
24 * Do we need to take care of CCS register?
25 * Maybe we could use finer grained locking (separate locks for pb/cap)?
26 * Wishlist:
27 * Control Interface (mixer) support
28 * Better AC97 support (VSR...)?
29 * PM support
30 * MIDI support
31 * Game Port support
25985edc 32 * SG DMA support (this will need *a lot* of work)
12bb5b78
CL		 33 */
34
35#include <linux/init.h>
36#include <linux/pci.h>
9d2f928d 37#include <linux/dma-mapping.h>
12bb5b78
CL		 38#include <linux/slab.h>
39#include <linux/interrupt.h>
40#include <linux/compiler.h>
41#include <linux/delay.h>
da155d5b 42#include <linux/module.h>
12bb5b78 43
12bb5b78
CL		 44#include <sound/core.h>
45#include <sound/pcm.h>
46#include <sound/initval.h>
47#include <sound/ac97_codec.h>
48
49#include <asm/io.h>
50
51#include "ad1889.h"
52#include "ac97/ac97_id.h"
53
c6f43290 54#define AD1889_DRVVER "Version: 1.7"
12bb5b78
CL		 55
56MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>, Thibaut Varene <t-bone@parisc-linux.org>");
57MODULE_DESCRIPTION("Analog Devices AD1889 ALSA sound driver");
58MODULE_LICENSE("GPL");
59MODULE_SUPPORTED_DEVICE("{{Analog Devices,AD1889}}");
60
61static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
62module_param_array(index, int, NULL, 0444);
63MODULE_PARM_DESC(index, "Index value for the AD1889 soundcard.");
64
65static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
66module_param_array(id, charp, NULL, 0444);
67MODULE_PARM_DESC(id, "ID string for the AD1889 soundcard.");
68
a67ff6a5 69static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
12bb5b78
CL		 70module_param_array(enable, bool, NULL, 0444);
71MODULE_PARM_DESC(enable, "Enable AD1889 soundcard.");
72
73static char *ac97_quirk[SNDRV_CARDS];
74module_param_array(ac97_quirk, charp, NULL, 0444);
75MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
76
77#define DEVNAME "ad1889"
78#define PFX DEVNAME ": "
79
80/* let's use the global sound debug interfaces */
81#define ad1889_debug(fmt, arg...) snd_printd(KERN_DEBUG fmt, ## arg)
82
83/* keep track of some hw registers */
84struct ad1889_register_state {
85 u16 reg; /* reg setup */
86 u32 addr; /* dma base address */
87 unsigned long size; /* DMA buffer size */
88};
89
90struct snd_ad1889 {
02c2de69 91 struct snd_card *card;
12bb5b78
CL		 92 struct pci_dev *pci;
93
94 int irq;
95 unsigned long bar;
96 void __iomem *iobase;
97
02c2de69
TI		 98 struct snd_ac97 *ac97;
99 struct snd_ac97_bus *ac97_bus;
100 struct snd_pcm *pcm;
101 struct snd_info_entry *proc;
12bb5b78 102
02c2de69
TI		 103 struct snd_pcm_substream *psubs;
104 struct snd_pcm_substream *csubs;
12bb5b78
CL		 105
106 /* playback register state */
107 struct ad1889_register_state wave;
108 struct ad1889_register_state ramc;
109
110 spinlock_t lock;
111};
112
113static inline u16
114ad1889_readw(struct snd_ad1889 *chip, unsigned reg)
115{
116 return readw(chip->iobase + reg);
117}
118
119static inline void
120ad1889_writew(struct snd_ad1889 *chip, unsigned reg, u16 val)
121{
122 writew(val, chip->iobase + reg);
123}
124
125static inline u32
126ad1889_readl(struct snd_ad1889 *chip, unsigned reg)
127{
128 return readl(chip->iobase + reg);
129}
130
131static inline void
132ad1889_writel(struct snd_ad1889 *chip, unsigned reg, u32 val)
133{
134 writel(val, chip->iobase + reg);
135}
136
137static inline void
138ad1889_unmute(struct snd_ad1889 *chip)
139{
140 u16 st;
141 st = ad1889_readw(chip, AD_DS_WADA) &
142 ~(AD_DS_WADA_RWAM | AD_DS_WADA_LWAM);
143 ad1889_writew(chip, AD_DS_WADA, st);
144 ad1889_readw(chip, AD_DS_WADA);
145}
146
147static inline void
148ad1889_mute(struct snd_ad1889 *chip)
149{
150 u16 st;
151 st = ad1889_readw(chip, AD_DS_WADA) | AD_DS_WADA_RWAM | AD_DS_WADA_LWAM;
152 ad1889_writew(chip, AD_DS_WADA, st);
153 ad1889_readw(chip, AD_DS_WADA);
154}
155
156static inline void
157ad1889_load_adc_buffer_address(struct snd_ad1889 *chip, u32 address)
158{
159 ad1889_writel(chip, AD_DMA_ADCBA, address);
160 ad1889_writel(chip, AD_DMA_ADCCA, address);
161}
162
163static inline void
164ad1889_load_adc_buffer_count(struct snd_ad1889 *chip, u32 count)
165{
166 ad1889_writel(chip, AD_DMA_ADCBC, count);
167 ad1889_writel(chip, AD_DMA_ADCCC, count);
168}
169
170static inline void
171ad1889_load_adc_interrupt_count(struct snd_ad1889 *chip, u32 count)
172{
173 ad1889_writel(chip, AD_DMA_ADCIB, count);
174 ad1889_writel(chip, AD_DMA_ADCIC, count);
175}
176
177static inline void
178ad1889_load_wave_buffer_address(struct snd_ad1889 *chip, u32 address)
179{
180 ad1889_writel(chip, AD_DMA_WAVBA, address);
181 ad1889_writel(chip, AD_DMA_WAVCA, address);
182}
183
184static inline void
185ad1889_load_wave_buffer_count(struct snd_ad1889 *chip, u32 count)
186{
187 ad1889_writel(chip, AD_DMA_WAVBC, count);
188 ad1889_writel(chip, AD_DMA_WAVCC, count);
189}
190
191static inline void
192ad1889_load_wave_interrupt_count(struct snd_ad1889 *chip, u32 count)
193{
194 ad1889_writel(chip, AD_DMA_WAVIB, count);
195 ad1889_writel(chip, AD_DMA_WAVIC, count);
196}
197
198static void
199ad1889_channel_reset(struct snd_ad1889 *chip, unsigned int channel)
200{
201 u16 reg;
202
203 if (channel & AD_CHAN_WAV) {
204 /* Disable wave channel */
205 reg = ad1889_readw(chip, AD_DS_WSMC) & ~AD_DS_WSMC_WAEN;
206 ad1889_writew(chip, AD_DS_WSMC, reg);
207 chip->wave.reg = reg;
208
209 /* disable IRQs */
210 reg = ad1889_readw(chip, AD_DMA_WAV);
211 reg &= AD_DMA_IM_DIS;
212 reg &= ~AD_DMA_LOOP;
213 ad1889_writew(chip, AD_DMA_WAV, reg);
214
215 /* clear IRQ and address counters and pointers */
216 ad1889_load_wave_buffer_address(chip, 0x0);
217 ad1889_load_wave_buffer_count(chip, 0x0);
218 ad1889_load_wave_interrupt_count(chip, 0x0);
219
220 /* flush */
221 ad1889_readw(chip, AD_DMA_WAV);
222 }
223
224 if (channel & AD_CHAN_ADC) {
225 /* Disable ADC channel */
226 reg = ad1889_readw(chip, AD_DS_RAMC) & ~AD_DS_RAMC_ADEN;
227 ad1889_writew(chip, AD_DS_RAMC, reg);
228 chip->ramc.reg = reg;
229
230 reg = ad1889_readw(chip, AD_DMA_ADC);
231 reg &= AD_DMA_IM_DIS;
232 reg &= ~AD_DMA_LOOP;
233 ad1889_writew(chip, AD_DMA_ADC, reg);
234
235 ad1889_load_adc_buffer_address(chip, 0x0);
236 ad1889_load_adc_buffer_count(chip, 0x0);
237 ad1889_load_adc_interrupt_count(chip, 0x0);
238
239 /* flush */
240 ad1889_readw(chip, AD_DMA_ADC);
241 }
242}
243
f40b6890 244static u16
02c2de69 245snd_ad1889_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
12bb5b78
CL		 246{
247 struct snd_ad1889 *chip = ac97->private_data;
248 return ad1889_readw(chip, AD_AC97_BASE + reg);
249}
250
f40b6890 251static void
02c2de69 252snd_ad1889_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
12bb5b78
CL		 253{
254 struct snd_ad1889 *chip = ac97->private_data;
255 ad1889_writew(chip, AD_AC97_BASE + reg, val);
256}
257
258static int
259snd_ad1889_ac97_ready(struct snd_ad1889 *chip)
260{
261 int retry = 400; /* average needs 352 msec */
262
263 while (!(ad1889_readw(chip, AD_AC97_ACIC) & AD_AC97_ACIC_ACRDY)
264 && --retry)
265 mdelay(1);
266 if (!retry) {
267 snd_printk(KERN_ERR PFX "[%s] Link is not ready.\n",
9bf8e7dd 268 __func__);
12bb5b78
CL		 269 return -EIO;
270 }
9bf8e7dd 271 ad1889_debug("[%s] ready after %d ms\n", __func__, 400 - retry);
12bb5b78
CL		 272
273 return 0;
274}
275
276static int
02c2de69
TI		 277snd_ad1889_hw_params(struct snd_pcm_substream *substream,
278 struct snd_pcm_hw_params *hw_params)
12bb5b78
CL		 279{
280 return snd_pcm_lib_malloc_pages(substream,
281 params_buffer_bytes(hw_params));
282}
283
284static int
02c2de69 285snd_ad1889_hw_free(struct snd_pcm_substream *substream)
12bb5b78
CL		 286{
287 return snd_pcm_lib_free_pages(substream);
288}
289
02c2de69 290static struct snd_pcm_hardware snd_ad1889_playback_hw = {
12bb5b78
CL		 291 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
292 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER,
293 .formats = SNDRV_PCM_FMTBIT_S16_LE,
294 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
295 .rate_min = 8000, /* docs say 7000, but we're lazy */
296 .rate_max = 48000,
297 .channels_min = 1,
298 .channels_max = 2,
299 .buffer_bytes_max = BUFFER_BYTES_MAX,
300 .period_bytes_min = PERIOD_BYTES_MIN,
301 .period_bytes_max = PERIOD_BYTES_MAX,
302 .periods_min = PERIODS_MIN,
303 .periods_max = PERIODS_MAX,
304 /*.fifo_size = 0,*/
305};
306
02c2de69 307static struct snd_pcm_hardware snd_ad1889_capture_hw = {
12bb5b78
CL		 308 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
309 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER,
310 .formats = SNDRV_PCM_FMTBIT_S16_LE,
311 .rates = SNDRV_PCM_RATE_48000,
312 .rate_min = 48000, /* docs say we could to VSR, but we're lazy */
313 .rate_max = 48000,
314 .channels_min = 1,
315 .channels_max = 2,
316 .buffer_bytes_max = BUFFER_BYTES_MAX,
317 .period_bytes_min = PERIOD_BYTES_MIN,
318 .period_bytes_max = PERIOD_BYTES_MAX,
319 .periods_min = PERIODS_MIN,
320 .periods_max = PERIODS_MAX,
321 /*.fifo_size = 0,*/
322};
323
324static int
02c2de69 325snd_ad1889_playback_open(struct snd_pcm_substream *ss)
12bb5b78
CL		 326{
327 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
02c2de69 328 struct snd_pcm_runtime *rt = ss->runtime;
12bb5b78
CL		 329
330 chip->psubs = ss;
331 rt->hw = snd_ad1889_playback_hw;
332
333 return 0;
334}
335
336static int
02c2de69 337snd_ad1889_capture_open(struct snd_pcm_substream *ss)
12bb5b78
CL		 338{
339 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
02c2de69 340 struct snd_pcm_runtime *rt = ss->runtime;
12bb5b78
CL		 341
342 chip->csubs = ss;
343 rt->hw = snd_ad1889_capture_hw;
344
345 return 0;
346}
347
348static int
02c2de69 349snd_ad1889_playback_close(struct snd_pcm_substream *ss)
12bb5b78
CL		 350{
351 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
352 chip->psubs = NULL;
353 return 0;
354}
355
356static int
02c2de69 357snd_ad1889_capture_close(struct snd_pcm_substream *ss)
12bb5b78
CL		 358{
359 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
360 chip->csubs = NULL;
361 return 0;
362}
363
364static int
02c2de69 365snd_ad1889_playback_prepare(struct snd_pcm_substream *ss)
12bb5b78
CL		 366{
367 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
02c2de69 368 struct snd_pcm_runtime *rt = ss->runtime;
12bb5b78
CL		 369 unsigned int size = snd_pcm_lib_buffer_bytes(ss);
370 unsigned int count = snd_pcm_lib_period_bytes(ss);
371 u16 reg;
372
373 ad1889_channel_reset(chip, AD_CHAN_WAV);
374
375 reg = ad1889_readw(chip, AD_DS_WSMC);
376
377 /* Mask out 16-bit / Stereo */
378 reg &= ~(AD_DS_WSMC_WA16 | AD_DS_WSMC_WAST);
379
380 if (snd_pcm_format_width(rt->format) == 16)
381 reg |= AD_DS_WSMC_WA16;
382
383 if (rt->channels > 1)
384 reg |= AD_DS_WSMC_WAST;
385
386 /* let's make sure we don't clobber ourselves */
387 spin_lock_irq(&chip->lock);
388
389 chip->wave.size = size;
390 chip->wave.reg = reg;
391 chip->wave.addr = rt->dma_addr;
392
393 ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg);
394
395 /* Set sample rates on the codec */
396 ad1889_writew(chip, AD_DS_WAS, rt->rate);
397
398 /* Set up DMA */
399 ad1889_load_wave_buffer_address(chip, chip->wave.addr);
400 ad1889_load_wave_buffer_count(chip, size);
401 ad1889_load_wave_interrupt_count(chip, count);
402
403 /* writes flush */
404 ad1889_readw(chip, AD_DS_WSMC);
405
406 spin_unlock_irq(&chip->lock);
407
408 ad1889_debug("prepare playback: addr = 0x%x, count = %u, "
409 "size = %u, reg = 0x%x, rate = %u\n", chip->wave.addr,
410 count, size, reg, rt->rate);
411 return 0;
412}
413
414static int
02c2de69 415snd_ad1889_capture_prepare(struct snd_pcm_substream *ss)
12bb5b78
CL		 416{
417 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
02c2de69 418 struct snd_pcm_runtime *rt = ss->runtime;
12bb5b78
CL		 419 unsigned int size = snd_pcm_lib_buffer_bytes(ss);
420 unsigned int count = snd_pcm_lib_period_bytes(ss);
421 u16 reg;
422
423 ad1889_channel_reset(chip, AD_CHAN_ADC);
424
425 reg = ad1889_readw(chip, AD_DS_RAMC);
426
427 /* Mask out 16-bit / Stereo */
428 reg &= ~(AD_DS_RAMC_AD16 | AD_DS_RAMC_ADST);
429
430 if (snd_pcm_format_width(rt->format) == 16)
431 reg |= AD_DS_RAMC_AD16;
432
433 if (rt->channels > 1)
434 reg |= AD_DS_RAMC_ADST;
435
436 /* let's make sure we don't clobber ourselves */
437 spin_lock_irq(&chip->lock);
438
439 chip->ramc.size = size;
440 chip->ramc.reg = reg;
441 chip->ramc.addr = rt->dma_addr;
442
443 ad1889_writew(chip, AD_DS_RAMC, chip->ramc.reg);
444
445 /* Set up DMA */
446 ad1889_load_adc_buffer_address(chip, chip->ramc.addr);
447 ad1889_load_adc_buffer_count(chip, size);
448 ad1889_load_adc_interrupt_count(chip, count);
449
450 /* writes flush */
451 ad1889_readw(chip, AD_DS_RAMC);
452
453 spin_unlock_irq(&chip->lock);
454
455 ad1889_debug("prepare capture: addr = 0x%x, count = %u, "
456 "size = %u, reg = 0x%x, rate = %u\n", chip->ramc.addr,
457 count, size, reg, rt->rate);
458 return 0;
459}
460
461/* this is called in atomic context with IRQ disabled.
462 Must be as fast as possible and not sleep.
463 DMA should be *triggered* by this call.
464 The WSMC "WAEN" bit triggers DMA Wave On/Off */
465static int
02c2de69 466snd_ad1889_playback_trigger(struct snd_pcm_substream *ss, int cmd)
12bb5b78
CL		 467{
468 u16 wsmc;
469 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
470
471 wsmc = ad1889_readw(chip, AD_DS_WSMC);
472
473 switch (cmd) {
474 case SNDRV_PCM_TRIGGER_START:
475 /* enable DMA loop & interrupts */
476 ad1889_writew(chip, AD_DMA_WAV, AD_DMA_LOOP | AD_DMA_IM_CNT);
477 wsmc |= AD_DS_WSMC_WAEN;
478 /* 1 to clear CHSS bit */
479 ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_WAVS);
480 ad1889_unmute(chip);
481 break;
482 case SNDRV_PCM_TRIGGER_STOP:
483 ad1889_mute(chip);
484 wsmc &= ~AD_DS_WSMC_WAEN;
485 break;
486 default:
487 snd_BUG();
488 return -EINVAL;
489 }
490
491 chip->wave.reg = wsmc;
492 ad1889_writew(chip, AD_DS_WSMC, wsmc);
493 ad1889_readw(chip, AD_DS_WSMC); /* flush */
494
495 /* reset the chip when STOP - will disable IRQs */
496 if (cmd == SNDRV_PCM_TRIGGER_STOP)
497 ad1889_channel_reset(chip, AD_CHAN_WAV);
498
499 return 0;
500}
501
502/* this is called in atomic context with IRQ disabled.
503 Must be as fast as possible and not sleep.
504 DMA should be *triggered* by this call.
505 The RAMC "ADEN" bit triggers DMA ADC On/Off */
506static int
02c2de69 507snd_ad1889_capture_trigger(struct snd_pcm_substream *ss, int cmd)
12bb5b78
CL		 508{
509 u16 ramc;
510 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
511
512 ramc = ad1889_readw(chip, AD_DS_RAMC);
513
514 switch (cmd) {
515 case SNDRV_PCM_TRIGGER_START:
516 /* enable DMA loop & interrupts */
517 ad1889_writew(chip, AD_DMA_ADC, AD_DMA_LOOP | AD_DMA_IM_CNT);
518 ramc |= AD_DS_RAMC_ADEN;
519 /* 1 to clear CHSS bit */
520 ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_ADCS);
521 break;
522 case SNDRV_PCM_TRIGGER_STOP:
523 ramc &= ~AD_DS_RAMC_ADEN;
524 break;
525 default:
526 return -EINVAL;
527 }
528
529 chip->ramc.reg = ramc;
530 ad1889_writew(chip, AD_DS_RAMC, ramc);
531 ad1889_readw(chip, AD_DS_RAMC); /* flush */
532
533 /* reset the chip when STOP - will disable IRQs */
534 if (cmd == SNDRV_PCM_TRIGGER_STOP)
535 ad1889_channel_reset(chip, AD_CHAN_ADC);
536
537 return 0;
538}
539
540/* Called in atomic context with IRQ disabled */
541static snd_pcm_uframes_t
02c2de69 542snd_ad1889_playback_pointer(struct snd_pcm_substream *ss)
12bb5b78
CL		 543{
544 size_t ptr = 0;
545 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
546
547 if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN)))
548 return 0;
549
550 ptr = ad1889_readl(chip, AD_DMA_WAVCA);
551 ptr -= chip->wave.addr;
552
da3cec35
TI		 553 if (snd_BUG_ON(ptr >= chip->wave.size))
554 return 0;
12bb5b78
CL		 555
556 return bytes_to_frames(ss->runtime, ptr);
557}
558
559/* Called in atomic context with IRQ disabled */
560static snd_pcm_uframes_t
02c2de69 561snd_ad1889_capture_pointer(struct snd_pcm_substream *ss)
12bb5b78
CL		 562{
563 size_t ptr = 0;
564 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
565
566 if (unlikely(!(chip->ramc.reg & AD_DS_RAMC_ADEN)))
567 return 0;
568
569 ptr = ad1889_readl(chip, AD_DMA_ADCCA);
570 ptr -= chip->ramc.addr;
571
da3cec35
TI		 572 if (snd_BUG_ON(ptr >= chip->ramc.size))
573 return 0;
12bb5b78
CL		 574
575 return bytes_to_frames(ss->runtime, ptr);
576}
577
02c2de69 578static struct snd_pcm_ops snd_ad1889_playback_ops = {
12bb5b78
CL		 579 .open = snd_ad1889_playback_open,
580 .close = snd_ad1889_playback_close,
581 .ioctl = snd_pcm_lib_ioctl,
582 .hw_params = snd_ad1889_hw_params,
583 .hw_free = snd_ad1889_hw_free,
584 .prepare = snd_ad1889_playback_prepare,
585 .trigger = snd_ad1889_playback_trigger,
586 .pointer = snd_ad1889_playback_pointer,
587};
588
02c2de69 589static struct snd_pcm_ops snd_ad1889_capture_ops = {
12bb5b78
CL		 590 .open = snd_ad1889_capture_open,
591 .close = snd_ad1889_capture_close,
592 .ioctl = snd_pcm_lib_ioctl,
593 .hw_params = snd_ad1889_hw_params,
594 .hw_free = snd_ad1889_hw_free,
595 .prepare = snd_ad1889_capture_prepare,
596 .trigger = snd_ad1889_capture_trigger,
597 .pointer = snd_ad1889_capture_pointer,
598};
599
600static irqreturn_t
7d12e780 601snd_ad1889_interrupt(int irq, void *dev_id)
12bb5b78
CL		 602{
603 unsigned long st;
604 struct snd_ad1889 *chip = dev_id;
605
606 st = ad1889_readl(chip, AD_DMA_DISR);
607
608 /* clear ISR */
609 ad1889_writel(chip, AD_DMA_DISR, st);
610
611 st &= AD_INTR_MASK;
612
613 if (unlikely(!st))
614 return IRQ_NONE;
615
616 if (st & (AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI))
617 ad1889_debug("Unexpected master or target abort interrupt!\n");
618
619 if ((st & AD_DMA_DISR_WAVI) && chip->psubs)
620 snd_pcm_period_elapsed(chip->psubs);
621 if ((st & AD_DMA_DISR_ADCI) && chip->csubs)
622 snd_pcm_period_elapsed(chip->csubs);
623
624 return IRQ_HANDLED;
625}
626
2f5c1302 627static int
02c2de69 628snd_ad1889_pcm_init(struct snd_ad1889 *chip, int device, struct snd_pcm **rpcm)
12bb5b78
CL		 629{
630 int err;
02c2de69 631 struct snd_pcm *pcm;
12bb5b78
CL		 632
633 if (rpcm)
634 *rpcm = NULL;
635
636 err = snd_pcm_new(chip->card, chip->card->driver, device, 1, 1, &pcm);
637 if (err < 0)
638 return err;
639
640 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
641 &snd_ad1889_playback_ops);
642 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
643 &snd_ad1889_capture_ops);
644
645 pcm->private_data = chip;
12bb5b78
CL		 646 pcm->info_flags = 0;
647 strcpy(pcm->name, chip->card->shortname);
648
649 chip->pcm = pcm;
650 chip->psubs = NULL;
651 chip->csubs = NULL;
652
653 err = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
654 snd_dma_pci_data(chip->pci),
655 BUFFER_BYTES_MAX / 2,
656 BUFFER_BYTES_MAX);
657
658 if (err < 0) {
659 snd_printk(KERN_ERR PFX "buffer allocation error: %d\n", err);
660 return err;
661 }
662
663 if (rpcm)
664 *rpcm = pcm;
665
666 return 0;
667}
668
669static void
02c2de69 670snd_ad1889_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
12bb5b78
CL		 671{
672 struct snd_ad1889 *chip = entry->private_data;
673 u16 reg;
674 int tmp;
675
676 reg = ad1889_readw(chip, AD_DS_WSMC);
677 snd_iprintf(buffer, "Wave output: %s\n",
678 (reg & AD_DS_WSMC_WAEN) ? "enabled" : "disabled");
679 snd_iprintf(buffer, "Wave Channels: %s\n",
680 (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
681 snd_iprintf(buffer, "Wave Quality: %d-bit linear\n",
682 (reg & AD_DS_WSMC_WA16) ? 16 : 8);
683
684 /* WARQ is at offset 12 */
685 tmp = (reg & AD_DS_WSMC_WARQ) ?
686 (((reg & AD_DS_WSMC_WARQ >> 12) & 0x01) ? 12 : 18) : 4;
687 tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
688
689 snd_iprintf(buffer, "Wave FIFO: %d %s words\n\n", tmp,
690 (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
691
692
693 snd_iprintf(buffer, "Synthesis output: %s\n",
694 reg & AD_DS_WSMC_SYEN ? "enabled" : "disabled");
695
696 /* SYRQ is at offset 4 */
697 tmp = (reg & AD_DS_WSMC_SYRQ) ?
698 (((reg & AD_DS_WSMC_SYRQ >> 4) & 0x01) ? 12 : 18) : 4;
699 tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
700
701 snd_iprintf(buffer, "Synthesis FIFO: %d %s words\n\n", tmp,
702 (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
703
704 reg = ad1889_readw(chip, AD_DS_RAMC);
705 snd_iprintf(buffer, "ADC input: %s\n",
706 (reg & AD_DS_RAMC_ADEN) ? "enabled" : "disabled");
707 snd_iprintf(buffer, "ADC Channels: %s\n",
708 (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono");
709 snd_iprintf(buffer, "ADC Quality: %d-bit linear\n",
710 (reg & AD_DS_RAMC_AD16) ? 16 : 8);
711
712 /* ACRQ is at offset 4 */
713 tmp = (reg & AD_DS_RAMC_ACRQ) ?
714 (((reg & AD_DS_RAMC_ACRQ >> 4) & 0x01) ? 12 : 18) : 4;
715 tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
716
717 snd_iprintf(buffer, "ADC FIFO: %d %s words\n\n", tmp,
718 (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono");
719
720 snd_iprintf(buffer, "Resampler input: %s\n",
721 reg & AD_DS_RAMC_REEN ? "enabled" : "disabled");
722
723 /* RERQ is at offset 12 */
724 tmp = (reg & AD_DS_RAMC_RERQ) ?
725 (((reg & AD_DS_RAMC_RERQ >> 12) & 0x01) ? 12 : 18) : 4;
726 tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
727
728 snd_iprintf(buffer, "Resampler FIFO: %d %s words\n\n", tmp,
729 (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
730
731
732 /* doc says LSB represents -1.5dB, but the max value (-94.5dB)
733 suggests that LSB is -3dB, which is more coherent with the logarithmic
734 nature of the dB scale */
735 reg = ad1889_readw(chip, AD_DS_WADA);
736 snd_iprintf(buffer, "Left: %s, -%d dB\n",
737 (reg & AD_DS_WADA_LWAM) ? "mute" : "unmute",
738 ((reg & AD_DS_WADA_LWAA) >> 8) * 3);
739 reg = ad1889_readw(chip, AD_DS_WADA);
740 snd_iprintf(buffer, "Right: %s, -%d dB\n",
741 (reg & AD_DS_WADA_RWAM) ? "mute" : "unmute",
742 ((reg & AD_DS_WADA_RWAA) >> 8) * 3);
743
744 reg = ad1889_readw(chip, AD_DS_WAS);
745 snd_iprintf(buffer, "Wave samplerate: %u Hz\n", reg);
746 reg = ad1889_readw(chip, AD_DS_RES);
747 snd_iprintf(buffer, "Resampler samplerate: %u Hz\n", reg);
748}
749
2f5c1302 750static void
12bb5b78
CL		 751snd_ad1889_proc_init(struct snd_ad1889 *chip)
752{
02c2de69 753 struct snd_info_entry *entry;
12bb5b78
CL		 754
755 if (!snd_card_proc_new(chip->card, chip->card->driver, &entry))
bf850204 756 snd_info_set_text_ops(entry, chip, snd_ad1889_proc_read);
12bb5b78
CL		 757}
758
759static struct ac97_quirk ac97_quirks[] = {
760 {
761 .subvendor = 0x11d4, /* AD */
762 .subdevice = 0x1889, /* AD1889 */
763 .codec_id = AC97_ID_AD1819,
764 .name = "AD1889",
765 .type = AC97_TUNE_HP_ONLY
766 },
767 { } /* terminator */
768};
769
2f5c1302 770static void
12bb5b78
CL		 771snd_ad1889_ac97_xinit(struct snd_ad1889 *chip)
772{
773 u16 reg;
774
775 reg = ad1889_readw(chip, AD_AC97_ACIC);
776 reg |= AD_AC97_ACIC_ACRD; /* Reset Disable */
777 ad1889_writew(chip, AD_AC97_ACIC, reg);
778 ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */
779 udelay(10);
780 /* Interface Enable */
781 reg |= AD_AC97_ACIC_ACIE;
782 ad1889_writew(chip, AD_AC97_ACIC, reg);
783
784 snd_ad1889_ac97_ready(chip);
785
786 /* Audio Stream Output | Variable Sample Rate Mode */
787 reg = ad1889_readw(chip, AD_AC97_ACIC);
788 reg |= AD_AC97_ACIC_ASOE | AD_AC97_ACIC_VSRM;
789 ad1889_writew(chip, AD_AC97_ACIC, reg);
790 ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */
791
792}
793
794static void
02c2de69 795snd_ad1889_ac97_bus_free(struct snd_ac97_bus *bus)
12bb5b78
CL		 796{
797 struct snd_ad1889 *chip = bus->private_data;
798 chip->ac97_bus = NULL;
799}
800
801static void
02c2de69 802snd_ad1889_ac97_free(struct snd_ac97 *ac97)
12bb5b78
CL		 803{
804 struct snd_ad1889 *chip = ac97->private_data;
805 chip->ac97 = NULL;
806}
807
2f5c1302 808static int
12bb5b78
CL		 809snd_ad1889_ac97_init(struct snd_ad1889 *chip, const char *quirk_override)
810{
811 int err;
02c2de69
TI		 812 struct snd_ac97_template ac97;
813 static struct snd_ac97_bus_ops ops = {
12bb5b78
CL		 814 .write = snd_ad1889_ac97_write,
815 .read = snd_ad1889_ac97_read,
816 };
817
818 /* doing that here, it works. */
819 snd_ad1889_ac97_xinit(chip);
820
821 err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus);
822 if (err < 0)
823 return err;
824
825 chip->ac97_bus->private_free = snd_ad1889_ac97_bus_free;
826
827 memset(&ac97, 0, sizeof(ac97));
828 ac97.private_data = chip;
829 ac97.private_free = snd_ad1889_ac97_free;
830 ac97.pci = chip->pci;
831
832 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97);
833 if (err < 0)
834 return err;
835
836 snd_ac97_tune_hardware(chip->ac97, ac97_quirks, quirk_override);
837
838 return 0;
839}
840
841static int
842snd_ad1889_free(struct snd_ad1889 *chip)
843{
844 if (chip->irq < 0)
845 goto skip_hw;
846
847 spin_lock_irq(&chip->lock);
848
849 ad1889_mute(chip);
850
851 /* Turn off interrupt on count and zero DMA registers */
852 ad1889_channel_reset(chip, AD_CHAN_WAV | AD_CHAN_ADC);
853
854 /* clear DISR. If we don't, we'd better jump off the Eiffel Tower */
855 ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PTAI | AD_DMA_DISR_PMAI);
856 ad1889_readl(chip, AD_DMA_DISR); /* flush, dammit! */
857
858 spin_unlock_irq(&chip->lock);
859
12bb5b78 860 if (chip->irq >= 0)
437a5a46 861 free_irq(chip->irq, chip);
12bb5b78
CL		 862
863skip_hw:
864 if (chip->iobase)
865 iounmap(chip->iobase);
866
867 pci_release_regions(chip->pci);
868 pci_disable_device(chip->pci);
869
870 kfree(chip);
871 return 0;
872}
873
f40b6890 874static int
02c2de69 875snd_ad1889_dev_free(struct snd_device *device)
12bb5b78
CL		 876{
877 struct snd_ad1889 *chip = device->device_data;
878 return snd_ad1889_free(chip);
879}
880
2f5c1302 881static int
12bb5b78
CL		 882snd_ad1889_init(struct snd_ad1889 *chip)
883{
884 ad1889_writew(chip, AD_DS_CCS, AD_DS_CCS_CLKEN); /* turn on clock */
885 ad1889_readw(chip, AD_DS_CCS); /* flush posted write */
886
887 mdelay(10);
888
889 /* enable Master and Target abort interrupts */
890 ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PMAE | AD_DMA_DISR_PTAE);
891
892 return 0;
893}
894
2f5c1302 895static int
02c2de69 896snd_ad1889_create(struct snd_card *card,
12bb5b78
CL		 897 struct pci_dev *pci,
898 struct snd_ad1889 **rchip)
899{
900 int err;
901
902 struct snd_ad1889 *chip;
02c2de69 903 static struct snd_device_ops ops = {
12bb5b78
CL		 904 .dev_free = snd_ad1889_dev_free,
905 };
906
907 *rchip = NULL;
908
909 if ((err = pci_enable_device(pci)) < 0)
910 return err;
9d2f928d 911
12bb5b78 912 /* check PCI availability (32bit DMA) */
284901a9
YH		 913 if (pci_set_dma_mask(pci, DMA_BIT_MASK(32)) < 0 ||
914 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)) < 0) {
12bb5b78
CL		 915 printk(KERN_ERR PFX "error setting 32-bit DMA mask.\n");
916 pci_disable_device(pci);
917 return -ENXIO;
918 }
919
920 /* allocate chip specific data with zero-filled memory */
e560d8d8 921 if ((chip = kzalloc(sizeof(*chip), GFP_KERNEL)) == NULL) {
12bb5b78
CL		 922 pci_disable_device(pci);
923 return -ENOMEM;
924 }
925
926 chip->card = card;
927 card->private_data = chip;
928 chip->pci = pci;
929 chip->irq = -1;
930
931 /* (1) PCI resource allocation */
932 if ((err = pci_request_regions(pci, card->driver)) < 0)
933 goto free_and_ret;
934
935 chip->bar = pci_resource_start(pci, 0);
2f5ad54e 936 chip->iobase = pci_ioremap_bar(pci, 0);
12bb5b78
CL		 937 if (chip->iobase == NULL) {
938 printk(KERN_ERR PFX "unable to reserve region.\n");
939 err = -EBUSY;
940 goto free_and_ret;
941 }
942
943 pci_set_master(pci);
944
945 spin_lock_init(&chip->lock); /* only now can we call ad1889_free */
946
947 if (request_irq(pci->irq, snd_ad1889_interrupt,
934c2b6d 948 IRQF_SHARED, KBUILD_MODNAME, chip)) {
12bb5b78
CL		 949 printk(KERN_ERR PFX "cannot obtain IRQ %d\n", pci->irq);
950 snd_ad1889_free(chip);
951 return -EBUSY;
952 }
953
954 chip->irq = pci->irq;
955 synchronize_irq(chip->irq);
956
957 /* (2) initialization of the chip hardware */
958 if ((err = snd_ad1889_init(chip)) < 0) {
959 snd_ad1889_free(chip);
960 return err;
961 }
962
963 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
964 snd_ad1889_free(chip);
965 return err;
966 }
967
968 snd_card_set_dev(card, &pci->dev);
969
970 *rchip = chip;
971
972 return 0;
973
974free_and_ret:
fc58422a 975 kfree(chip);
12bb5b78
CL		 976 pci_disable_device(pci);
977
978 return err;
979}
980
2f5c1302 981static int
12bb5b78
CL		 982snd_ad1889_probe(struct pci_dev *pci,
983 const struct pci_device_id *pci_id)
984{
985 int err;
986 static int devno;
02c2de69 987 struct snd_card *card;
12bb5b78
CL		 988 struct snd_ad1889 *chip;
989
990 /* (1) */
991 if (devno >= SNDRV_CARDS)
992 return -ENODEV;
993 if (!enable[devno]) {
994 devno++;
995 return -ENOENT;
996 }
997
998 /* (2) */
e58de7ba 999 err = snd_card_create(index[devno], id[devno], THIS_MODULE, 0, &card);
12bb5b78 1000 /* XXX REVISIT: we can probably allocate chip in this call */
e58de7ba
TI		 1001 if (err < 0)
1002 return err;
12bb5b78
CL		 1003
1004 strcpy(card->driver, "AD1889");
1005 strcpy(card->shortname, "Analog Devices AD1889");
1006
1007 /* (3) */
1008 err = snd_ad1889_create(card, pci, &chip);
1009 if (err < 0)
1010 goto free_and_ret;
1011
1012 /* (4) */
1013 sprintf(card->longname, "%s at 0x%lx irq %i",
1014 card->shortname, chip->bar, chip->irq);
1015
1016 /* (5) */
1017 /* register AC97 mixer */
1018 err = snd_ad1889_ac97_init(chip, ac97_quirk[devno]);
1019 if (err < 0)
1020 goto free_and_ret;
1021
1022 err = snd_ad1889_pcm_init(chip, 0, NULL);
1023 if (err < 0)
1024 goto free_and_ret;
1025
1026 /* register proc interface */
1027 snd_ad1889_proc_init(chip);
1028
1029 /* (6) */
1030 err = snd_card_register(card);
1031 if (err < 0)
1032 goto free_and_ret;
1033
1034 /* (7) */
1035 pci_set_drvdata(pci, card);
1036
1037 devno++;
1038 return 0;
1039
1040free_and_ret:
1041 snd_card_free(card);
1042 return err;
1043}
1044
2f5c1302 1045static void
12bb5b78
CL		 1046snd_ad1889_remove(struct pci_dev *pci)
1047{
1048 snd_card_free(pci_get_drvdata(pci));
1049 pci_set_drvdata(pci, NULL);
1050}
1051
cebe41d4 1052static DEFINE_PCI_DEVICE_TABLE(snd_ad1889_ids) = {
12bb5b78
CL		 1053 { PCI_DEVICE(PCI_VENDOR_ID_ANALOG_DEVICES, PCI_DEVICE_ID_AD1889JS) },
1054 { 0, },
1055};
1056MODULE_DEVICE_TABLE(pci, snd_ad1889_ids);
1057
e4d76815 1058static struct pci_driver ad1889_pci_driver = {
3733e424 1059 .name = KBUILD_MODNAME,
12bb5b78
CL		 1060 .id_table = snd_ad1889_ids,
1061 .probe = snd_ad1889_probe,
2f5c1302 1062 .remove = snd_ad1889_remove,
12bb5b78
CL		 1063};
1064
e9f66d9b 1065module_pci_driver(ad1889_pci_driver);
kernel source for telekom puls (alcatel/mediatek)