[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / video / exynos_dp.h

/*
 * Samsung SoC DP device support
 *
 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
 * Author: Jingoo Han <jg1.han@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _EXYNOS_DP_H
#define _EXYNOS_DP_H

#define DP_TIMEOUT_LOOP_COUNT 100
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5

enum link_rate_type {
	LINK_RATE_1_62GBPS = 0x06,
	LINK_RATE_2_70GBPS = 0x0a
};

enum link_lane_count_type {
	LANE_COUNT1 = 1,
	LANE_COUNT2 = 2,
	LANE_COUNT4 = 4
};

enum link_training_state {
	START,
	CLOCK_RECOVERY,
	EQUALIZER_TRAINING,
	FINISHED,
	FAILED
};

enum voltage_swing_level {
	VOLTAGE_LEVEL_0,
	VOLTAGE_LEVEL_1,
	VOLTAGE_LEVEL_2,
	VOLTAGE_LEVEL_3,
};

enum pre_emphasis_level {
	PRE_EMPHASIS_LEVEL_0,
	PRE_EMPHASIS_LEVEL_1,
	PRE_EMPHASIS_LEVEL_2,
	PRE_EMPHASIS_LEVEL_3,
};

enum pattern_set {
	PRBS7,
	D10_2,
	TRAINING_PTN1,
	TRAINING_PTN2,
	DP_NONE
};

enum color_space {
	COLOR_RGB,
	COLOR_YCBCR422,
	COLOR_YCBCR444
};

enum color_depth {
	COLOR_6,
	COLOR_8,
	COLOR_10,
	COLOR_12
};

enum color_coefficient {
	COLOR_YCBCR601,
	COLOR_YCBCR709
};

enum dynamic_range {
	VESA,
	CEA
};

enum pll_status {
	PLL_UNLOCKED,
	PLL_LOCKED
};

enum clock_recovery_m_value_type {
	CALCULATED_M,
	REGISTER_M
};

enum video_timing_recognition_type {
	VIDEO_TIMING_FROM_CAPTURE,
	VIDEO_TIMING_FROM_REGISTER
};

enum analog_power_block {
	AUX_BLOCK,
	CH0_BLOCK,
	CH1_BLOCK,
	CH2_BLOCK,
	CH3_BLOCK,
	ANALOG_TOTAL,
	POWER_ALL
};

struct video_info {
	char *name;

	bool h_sync_polarity;
	bool v_sync_polarity;
	bool interlaced;

	enum color_space color_space;
	enum dynamic_range dynamic_range;
	enum color_coefficient ycbcr_coeff;
	enum color_depth color_depth;

	enum link_rate_type link_rate;
	enum link_lane_count_type lane_count;
};

struct exynos_dp_platdata {
	struct video_info *video_info;

	void (*phy_init)(void);
	void (*phy_exit)(void);
};

#endif /* _EXYNOS_DP_H */
Commit	Line	Data
e9474be4 JH	1	/*
	2	* Samsung SoC DP device support
	3	*
	4	* Copyright (C) 2012 Samsung Electronics Co., Ltd.
	5	* Author: Jingoo Han <jg1.han@samsung.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#ifndef _EXYNOS_DP_H
	13	#define _EXYNOS_DP_H
	14
	15	#define DP_TIMEOUT_LOOP_COUNT 100
	16	#define MAX_CR_LOOP 5
982cfa2f	17	#define MAX_EQ_LOOP 5
e9474be4 JH	18
	19	enum link_rate_type {
	20	LINK_RATE_1_62GBPS = 0x06,
	21	LINK_RATE_2_70GBPS = 0x0a
	22	};
	23
	24	enum link_lane_count_type {
	25	LANE_COUNT1 = 1,
	26	LANE_COUNT2 = 2,
	27	LANE_COUNT4 = 4
	28	};
	29
	30	enum link_training_state {
	31	START,
	32	CLOCK_RECOVERY,
	33	EQUALIZER_TRAINING,
	34	FINISHED,
	35	FAILED
	36	};
	37
	38	enum voltage_swing_level {
	39	VOLTAGE_LEVEL_0,
	40	VOLTAGE_LEVEL_1,
	41	VOLTAGE_LEVEL_2,
	42	VOLTAGE_LEVEL_3,
	43	};
	44
	45	enum pre_emphasis_level {
	46	PRE_EMPHASIS_LEVEL_0,
	47	PRE_EMPHASIS_LEVEL_1,
	48	PRE_EMPHASIS_LEVEL_2,
	49	PRE_EMPHASIS_LEVEL_3,
	50	};
	51
	52	enum pattern_set {
	53	PRBS7,
	54	D10_2,
	55	TRAINING_PTN1,
	56	TRAINING_PTN2,
	57	DP_NONE
	58	};
	59
	60	enum color_space {
	61	COLOR_RGB,
	62	COLOR_YCBCR422,
	63	COLOR_YCBCR444
	64	};
	65
	66	enum color_depth {
	67	COLOR_6,
	68	COLOR_8,
	69	COLOR_10,
	70	COLOR_12
	71	};
	72
	73	enum color_coefficient {
	74	COLOR_YCBCR601,
	75	COLOR_YCBCR709
	76	};
	77
	78	enum dynamic_range {
	79	VESA,
	80	CEA
	81	};
82
83	enum pll_status {
84	PLL_UNLOCKED,
85	PLL_LOCKED
86	};
87
88	enum clock_recovery_m_value_type {
89	CALCULATED_M,
90	REGISTER_M
91	};
92
93	enum video_timing_recognition_type {
94	VIDEO_TIMING_FROM_CAPTURE,
95	VIDEO_TIMING_FROM_REGISTER
96	};
97
98	enum analog_power_block {
99	AUX_BLOCK,
100	CH0_BLOCK,
101	CH1_BLOCK,
102	CH2_BLOCK,
103	CH3_BLOCK,
104	ANALOG_TOTAL,
105	POWER_ALL
106	};
107
108	struct video_info {
109	char *name;
110
111	bool h_sync_polarity;
112	bool v_sync_polarity;
113	bool interlaced;
114
115	enum color_space color_space;
116	enum dynamic_range dynamic_range;
117	enum color_coefficient ycbcr_coeff;
118	enum color_depth color_depth;
119
120	enum link_rate_type link_rate;
121	enum link_lane_count_type lane_count;
122	};
123
124	struct exynos_dp_platdata {
125	struct video_info *video_info;
126
127	void (*phy_init)(void);
128	void (*phy_exit)(void);
129	};
130
131	#endif /* _EXYNOS_DP_H */