projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| d2da2611 SNC |
1 | /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics |
| 2 | * Digitizer with Horizontal PLL registers | |
| 3 | * | |
| 4 | * Copyright (C) 2009 Texas Instruments Inc | |
| 5 | * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> | |
| 6 | * | |
| 7 | * This code is partially based upon the TVP5150 driver | |
| 8 | * written by Mauro Carvalho Chehab (mchehab@infradead.org), | |
| 9 | * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com> | |
| 10 | * and the TVP7002 driver in the TI LSP 2.10.00.14 | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or modify | |
| 13 | * it under the terms of the GNU General Public License as published by | |
| 14 | * the Free Software Foundation; either version 2 of the License, or | |
| 15 | * (at your option) any later version. | |
| 16 | * | |
| 17 | * This program is distributed in the hope that it will be useful, | |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 20 | * GNU General Public License for more details. | |
| 21 | * | |
| 22 | * You should have received a copy of the GNU General Public License | |
| 23 | * along with this program; if not, write to the Free Software | |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 25 | */ | |
| 26 | #ifndef _TVP7002_H_ | |
| 27 | #define _TVP7002_H_ | |
| 28 | ||
| 29 | /* Platform-dependent data | |
| 30 | * | |
| 31 | * clk_polarity: | |
| 32 | * 0 -> data clocked out on rising edge of DATACLK signal | |
| 33 | * 1 -> data clocked out on falling edge of DATACLK signal | |
| 34 | * hs_polarity: | |
| 35 | * 0 -> active low HSYNC output | |
| 36 | * 1 -> active high HSYNC output | |
| 37 | * sog_polarity: | |
| 38 | * 0 -> normal operation | |
| 39 | * 1 -> operation with polarity inverted | |
| 40 | * vs_polarity: | |
| 41 | * 0 -> active low VSYNC output | |
| 42 | * 1 -> active high VSYNC output | |
| 43 | * fid_polarity: | |
| 44 | * 0 -> the field ID output is set to logic 1 for an odd | |
| 45 | * field (field 1) and set to logic 0 for an even | |
| 46 | * field (field 0). | |
| 47 | * 1 -> operation with polarity inverted. | |
| 48 | */ | |
| 49 | struct tvp7002_config { | |
| 50 | u8 clk_polarity; | |
| 51 | u8 hs_polarity; | |
| 52 | u8 vs_polarity; | |
| 53 | u8 fid_polarity; | |
| 54 | u8 sog_polarity; | |
| 55 | }; | |
| 56 | #endif |