[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / sh_intc.h

#ifndef __SH_INTC_H
#define __SH_INTC_H

#include <linux/ioport.h>

#ifdef CONFIG_SUPERH
#define INTC_NR_IRQS	512
#else
#define INTC_NR_IRQS	1024
#endif

/*
 * Convert back and forth between INTEVT and IRQ values.
 */
#ifdef CONFIG_CPU_HAS_INTEVT
#define evt2irq(evt)		(((evt) >> 5) - 16)
#define irq2evt(irq)		(((irq) + 16) << 5)
#else
#define evt2irq(evt)		(evt)
#define irq2evt(irq)		(irq)
#endif

typedef unsigned char intc_enum;

struct intc_vect {
	intc_enum enum_id;
	unsigned short vect;
};

#define INTC_VECT(enum_id, vect) { enum_id, vect }
#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))

struct intc_group {
	intc_enum enum_id;
	intc_enum enum_ids[32];
};

#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }

struct intc_subgroup {
	unsigned long reg, reg_width;
	intc_enum parent_id;
	intc_enum enum_ids[32];
};

struct intc_mask_reg {
	unsigned long set_reg, clr_reg, reg_width;
	intc_enum enum_ids[32];
#ifdef CONFIG_INTC_BALANCING
	unsigned long dist_reg;
#endif
#ifdef CONFIG_SMP
	unsigned long smp;
#endif
};

struct intc_prio_reg {
	unsigned long set_reg, clr_reg, reg_width, field_width;
	intc_enum enum_ids[16];
#ifdef CONFIG_SMP
	unsigned long smp;
#endif
};

struct intc_sense_reg {
	unsigned long reg, reg_width, field_width;
	intc_enum enum_ids[16];
};

#ifdef CONFIG_INTC_BALANCING
#define INTC_SMP_BALANCING(reg)	.dist_reg = (reg)
#else
#define INTC_SMP_BALANCING(reg)
#endif

#ifdef CONFIG_SMP
#define INTC_SMP(stride, nr)	.smp = (stride) | ((nr) << 8)
#else
#define INTC_SMP(stride, nr)
#endif

struct intc_hw_desc {
	struct intc_vect *vectors;
	unsigned int nr_vectors;
	struct intc_group *groups;
	unsigned int nr_groups;
	struct intc_mask_reg *mask_regs;
	unsigned int nr_mask_regs;
	struct intc_prio_reg *prio_regs;
	unsigned int nr_prio_regs;
	struct intc_sense_reg *sense_regs;
	unsigned int nr_sense_regs;
	struct intc_mask_reg *ack_regs;
	unsigned int nr_ack_regs;
	struct intc_subgroup *subgroups;
	unsigned int nr_subgroups;
};

#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a)

#define INTC_HW_DESC(vectors, groups, mask_regs,	\
		     prio_regs,	sense_regs, ack_regs)	\
{							\
	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),	\
	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),	\
	_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs),	\
}

struct intc_desc {
	char *name;
	struct resource *resource;
	unsigned int num_resources;
	intc_enum force_enable;
	intc_enum force_disable;
	bool skip_syscore_suspend;
	struct intc_hw_desc hw;
};

#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,		\
	mask_regs, prio_regs, sense_regs)				\
struct intc_desc symbol __initdata = {					\
	.name = chipname,						\
	.hw = INTC_HW_DESC(vectors, groups, mask_regs,			\
			   prio_regs, sense_regs, NULL),		\
}

#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,	\
	mask_regs, prio_regs, sense_regs, ack_regs)			\
struct intc_desc symbol __initdata = {					\
	.name = chipname,						\
	.hw = INTC_HW_DESC(vectors, groups, mask_regs,			\
			   prio_regs, sense_regs, ack_regs),		\
}

int register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);
int intc_irq_lookup(const char *chipname, intc_enum enum_id);
void intc_finalize(void);

#ifdef CONFIG_INTC_USERIMASK
int register_intc_userimask(unsigned long addr);
#else
static inline int register_intc_userimask(unsigned long addr)
{
	return 0;
}
#endif

#endif /* __SH_INTC_H */
Commit	Line	Data
bbfbd8b1 PM	1	#ifndef __SH_INTC_H
	2	#define __SH_INTC_H
	3
dec710b7 MD	4	#include <linux/ioport.h>
dec710b7 MD	5
0f552393 RH	6	#ifdef CONFIG_SUPERH
	7	#define INTC_NR_IRQS 512
	8	#else
	9	#define INTC_NR_IRQS 1024
	10	#endif
	11
7f1e7637 RH	12	/*
	13	* Convert back and forth between INTEVT and IRQ values.
	14	*/
	15	#ifdef CONFIG_CPU_HAS_INTEVT
	16	#define evt2irq(evt) (((evt) >> 5) - 16)
	17	#define irq2evt(irq) (((irq) + 16) << 5)
	18	#else
	19	#define evt2irq(evt) (evt)
	20	#define irq2evt(irq) (irq)
	21	#endif
	22
bbfbd8b1 PM	23	typedef unsigned char intc_enum;
	24
	25	struct intc_vect {
	26	intc_enum enum_id;
	27	unsigned short vect;
	28	};
	29
	30	#define INTC_VECT(enum_id, vect) { enum_id, vect }
	31	#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
	32
	33	struct intc_group {
	34	intc_enum enum_id;
	35	intc_enum enum_ids[32];
	36	};
	37
	38	#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
	39
c1e30ad9 PM	40	struct intc_subgroup {
	41	unsigned long reg, reg_width;
	42	intc_enum parent_id;
	43	intc_enum enum_ids[32];
	44	};
	45
bbfbd8b1 PM	46	struct intc_mask_reg {
	47	unsigned long set_reg, clr_reg, reg_width;
	48	intc_enum enum_ids[32];
dc825b17 PM	49	#ifdef CONFIG_INTC_BALANCING
	50	unsigned long dist_reg;
	51	#endif
bbfbd8b1 PM	52	#ifdef CONFIG_SMP
	53	unsigned long smp;
	54	#endif
	55	};
	56
	57	struct intc_prio_reg {
	58	unsigned long set_reg, clr_reg, reg_width, field_width;
	59	intc_enum enum_ids[16];
	60	#ifdef CONFIG_SMP
	61	unsigned long smp;
	62	#endif
	63	};
	64
	65	struct intc_sense_reg {
	66	unsigned long reg, reg_width, field_width;
	67	intc_enum enum_ids[16];
	68	};
	69
dc825b17 PM	70	#ifdef CONFIG_INTC_BALANCING
	71	#define INTC_SMP_BALANCING(reg) .dist_reg = (reg)
	72	#else
	73	#define INTC_SMP_BALANCING(reg)
	74	#endif
	75
bbfbd8b1	76	#ifdef CONFIG_SMP
dc825b17	77	#define INTC_SMP(stride, nr) .smp = (stride) \| ((nr) << 8)
bbfbd8b1 PM	78	#else
	79	#define INTC_SMP(stride, nr)
	80	#endif
	81
577cd758	82	struct intc_hw_desc {
bbfbd8b1 PM	83	struct intc_vect *vectors;
	84	unsigned int nr_vectors;
	85	struct intc_group *groups;
	86	unsigned int nr_groups;
	87	struct intc_mask_reg *mask_regs;
	88	unsigned int nr_mask_regs;
	89	struct intc_prio_reg *prio_regs;
	90	unsigned int nr_prio_regs;
	91	struct intc_sense_reg *sense_regs;
	92	unsigned int nr_sense_regs;
bbfbd8b1 PM	93	struct intc_mask_reg *ack_regs;
bbfbd8b1 PM	94	unsigned int nr_ack_regs;
c1e30ad9 PM	95	struct intc_subgroup *subgroups;
c1e30ad9 PM	96	unsigned int nr_subgroups;
bbfbd8b1 PM	97	};
bbfbd8b1 PM	98
99870bd7	99	#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a)
c1e30ad9	100
577cd758 MD	101	#define INTC_HW_DESC(vectors, groups, mask_regs, \
	102	prio_regs, sense_regs, ack_regs) \
	103	{ \
	104	_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
	105	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
	106	_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs), \
	107	}
	108
	109	struct intc_desc {
	110	char *name;
dec710b7 MD	111	struct resource *resource;
dec710b7 MD	112	unsigned int num_resources;
d5190953	113	intc_enum force_enable;
d85429a3	114	intc_enum force_disable;
0f966d74	115	bool skip_syscore_suspend;
577cd758 MD	116	struct intc_hw_desc hw;
	117	};
	118
bbfbd8b1 PM	119	#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
	120	mask_regs, prio_regs, sense_regs) \
	121	struct intc_desc symbol __initdata = { \
577cd758 MD	122	.name = chipname, \
	123	.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
	124	prio_regs, sense_regs, NULL), \
bbfbd8b1 PM	125	}
bbfbd8b1 PM	126
bbfbd8b1 PM	127	#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
	128	mask_regs, prio_regs, sense_regs, ack_regs) \
	129	struct intc_desc symbol __initdata = { \
577cd758 MD	130	.name = chipname, \
	131	.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
	132	prio_regs, sense_regs, ack_regs), \
bbfbd8b1	133	}
bbfbd8b1	134
2be6bb0c	135	int register_intc_controller(struct intc_desc *desc);
bbfbd8b1	136	int intc_set_priority(unsigned int irq, unsigned int prio);
d74310d3	137	int intc_irq_lookup(const char *chipname, intc_enum enum_id);
c1e30ad9	138	void intc_finalize(void);
bbfbd8b1	139
43b8774d PM	140	#ifdef CONFIG_INTC_USERIMASK
	141	int register_intc_userimask(unsigned long addr);
	142	#else
	143	static inline int register_intc_userimask(unsigned long addr)
	144	{
	145	return 0;
	146	}
	147	#endif
	148
bbfbd8b1	149	#endif /* __SH_INTC_H */