[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / sh_clk.h

#ifndef __SH_CLOCK_H
#define __SH_CLOCK_H

#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/cpufreq.h>
#include <linux/types.h>
#include <linux/kref.h>
#include <linux/clk.h>
#include <linux/err.h>

struct clk;

struct clk_mapping {
	phys_addr_t		phys;
	void __iomem		*base;
	unsigned long		len;
	struct kref		ref;
};

struct sh_clk_ops {
#ifdef CONFIG_SH_CLK_CPG_LEGACY
	void (*init)(struct clk *clk);
#endif
	int (*enable)(struct clk *clk);
	void (*disable)(struct clk *clk);
	unsigned long (*recalc)(struct clk *clk);
	int (*set_rate)(struct clk *clk, unsigned long rate);
	int (*set_parent)(struct clk *clk, struct clk *parent);
	long (*round_rate)(struct clk *clk, unsigned long rate);
};

#define SH_CLK_DIV_MSK(div)	((1 << (div)) - 1)
#define SH_CLK_DIV4_MSK		SH_CLK_DIV_MSK(4)
#define SH_CLK_DIV6_MSK		SH_CLK_DIV_MSK(6)

struct clk {
	struct list_head	node;
	struct clk		*parent;
	struct clk		**parent_table;	/* list of parents to */
	unsigned short		parent_num;	/* choose between */
	unsigned char		src_shift;	/* source clock field in the */
	unsigned char		src_width;	/* configuration register */
	struct sh_clk_ops	*ops;

	struct list_head	children;
	struct list_head	sibling;	/* node for children */

	int			usecount;

	unsigned long		rate;
	unsigned long		flags;

	void __iomem		*enable_reg;
	unsigned int		enable_bit;
	void __iomem		*mapped_reg;

	unsigned int		div_mask;
	unsigned long		arch_flags;
	void			*priv;
	struct clk_mapping	*mapping;
	struct cpufreq_frequency_table *freq_table;
	unsigned int		nr_freqs;
};

#define CLK_ENABLE_ON_INIT	BIT(0)

#define CLK_ENABLE_REG_32BIT	BIT(1)	/* default access size */
#define CLK_ENABLE_REG_16BIT	BIT(2)
#define CLK_ENABLE_REG_8BIT	BIT(3)

#define CLK_MASK_DIV_ON_DISABLE	BIT(4)

#define CLK_ENABLE_REG_MASK	(CLK_ENABLE_REG_32BIT | \
				 CLK_ENABLE_REG_16BIT | \
				 CLK_ENABLE_REG_8BIT)

/* drivers/sh/clk.c */
unsigned long followparent_recalc(struct clk *);
void recalculate_root_clocks(void);
void propagate_rate(struct clk *);
int clk_reparent(struct clk *child, struct clk *parent);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
void clk_enable_init_clocks(void);

struct clk_div_mult_table {
	unsigned int *divisors;
	unsigned int nr_divisors;
	unsigned int *multipliers;
	unsigned int nr_multipliers;
};

struct cpufreq_frequency_table;
void clk_rate_table_build(struct clk *clk,
			  struct cpufreq_frequency_table *freq_table,
			  int nr_freqs,
			  struct clk_div_mult_table *src_table,
			  unsigned long *bitmap);

long clk_rate_table_round(struct clk *clk,
			  struct cpufreq_frequency_table *freq_table,
			  unsigned long rate);

int clk_rate_table_find(struct clk *clk,
			struct cpufreq_frequency_table *freq_table,
			unsigned long rate);

long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
			      unsigned int div_max, unsigned long rate);

long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
			       unsigned int mult_max, unsigned long rate);

long clk_round_parent(struct clk *clk, unsigned long target,
		      unsigned long *best_freq, unsigned long *parent_freq,
		      unsigned int div_min, unsigned int div_max);

#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags)		\
{									\
	.parent		= _parent,					\
	.enable_reg	= (void __iomem *)_enable_reg,			\
	.enable_bit	= _enable_bit,					\
	.flags		= _flags,					\
}

#define SH_CLK_MSTP32(_p, _r, _b, _f)					\
	SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)

#define SH_CLK_MSTP16(_p, _r, _b, _f)					\
	SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)

#define SH_CLK_MSTP8(_p, _r, _b, _f)					\
	SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)

int sh_clk_mstp_register(struct clk *clks, int nr);

/*
 * MSTP registration never really cared about access size, despite the
 * original enable/disable pairs assuming a 32-bit access. Clocks are
 * responsible for defining their access sizes either directly or via the
 * clock definition wrappers.
 */
static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
{
	return sh_clk_mstp_register(clks, nr);
}

#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags)	\
{								\
	.parent = _parent,					\
	.enable_reg = (void __iomem *)_reg,			\
	.enable_bit = _shift,					\
	.arch_flags = _div_bitmap,				\
	.div_mask = SH_CLK_DIV4_MSK,				\
	.flags = _flags,					\
}

struct clk_div_table {
	struct clk_div_mult_table *div_mult_table;
	void (*kick)(struct clk *clk);
};

#define clk_div4_table clk_div_table

int sh_clk_div4_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);
int sh_clk_div4_enable_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);
int sh_clk_div4_reparent_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);

#define SH_CLK_DIV6_EXT(_reg, _flags, _parents,			\
			_num_parents, _src_shift, _src_width)	\
{								\
	.enable_reg = (void __iomem *)_reg,			\
	.enable_bit = 0, /* unused */				\
	.flags = _flags | CLK_MASK_DIV_ON_DISABLE,		\
	.div_mask = SH_CLK_DIV6_MSK,				\
	.parent_table = _parents,				\
	.parent_num = _num_parents,				\
	.src_shift = _src_shift,				\
	.src_width = _src_width,				\
}

#define SH_CLK_DIV6(_parent, _reg, _flags)			\
{								\
	.parent		= _parent,				\
	.enable_reg	= (void __iomem *)_reg,			\
	.enable_bit	= 0,	/* unused */			\
	.div_mask	= SH_CLK_DIV6_MSK,			\
	.flags		= _flags | CLK_MASK_DIV_ON_DISABLE,	\
}

int sh_clk_div6_register(struct clk *clks, int nr);
int sh_clk_div6_reparent_register(struct clk *clks, int nr);

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }

/* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
#define SH_CLK_FSIDIV(_reg, _parent)		\
{						\
	.enable_reg = (void __iomem *)_reg,	\
	.parent		= _parent,		\
}

int sh_clk_fsidiv_register(struct clk *clks, int nr);

#endif /* __SH_CLOCK_H */
Commit	Line	Data
d28bdf05 MD	1	#ifndef __SH_CLOCK_H
	2	#define __SH_CLOCK_H
	3
	4	#include <linux/list.h>
	5	#include <linux/seq_file.h>
	6	#include <linux/cpufreq.h>
28085bc5 PM	7	#include <linux/types.h>
28085bc5 PM	8	#include <linux/kref.h>
d28bdf05 MD	9	#include <linux/clk.h>
	10	#include <linux/err.h>
	11
	12	struct clk;
	13
28085bc5 PM	14	struct clk_mapping {
	15	phys_addr_t phys;
	16	void __iomem *base;
	17	unsigned long len;
	18	struct kref ref;
	19	};
	20
84c36ffd	21	struct sh_clk_ops {
549015c3	22	#ifdef CONFIG_SH_CLK_CPG_LEGACY
d28bdf05	23	void (init)(struct clk clk);
549015c3	24	#endif
d28bdf05 MD	25	int (enable)(struct clk clk);
	26	void (disable)(struct clk clk);
	27	unsigned long (recalc)(struct clk clk);
35a96c73	28	int (set_rate)(struct clk clk, unsigned long rate);
d28bdf05 MD	29	int (set_parent)(struct clk clk, struct clk *parent);
	30	long (round_rate)(struct clk clk, unsigned long rate);
	31	};
	32
1111cc1e PM	33	#define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1)
	34	#define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4)
	35	#define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6)
	36
d28bdf05 MD	37	struct clk {
d28bdf05 MD	38	struct list_head node;
d28bdf05	39	struct clk *parent;
b5272b50 GL	40	struct clk *parent_table; / list of parents to */
	41	unsigned short parent_num; /* choose between */
	42	unsigned char src_shift; /* source clock field in the */
	43	unsigned char src_width; /* configuration register */
84c36ffd	44	struct sh_clk_ops *ops;
d28bdf05 MD	45
	46	struct list_head children;
	47	struct list_head sibling; /* node for children */
	48
	49	int usecount;
	50
	51	unsigned long rate;
	52	unsigned long flags;
	53
	54	void __iomem *enable_reg;
	55	unsigned int enable_bit;
eda2030a	56	void __iomem *mapped_reg;
d28bdf05	57
1111cc1e	58	unsigned int div_mask;
d28bdf05 MD	59	unsigned long arch_flags;
d28bdf05 MD	60	void *priv;
28085bc5	61	struct clk_mapping *mapping;
d28bdf05	62	struct cpufreq_frequency_table *freq_table;
f586903d	63	unsigned int nr_freqs;
d28bdf05 MD	64	};
d28bdf05 MD	65
4d6ddb08 PM	66	#define CLK_ENABLE_ON_INIT BIT(0)
	67
	68	#define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */
	69	#define CLK_ENABLE_REG_16BIT BIT(2)
	70	#define CLK_ENABLE_REG_8BIT BIT(3)
	71
764f4e4e PM	72	#define CLK_MASK_DIV_ON_DISABLE BIT(4)
764f4e4e PM	73
4d6ddb08 PM	74	#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT \| \
	75	CLK_ENABLE_REG_16BIT \| \
	76	CLK_ENABLE_REG_8BIT)
d28bdf05	77
a71ba096	78	/* drivers/sh/clk.c */
d28bdf05 MD	79	unsigned long followparent_recalc(struct clk *);
	80	void recalculate_root_clocks(void);
	81	void propagate_rate(struct clk *);
	82	int clk_reparent(struct clk child, struct clk parent);
	83	int clk_register(struct clk *);
	84	void clk_unregister(struct clk *);
8b5ee113	85	void clk_enable_init_clocks(void);
d28bdf05	86
d28bdf05 MD	87	struct clk_div_mult_table {
	88	unsigned int *divisors;
	89	unsigned int nr_divisors;
	90	unsigned int *multipliers;
	91	unsigned int nr_multipliers;
	92	};
	93
	94	struct cpufreq_frequency_table;
	95	void clk_rate_table_build(struct clk *clk,
	96	struct cpufreq_frequency_table *freq_table,
	97	int nr_freqs,
	98	struct clk_div_mult_table *src_table,
	99	unsigned long *bitmap);
	100
	101	long clk_rate_table_round(struct clk *clk,
	102	struct cpufreq_frequency_table *freq_table,
	103	unsigned long rate);
	104
	105	int clk_rate_table_find(struct clk *clk,
	106	struct cpufreq_frequency_table *freq_table,
	107	unsigned long rate);
	108
8e122db6 PM	109	long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
	110	unsigned int div_max, unsigned long rate);
	111
dd2c0ca1 KM	112	long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
	113	unsigned int mult_max, unsigned long rate);
	114
6af26c6c GL	115	long clk_round_parent(struct clk *clk, unsigned long target,
	116	unsigned long best_freq, unsigned long parent_freq,
	117	unsigned int div_min, unsigned int div_max);
	118
4d6ddb08	119	#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \
d28bdf05 MD	120	{ \
	121	.parent = _parent, \
	122	.enable_reg = (void __iomem *)_enable_reg, \
	123	.enable_bit = _enable_bit, \
	124	.flags = _flags, \
	125	}
	126
4d6ddb08 PM	127	#define SH_CLK_MSTP32(_p, _r, _b, _f) \
	128	SH_CLK_MSTP(_p, _r, _b, _f \| CLK_ENABLE_REG_32BIT)
	129
	130	#define SH_CLK_MSTP16(_p, _r, _b, _f) \
	131	SH_CLK_MSTP(_p, _r, _b, _f \| CLK_ENABLE_REG_16BIT)
	132
	133	#define SH_CLK_MSTP8(_p, _r, _b, _f) \
	134	SH_CLK_MSTP(_p, _r, _b, _f \| CLK_ENABLE_REG_8BIT)
	135
	136	int sh_clk_mstp_register(struct clk *clks, int nr);
	137
	138	/*
	139	* MSTP registration never really cared about access size, despite the
	140	* original enable/disable pairs assuming a 32-bit access. Clocks are
	141	* responsible for defining their access sizes either directly or via the
	142	* clock definition wrappers.
	143	*/
	144	static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
	145	{
	146	return sh_clk_mstp_register(clks, nr);
	147	}
d28bdf05 MD	148
	149	#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
	150	{ \
	151	.parent = _parent, \
	152	.enable_reg = (void __iomem *)_reg, \
	153	.enable_bit = _shift, \
	154	.arch_flags = _div_bitmap, \
1111cc1e	155	.div_mask = SH_CLK_DIV4_MSK, \
d28bdf05 MD	156	.flags = _flags, \
	157	}
	158
a60977a5	159	struct clk_div_table {
d28bdf05 MD	160	struct clk_div_mult_table *div_mult_table;
	161	void (kick)(struct clk clk);
	162	};
	163
a60977a5 PM	164	#define clk_div4_table clk_div_table
a60977a5 PM	165
d28bdf05 MD	166	int sh_clk_div4_register(struct clk *clks, int nr,
	167	struct clk_div4_table *table);
	168	int sh_clk_div4_enable_register(struct clk *clks, int nr,
	169	struct clk_div4_table *table);
	170	int sh_clk_div4_reparent_register(struct clk *clks, int nr,
	171	struct clk_div4_table *table);
	172
56242a1f	173	#define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
b3dd51a8 GL	174	_num_parents, _src_shift, _src_width) \
b3dd51a8 GL	175	{ \
b3dd51a8	176	.enable_reg = (void __iomem *)_reg, \
75f5f8a5	177	.enable_bit = 0, /* unused */ \
764f4e4e	178	.flags = _flags \| CLK_MASK_DIV_ON_DISABLE, \
1111cc1e	179	.div_mask = SH_CLK_DIV6_MSK, \
b3dd51a8 GL	180	.parent_table = _parents, \
	181	.parent_num = _num_parents, \
	182	.src_shift = _src_shift, \
	183	.src_width = _src_width, \
d28bdf05 MD	184	}
d28bdf05 MD	185
b3dd51a8	186	#define SH_CLK_DIV6(_parent, _reg, _flags) \
56242a1f KM	187	{ \
	188	.parent = _parent, \
	189	.enable_reg = (void __iomem *)_reg, \
75f5f8a5	190	.enable_bit = 0, /* unused */ \
1111cc1e	191	.div_mask = SH_CLK_DIV6_MSK, \
764f4e4e	192	.flags = _flags \| CLK_MASK_DIV_ON_DISABLE, \
56242a1f	193	}
b3dd51a8	194
d28bdf05	195	int sh_clk_div6_register(struct clk *clks, int nr);
b3dd51a8	196	int sh_clk_div6_reparent_register(struct clk *clks, int nr);
d28bdf05	197
1522043b KM	198	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
	199	#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
	200	#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
	201
9d626ecc KM	202	/* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
	203	#define SH_CLK_FSIDIV(_reg, _parent) \
	204	{ \
	205	.enable_reg = (void __iomem *)_reg, \
	206	.parent = _parent, \
	207	}
	208
	209	int sh_clk_fsidiv_register(struct clk *clks, int nr);
	210
d28bdf05	211	#endif /* __SH_CLOCK_H */