[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / nvme.h

/*
 * Definitions for the NVM Express interface
 * Copyright (c) 2011, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 */

#ifndef _LINUX_NVME_H
#define _LINUX_NVME_H

#include <linux/types.h>

struct nvme_bar {
	__u64			cap;	/* Controller Capabilities */
	__u32			vs;	/* Version */
	__u32			intms;	/* Interrupt Mask Set */
	__u32			intmc;	/* Interrupt Mask Clear */
	__u32			cc;	/* Controller Configuration */
	__u32			rsvd1;	/* Reserved */
	__u32			csts;	/* Controller Status */
	__u32			rsvd2;	/* Reserved */
	__u32			aqa;	/* Admin Queue Attributes */
	__u64			asq;	/* Admin SQ Base Address */
	__u64			acq;	/* Admin CQ Base Address */
};

#define NVME_CAP_TIMEOUT(cap)	(((cap) >> 24) & 0xff)
#define NVME_CAP_STRIDE(cap)	(((cap) >> 32) & 0xf)
#define NVME_CAP_MPSMIN(cap)	(((cap) >> 48) & 0xf)

enum {
	NVME_CC_ENABLE		= 1 << 0,
	NVME_CC_CSS_NVM		= 0 << 4,
	NVME_CC_MPS_SHIFT	= 7,
	NVME_CC_ARB_RR		= 0 << 11,
	NVME_CC_ARB_WRRU	= 1 << 11,
	NVME_CC_ARB_VS		= 7 << 11,
	NVME_CC_SHN_NONE	= 0 << 14,
	NVME_CC_SHN_NORMAL	= 1 << 14,
	NVME_CC_SHN_ABRUPT	= 2 << 14,
	NVME_CC_IOSQES		= 6 << 16,
	NVME_CC_IOCQES		= 4 << 20,
	NVME_CSTS_RDY		= 1 << 0,
	NVME_CSTS_CFS		= 1 << 1,
	NVME_CSTS_SHST_NORMAL	= 0 << 2,
	NVME_CSTS_SHST_OCCUR	= 1 << 2,
	NVME_CSTS_SHST_CMPLT	= 2 << 2,
};

struct nvme_id_power_state {
	__le16			max_power;	/* centiwatts */
	__u16			rsvd2;
	__le32			entry_lat;	/* microseconds */
	__le32			exit_lat;	/* microseconds */
	__u8			read_tput;
	__u8			read_lat;
	__u8			write_tput;
	__u8			write_lat;
	__u8			rsvd16[16];
};

#define NVME_VS(major, minor)	(major << 16 | minor)

struct nvme_id_ctrl {
	__le16			vid;
	__le16			ssvid;
	char			sn[20];
	char			mn[40];
	char			fr[8];
	__u8			rab;
	__u8			ieee[3];
	__u8			mic;
	__u8			mdts;
	__u8			rsvd78[178];
	__le16			oacs;
	__u8			acl;
	__u8			aerl;
	__u8			frmw;
	__u8			lpa;
	__u8			elpe;
	__u8			npss;
	__u8			rsvd264[248];
	__u8			sqes;
	__u8			cqes;
	__u8			rsvd514[2];
	__le32			nn;
	__le16			oncs;
	__le16			fuses;
	__u8			fna;
	__u8			vwc;
	__le16			awun;
	__le16			awupf;
	__u8			rsvd530[1518];
	struct nvme_id_power_state	psd[32];
	__u8			vs[1024];
};

struct nvme_lbaf {
	__le16			ms;
	__u8			ds;
	__u8			rp;
};

struct nvme_id_ns {
	__le64			nsze;
	__le64			ncap;
	__le64			nuse;
	__u8			nsfeat;
	__u8			nlbaf;
	__u8			flbas;
	__u8			mc;
	__u8			dpc;
	__u8			dps;
	__u8			rsvd30[98];
	struct nvme_lbaf	lbaf[16];
	__u8			rsvd192[192];
	__u8			vs[3712];
};

enum {
	NVME_NS_FEAT_THIN	= 1 << 0,
	NVME_LBAF_RP_BEST	= 0,
	NVME_LBAF_RP_BETTER	= 1,
	NVME_LBAF_RP_GOOD	= 2,
	NVME_LBAF_RP_DEGRADED	= 3,
};

struct nvme_lba_range_type {
	__u8			type;
	__u8			attributes;
	__u8			rsvd2[14];
	__u64			slba;
	__u64			nlb;
	__u8			guid[16];
	__u8			rsvd48[16];
};

enum {
	NVME_LBART_TYPE_FS	= 0x01,
	NVME_LBART_TYPE_RAID	= 0x02,
	NVME_LBART_TYPE_CACHE	= 0x03,
	NVME_LBART_TYPE_SWAP	= 0x04,

	NVME_LBART_ATTRIB_TEMP	= 1 << 0,
	NVME_LBART_ATTRIB_HIDE	= 1 << 1,
};

/* I/O commands */

enum nvme_opcode {
	nvme_cmd_flush		= 0x00,
	nvme_cmd_write		= 0x01,
	nvme_cmd_read		= 0x02,
	nvme_cmd_write_uncor	= 0x04,
	nvme_cmd_compare	= 0x05,
	nvme_cmd_dsm		= 0x09,
};

struct nvme_common_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u32			cdw2[2];
	__le64			metadata;
	__le64			prp1;
	__le64			prp2;
	__u32			cdw10[6];
};

struct nvme_rw_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2;
	__le64			metadata;
	__le64			prp1;
	__le64			prp2;
	__le64			slba;
	__le16			length;
	__le16			control;
	__le32			dsmgmt;
	__le32			reftag;
	__le16			apptag;
	__le16			appmask;
};

enum {
	NVME_RW_LR			= 1 << 15,
	NVME_RW_FUA			= 1 << 14,
	NVME_RW_DSM_FREQ_UNSPEC		= 0,
	NVME_RW_DSM_FREQ_TYPICAL	= 1,
	NVME_RW_DSM_FREQ_RARE		= 2,
	NVME_RW_DSM_FREQ_READS		= 3,
	NVME_RW_DSM_FREQ_WRITES		= 4,
	NVME_RW_DSM_FREQ_RW		= 5,
	NVME_RW_DSM_FREQ_ONCE		= 6,
	NVME_RW_DSM_FREQ_PREFETCH	= 7,
	NVME_RW_DSM_FREQ_TEMP		= 8,
	NVME_RW_DSM_LATENCY_NONE	= 0 << 4,
	NVME_RW_DSM_LATENCY_IDLE	= 1 << 4,
	NVME_RW_DSM_LATENCY_NORM	= 2 << 4,
	NVME_RW_DSM_LATENCY_LOW		= 3 << 4,
	NVME_RW_DSM_SEQ_REQ		= 1 << 6,
	NVME_RW_DSM_COMPRESSED		= 1 << 7,
};

/* Admin commands */

enum nvme_admin_opcode {
	nvme_admin_delete_sq		= 0x00,
	nvme_admin_create_sq		= 0x01,
	nvme_admin_get_log_page		= 0x02,
	nvme_admin_delete_cq		= 0x04,
	nvme_admin_create_cq		= 0x05,
	nvme_admin_identify		= 0x06,
	nvme_admin_abort_cmd		= 0x08,
	nvme_admin_set_features		= 0x09,
	nvme_admin_get_features		= 0x0a,
	nvme_admin_async_event		= 0x0c,
	nvme_admin_activate_fw		= 0x10,
	nvme_admin_download_fw		= 0x11,
	nvme_admin_format_nvm		= 0x80,
	nvme_admin_security_send	= 0x81,
	nvme_admin_security_recv	= 0x82,
};

enum {
	NVME_QUEUE_PHYS_CONTIG	= (1 << 0),
	NVME_CQ_IRQ_ENABLED	= (1 << 1),
	NVME_SQ_PRIO_URGENT	= (0 << 1),
	NVME_SQ_PRIO_HIGH	= (1 << 1),
	NVME_SQ_PRIO_MEDIUM	= (2 << 1),
	NVME_SQ_PRIO_LOW	= (3 << 1),
	NVME_FEAT_ARBITRATION	= 0x01,
	NVME_FEAT_POWER_MGMT	= 0x02,
	NVME_FEAT_LBA_RANGE	= 0x03,
	NVME_FEAT_TEMP_THRESH	= 0x04,
	NVME_FEAT_ERR_RECOVERY	= 0x05,
	NVME_FEAT_VOLATILE_WC	= 0x06,
	NVME_FEAT_NUM_QUEUES	= 0x07,
	NVME_FEAT_IRQ_COALESCE	= 0x08,
	NVME_FEAT_IRQ_CONFIG	= 0x09,
	NVME_FEAT_WRITE_ATOMIC	= 0x0a,
	NVME_FEAT_ASYNC_EVENT	= 0x0b,
	NVME_FEAT_SW_PROGRESS	= 0x0c,
};

struct nvme_identify {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			cns;
	__u32			rsvd11[5];
};

struct nvme_features {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			fid;
	__le32			dword11;
	__u32			rsvd12[4];
};

struct nvme_create_cq {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__u64			rsvd8;
	__le16			cqid;
	__le16			qsize;
	__le16			cq_flags;
	__le16			irq_vector;
	__u32			rsvd12[4];
};

struct nvme_create_sq {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__u64			rsvd8;
	__le16			sqid;
	__le16			qsize;
	__le16			sq_flags;
	__le16			cqid;
	__u32			rsvd12[4];
};

struct nvme_delete_queue {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[9];
	__le16			qid;
	__u16			rsvd10;
	__u32			rsvd11[5];
};

struct nvme_download_firmware {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__le64			prp2;
	__le32			numd;
	__le32			offset;
	__u32			rsvd12[4];
};

struct nvme_command {
	union {
		struct nvme_common_command common;
		struct nvme_rw_command rw;
		struct nvme_identify identify;
		struct nvme_features features;
		struct nvme_create_cq create_cq;
		struct nvme_create_sq create_sq;
		struct nvme_delete_queue delete_queue;
		struct nvme_download_firmware dlfw;
	};
};

enum {
	NVME_SC_SUCCESS			= 0x0,
	NVME_SC_INVALID_OPCODE		= 0x1,
	NVME_SC_INVALID_FIELD		= 0x2,
	NVME_SC_CMDID_CONFLICT		= 0x3,
	NVME_SC_DATA_XFER_ERROR		= 0x4,
	NVME_SC_POWER_LOSS		= 0x5,
	NVME_SC_INTERNAL		= 0x6,
	NVME_SC_ABORT_REQ		= 0x7,
	NVME_SC_ABORT_QUEUE		= 0x8,
	NVME_SC_FUSED_FAIL		= 0x9,
	NVME_SC_FUSED_MISSING		= 0xa,
	NVME_SC_INVALID_NS		= 0xb,
	NVME_SC_LBA_RANGE		= 0x80,
	NVME_SC_CAP_EXCEEDED		= 0x81,
	NVME_SC_NS_NOT_READY		= 0x82,
	NVME_SC_CQ_INVALID		= 0x100,
	NVME_SC_QID_INVALID		= 0x101,
	NVME_SC_QUEUE_SIZE		= 0x102,
	NVME_SC_ABORT_LIMIT		= 0x103,
	NVME_SC_ABORT_MISSING		= 0x104,
	NVME_SC_ASYNC_LIMIT		= 0x105,
	NVME_SC_FIRMWARE_SLOT		= 0x106,
	NVME_SC_FIRMWARE_IMAGE		= 0x107,
	NVME_SC_INVALID_VECTOR		= 0x108,
	NVME_SC_INVALID_LOG_PAGE	= 0x109,
	NVME_SC_INVALID_FORMAT		= 0x10a,
	NVME_SC_BAD_ATTRIBUTES		= 0x180,
	NVME_SC_WRITE_FAULT		= 0x280,
	NVME_SC_READ_ERROR		= 0x281,
	NVME_SC_GUARD_CHECK		= 0x282,
	NVME_SC_APPTAG_CHECK		= 0x283,
	NVME_SC_REFTAG_CHECK		= 0x284,
	NVME_SC_COMPARE_FAILED		= 0x285,
	NVME_SC_ACCESS_DENIED		= 0x286,
};

struct nvme_completion {
	__le32	result;		/* Used by admin commands to return data */
	__u32	rsvd;
	__le16	sq_head;	/* how much of this queue may be reclaimed */
	__le16	sq_id;		/* submission queue that generated this entry */
	__u16	command_id;	/* of the command which completed */
	__le16	status;		/* did the command fail, and if so, why? */
};

struct nvme_user_io {
	__u8	opcode;
	__u8	flags;
	__u16	control;
	__u16	nblocks;
	__u16	rsvd;
	__u64	metadata;
	__u64	addr;
	__u64	slba;
	__u32	dsmgmt;
	__u32	reftag;
	__u16	apptag;
	__u16	appmask;
};

struct nvme_admin_cmd {
	__u8	opcode;
	__u8	flags;
	__u16	rsvd1;
	__u32	nsid;
	__u32	cdw2;
	__u32	cdw3;
	__u64	metadata;
	__u64	addr;
	__u32	metadata_len;
	__u32	data_len;
	__u32	cdw10;
	__u32	cdw11;
	__u32	cdw12;
	__u32	cdw13;
	__u32	cdw14;
	__u32	cdw15;
	__u32	timeout_ms;
	__u32	result;
};

#define NVME_IOCTL_ID		_IO('N', 0x40)
#define NVME_IOCTL_ADMIN_CMD	_IOWR('N', 0x41, struct nvme_admin_cmd)
#define NVME_IOCTL_SUBMIT_IO	_IOW('N', 0x42, struct nvme_user_io)

#endif /* _LINUX_NVME_H */
Commit	Line	Data
b60503ba MW	1	/*
	2	* Definitions for the NVM Express interface
	3	* Copyright (c) 2011, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	17	*/
	18
	19	#ifndef _LINUX_NVME_H
	20	#define _LINUX_NVME_H
	21
	22	#include <linux/types.h>
	23
	24	struct nvme_bar {
	25	__u64 cap; /* Controller Capabilities */
	26	__u32 vs; /* Version */
897cfe1c MW	27	__u32 intms; /* Interrupt Mask Set */
897cfe1c MW	28	__u32 intmc; /* Interrupt Mask Clear */
b60503ba	29	__u32 cc; /* Controller Configuration */
897cfe1c	30	__u32 rsvd1; /* Reserved */
b60503ba	31	__u32 csts; /* Controller Status */
897cfe1c	32	__u32 rsvd2; /* Reserved */
b60503ba MW	33	__u32 aqa; /* Admin Queue Attributes */
	34	__u64 asq; /* Admin SQ Base Address */
	35	__u64 acq; /* Admin CQ Base Address */
	36	};
	37
22605f96	38	#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e	39	#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
8fc23e03	40	#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
22605f96	41
b60503ba MW	42	enum {
	43	NVME_CC_ENABLE = 1 << 0,
	44	NVME_CC_CSS_NVM = 0 << 4,
	45	NVME_CC_MPS_SHIFT = 7,
	46	NVME_CC_ARB_RR = 0 << 11,
	47	NVME_CC_ARB_WRRU = 1 << 11,
7f53f9d2 MW	48	NVME_CC_ARB_VS = 7 << 11,
	49	NVME_CC_SHN_NONE = 0 << 14,
	50	NVME_CC_SHN_NORMAL = 1 << 14,
	51	NVME_CC_SHN_ABRUPT = 2 << 14,
	52	NVME_CC_IOSQES = 6 << 16,
	53	NVME_CC_IOCQES = 4 << 20,
b60503ba MW	54	NVME_CSTS_RDY = 1 << 0,
	55	NVME_CSTS_CFS = 1 << 1,
	56	NVME_CSTS_SHST_NORMAL = 0 << 2,
	57	NVME_CSTS_SHST_OCCUR = 1 << 2,
	58	NVME_CSTS_SHST_CMPLT = 2 << 2,
	59	};
	60
010e646b MW	61	struct nvme_id_power_state {
	62	__le16 max_power; /* centiwatts */
	63	__u16 rsvd2;
	64	__le32 entry_lat; /* microseconds */
	65	__le32 exit_lat; /* microseconds */
	66	__u8 read_tput;
	67	__u8 read_lat;
	68	__u8 write_tput;
	69	__u8 write_lat;
	70	__u8 rsvd16[16];
	71	};
	72
b60503ba MW	73	#define NVME_VS(major, minor) (major << 16 \| minor)
	74
	75	struct nvme_id_ctrl {
	76	__le16 vid;
	77	__le16 ssvid;
	78	char sn[20];
	79	char mn[40];
	80	char fr[8];
b60503ba	81	__u8 rab;
010e646b MW	82	__u8 ieee[3];
	83	__u8 mic;
	84	__u8 mdts;
	85	__u8 rsvd78[178];
b60503ba MW	86	__le16 oacs;
	87	__u8 acl;
	88	__u8 aerl;
	89	__u8 frmw;
	90	__u8 lpa;
	91	__u8 elpe;
	92	__u8 npss;
	93	__u8 rsvd264[248];
010e646b MW	94	__u8 sqes;
	95	__u8 cqes;
	96	__u8 rsvd514[2];
	97	__le32 nn;
b60503ba MW	98	__le16 oncs;
	99	__le16 fuses;
	100	__u8 fna;
	101	__u8 vwc;
	102	__le16 awun;
	103	__le16 awupf;
010e646b MW	104	__u8 rsvd530[1518];
010e646b MW	105	struct nvme_id_power_state psd[32];
b60503ba MW	106	__u8 vs[1024];
	107	};
	108
	109	struct nvme_lbaf {
	110	__le16 ms;
	111	__u8 ds;
	112	__u8 rp;
	113	};
	114
	115	struct nvme_id_ns {
	116	__le64 nsze;
	117	__le64 ncap;
	118	__le64 nuse;
	119	__u8 nsfeat;
	120	__u8 nlbaf;
	121	__u8 flbas;
	122	__u8 mc;
	123	__u8 dpc;
	124	__u8 dps;
	125	__u8 rsvd30[98];
	126	struct nvme_lbaf lbaf[16];
	127	__u8 rsvd192[192];
	128	__u8 vs[3712];
	129	};
	130
	131	enum {
	132	NVME_NS_FEAT_THIN = 1 << 0,
	133	NVME_LBAF_RP_BEST = 0,
	134	NVME_LBAF_RP_BETTER = 1,
	135	NVME_LBAF_RP_GOOD = 2,
	136	NVME_LBAF_RP_DEGRADED = 3,
	137	};
	138
	139	struct nvme_lba_range_type {
	140	__u8 type;
	141	__u8 attributes;
	142	__u8 rsvd2[14];
	143	__u64 slba;
	144	__u64 nlb;
	145	__u8 guid[16];
	146	__u8 rsvd48[16];
	147	};
	148
	149	enum {
	150	NVME_LBART_TYPE_FS = 0x01,
	151	NVME_LBART_TYPE_RAID = 0x02,
	152	NVME_LBART_TYPE_CACHE = 0x03,
	153	NVME_LBART_TYPE_SWAP = 0x04,
	154
	155	NVME_LBART_ATTRIB_TEMP = 1 << 0,
	156	NVME_LBART_ATTRIB_HIDE = 1 << 1,
	157	};
	158
	159	/* I/O commands */
	160
	161	enum nvme_opcode {
	162	nvme_cmd_flush = 0x00,
	163	nvme_cmd_write = 0x01,
	164	nvme_cmd_read = 0x02,
	165	nvme_cmd_write_uncor = 0x04,
	166	nvme_cmd_compare = 0x05,
	167	nvme_cmd_dsm = 0x09,
	168	};
	169
7b4fe9b1 MW	170	struct nvme_common_command {
	171	__u8 opcode;
	172	__u8 flags;
	173	__u16 command_id;
	174	__le32 nsid;
6bbf1acd	175	__u32 cdw2[2];
7b4fe9b1 MW	176	__le64 metadata;
	177	__le64 prp1;
	178	__le64 prp2;
6bbf1acd	179	__u32 cdw10[6];
7b4fe9b1 MW	180	};
7b4fe9b1 MW	181
b60503ba MW	182	struct nvme_rw_command {
	183	__u8 opcode;
	184	__u8 flags;
	185	__u16 command_id;
	186	__le32 nsid;
	187	__u64 rsvd2;
	188	__le64 metadata;
	189	__le64 prp1;
	190	__le64 prp2;
	191	__le64 slba;
	192	__le16 length;
	193	__le16 control;
	194	__le32 dsmgmt;
	195	__le32 reftag;
	196	__le16 apptag;
	197	__le16 appmask;
	198	};
	199
	200	enum {
	201	NVME_RW_LR = 1 << 15,
	202	NVME_RW_FUA = 1 << 14,
	203	NVME_RW_DSM_FREQ_UNSPEC = 0,
	204	NVME_RW_DSM_FREQ_TYPICAL = 1,
	205	NVME_RW_DSM_FREQ_RARE = 2,
	206	NVME_RW_DSM_FREQ_READS = 3,
	207	NVME_RW_DSM_FREQ_WRITES = 4,
	208	NVME_RW_DSM_FREQ_RW = 5,
	209	NVME_RW_DSM_FREQ_ONCE = 6,
	210	NVME_RW_DSM_FREQ_PREFETCH = 7,
	211	NVME_RW_DSM_FREQ_TEMP = 8,
	212	NVME_RW_DSM_LATENCY_NONE = 0 << 4,
	213	NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
	214	NVME_RW_DSM_LATENCY_NORM = 2 << 4,
	215	NVME_RW_DSM_LATENCY_LOW = 3 << 4,
	216	NVME_RW_DSM_SEQ_REQ = 1 << 6,
	217	NVME_RW_DSM_COMPRESSED = 1 << 7,
	218	};
	219
	220	/* Admin commands */
	221
	222	enum nvme_admin_opcode {
	223	nvme_admin_delete_sq = 0x00,
	224	nvme_admin_create_sq = 0x01,
2ddc4f74	225	nvme_admin_get_log_page = 0x02,
b60503ba MW	226	nvme_admin_delete_cq = 0x04,
	227	nvme_admin_create_cq = 0x05,
	228	nvme_admin_identify = 0x06,
	229	nvme_admin_abort_cmd = 0x08,
	230	nvme_admin_set_features = 0x09,
2ddc4f74	231	nvme_admin_get_features = 0x0a,
b60503ba	232	nvme_admin_async_event = 0x0c,
2ddc4f74 KW	233	nvme_admin_activate_fw = 0x10,
	234	nvme_admin_download_fw = 0x11,
	235	nvme_admin_format_nvm = 0x80,
	236	nvme_admin_security_send = 0x81,
	237	nvme_admin_security_recv = 0x82,
b60503ba MW	238	};
	239
	240	enum {
	241	NVME_QUEUE_PHYS_CONTIG = (1 << 0),
	242	NVME_CQ_IRQ_ENABLED = (1 << 1),
	243	NVME_SQ_PRIO_URGENT = (0 << 1),
	244	NVME_SQ_PRIO_HIGH = (1 << 1),
	245	NVME_SQ_PRIO_MEDIUM = (2 << 1),
	246	NVME_SQ_PRIO_LOW = (3 << 1),
	247	NVME_FEAT_ARBITRATION = 0x01,
	248	NVME_FEAT_POWER_MGMT = 0x02,
	249	NVME_FEAT_LBA_RANGE = 0x03,
	250	NVME_FEAT_TEMP_THRESH = 0x04,
	251	NVME_FEAT_ERR_RECOVERY = 0x05,
	252	NVME_FEAT_VOLATILE_WC = 0x06,
	253	NVME_FEAT_NUM_QUEUES = 0x07,
	254	NVME_FEAT_IRQ_COALESCE = 0x08,
	255	NVME_FEAT_IRQ_CONFIG = 0x09,
	256	NVME_FEAT_WRITE_ATOMIC = 0x0a,
	257	NVME_FEAT_ASYNC_EVENT = 0x0b,
	258	NVME_FEAT_SW_PROGRESS = 0x0c,
	259	};
	260
	261	struct nvme_identify {
	262	__u8 opcode;
	263	__u8 flags;
	264	__u16 command_id;
	265	__le32 nsid;
	266	__u64 rsvd2[2];
	267	__le64 prp1;
	268	__le64 prp2;
	269	__le32 cns;
	270	__u32 rsvd11[5];
	271	};
	272
	273	struct nvme_features {
	274	__u8 opcode;
	275	__u8 flags;
	276	__u16 command_id;
	277	__le32 nsid;
	278	__u64 rsvd2[2];
	279	__le64 prp1;
	280	__le64 prp2;
	281	__le32 fid;
	282	__le32 dword11;
	283	__u32 rsvd12[4];
	284	};
	285
	286	struct nvme_create_cq {
	287	__u8 opcode;
	288	__u8 flags;
	289	__u16 command_id;
6ee44cdc	290	__u32 rsvd1[5];
b60503ba MW	291	__le64 prp1;
	292	__u64 rsvd8;
	293	__le16 cqid;
	294	__le16 qsize;
	295	__le16 cq_flags;
	296	__le16 irq_vector;
	297	__u32 rsvd12[4];
	298	};
	299
	300	struct nvme_create_sq {
	301	__u8 opcode;
	302	__u8 flags;
	303	__u16 command_id;
6ee44cdc	304	__u32 rsvd1[5];
b60503ba MW	305	__le64 prp1;
	306	__u64 rsvd8;
	307	__le16 sqid;
	308	__le16 qsize;
	309	__le16 sq_flags;
	310	__le16 cqid;
6ee44cdc	311	__u32 rsvd12[4];
b60503ba MW	312	};
	313
	314	struct nvme_delete_queue {
	315	__u8 opcode;
	316	__u8 flags;
	317	__u16 command_id;
	318	__u32 rsvd1[9];
	319	__le16 qid;
6ee44cdc MW	320	__u16 rsvd10;
	321	__u32 rsvd11[5];
	322	};
	323
	324	struct nvme_download_firmware {
	325	__u8 opcode;
	326	__u8 flags;
	327	__u16 command_id;
	328	__u32 rsvd1[5];
	329	__le64 prp1;
	330	__le64 prp2;
	331	__le32 numd;
	332	__le32 offset;
	333	__u32 rsvd12[4];
b60503ba MW	334	};
b60503ba MW	335
b60503ba MW	336	struct nvme_command {
	337	union {
	338	struct nvme_common_command common;
	339	struct nvme_rw_command rw;
	340	struct nvme_identify identify;
	341	struct nvme_features features;
	342	struct nvme_create_cq create_cq;
	343	struct nvme_create_sq create_sq;
	344	struct nvme_delete_queue delete_queue;
6ee44cdc	345	struct nvme_download_firmware dlfw;
b60503ba MW	346	};
	347	};
	348
b60503ba MW	349	enum {
	350	NVME_SC_SUCCESS = 0x0,
	351	NVME_SC_INVALID_OPCODE = 0x1,
	352	NVME_SC_INVALID_FIELD = 0x2,
	353	NVME_SC_CMDID_CONFLICT = 0x3,
	354	NVME_SC_DATA_XFER_ERROR = 0x4,
	355	NVME_SC_POWER_LOSS = 0x5,
	356	NVME_SC_INTERNAL = 0x6,
	357	NVME_SC_ABORT_REQ = 0x7,
	358	NVME_SC_ABORT_QUEUE = 0x8,
	359	NVME_SC_FUSED_FAIL = 0x9,
	360	NVME_SC_FUSED_MISSING = 0xa,
7a63e07b	361	NVME_SC_INVALID_NS = 0xb,
b60503ba MW	362	NVME_SC_LBA_RANGE = 0x80,
	363	NVME_SC_CAP_EXCEEDED = 0x81,
	364	NVME_SC_NS_NOT_READY = 0x82,
	365	NVME_SC_CQ_INVALID = 0x100,
	366	NVME_SC_QID_INVALID = 0x101,
	367	NVME_SC_QUEUE_SIZE = 0x102,
7a63e07b MW	368	NVME_SC_ABORT_LIMIT = 0x103,
	369	NVME_SC_ABORT_MISSING = 0x104,
	370	NVME_SC_ASYNC_LIMIT = 0x105,
	371	NVME_SC_FIRMWARE_SLOT = 0x106,
	372	NVME_SC_FIRMWARE_IMAGE = 0x107,
	373	NVME_SC_INVALID_VECTOR = 0x108,
	374	NVME_SC_INVALID_LOG_PAGE = 0x109,
	375	NVME_SC_INVALID_FORMAT = 0x10a,
	376	NVME_SC_BAD_ATTRIBUTES = 0x180,
b60503ba MW	377	NVME_SC_WRITE_FAULT = 0x280,
b60503ba MW	378	NVME_SC_READ_ERROR = 0x281,
7a63e07b MW	379	NVME_SC_GUARD_CHECK = 0x282,
	380	NVME_SC_APPTAG_CHECK = 0x283,
	381	NVME_SC_REFTAG_CHECK = 0x284,
	382	NVME_SC_COMPARE_FAILED = 0x285,
	383	NVME_SC_ACCESS_DENIED = 0x286,
b60503ba MW	384	};
	385
	386	struct nvme_completion {
	387	__le32 result; /* Used by admin commands to return data */
6ee44cdc	388	__u32 rsvd;
b60503ba MW	389	__le16 sq_head; /* how much of this queue may be reclaimed */
	390	__le16 sq_id; /* submission queue that generated this entry */
	391	__u16 command_id; /* of the command which completed */
	392	__le16 status; /* did the command fail, and if so, why? */
	393	};
	394
a53295b6 MW	395	struct nvme_user_io {
	396	__u8 opcode;
	397	__u8 flags;
	398	__u16 control;
6c7d4945 MW	399	__u16 nblocks;
6c7d4945 MW	400	__u16 rsvd;
a53295b6 MW	401	__u64 metadata;
	402	__u64 addr;
	403	__u64 slba;
a53295b6 MW	404	__u32 dsmgmt;
	405	__u32 reftag;
	406	__u16 apptag;
	407	__u16 appmask;
a53295b6 MW	408	};
a53295b6 MW	409
6bbf1acd MW	410	struct nvme_admin_cmd {
	411	__u8 opcode;
	412	__u8 flags;
	413	__u16 rsvd1;
	414	__u32 nsid;
	415	__u32 cdw2;
	416	__u32 cdw3;
	417	__u64 metadata;
6ee44cdc	418	__u64 addr;
6bbf1acd MW	419	__u32 metadata_len;
	420	__u32 data_len;
	421	__u32 cdw10;
	422	__u32 cdw11;
	423	__u32 cdw12;
	424	__u32 cdw13;
	425	__u32 cdw14;
	426	__u32 cdw15;
	427	__u32 timeout_ms;
	428	__u32 result;
6ee44cdc MW	429	};
6ee44cdc MW	430
6bbf1acd MW	431	#define NVME_IOCTL_ID _IO('N', 0x40)
	432	#define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
	433	#define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
b60503ba MW	434
b60503ba MW	435	#endif /* _LINUX_NVME_H */