[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / hpet.h

#ifndef	__HPET__
#define	__HPET__ 1

#include <uapi/linux/hpet.h>


/*
 * Offsets into HPET Registers
 */

struct hpet {
	u64 hpet_cap;		/* capabilities */
	u64 res0;		/* reserved */
	u64 hpet_config;	/* configuration */
	u64 res1;		/* reserved */
	u64 hpet_isr;		/* interrupt status reg */
	u64 res2[25];		/* reserved */
	union {			/* main counter */
		u64 _hpet_mc64;
		u32 _hpet_mc32;
		unsigned long _hpet_mc;
	} _u0;
	u64 res3;		/* reserved */
	struct hpet_timer {
		u64 hpet_config;	/* configuration/cap */
		union {		/* timer compare register */
			u64 _hpet_hc64;
			u32 _hpet_hc32;
			unsigned long _hpet_compare;
		} _u1;
		u64 hpet_fsb[2];	/* FSB route */
	} hpet_timers[1];
};

#define	hpet_mc		_u0._hpet_mc
#define	hpet_compare	_u1._hpet_compare

#define	HPET_MAX_TIMERS	(32)
#define	HPET_MAX_IRQ	(32)

/*
 * HPET general capabilities register
 */

#define	HPET_COUNTER_CLK_PERIOD_MASK	(0xffffffff00000000ULL)
#define	HPET_COUNTER_CLK_PERIOD_SHIFT	(32UL)
#define	HPET_VENDOR_ID_MASK		(0x00000000ffff0000ULL)
#define	HPET_VENDOR_ID_SHIFT		(16ULL)
#define	HPET_LEG_RT_CAP_MASK		(0x8000)
#define	HPET_COUNTER_SIZE_MASK		(0x2000)
#define	HPET_NUM_TIM_CAP_MASK		(0x1f00)
#define	HPET_NUM_TIM_CAP_SHIFT		(8ULL)

/*
 * HPET general configuration register
 */

#define	HPET_LEG_RT_CNF_MASK		(2UL)
#define	HPET_ENABLE_CNF_MASK		(1UL)


/*
 * Timer configuration register
 */

#define	Tn_INT_ROUTE_CAP_MASK		(0xffffffff00000000ULL)
#define	Tn_INT_ROUTE_CAP_SHIFT		(32UL)
#define	Tn_FSB_INT_DELCAP_MASK		(0x8000UL)
#define	Tn_FSB_INT_DELCAP_SHIFT		(15)
#define	Tn_FSB_EN_CNF_MASK		(0x4000UL)
#define	Tn_FSB_EN_CNF_SHIFT		(14)
#define	Tn_INT_ROUTE_CNF_MASK		(0x3e00UL)
#define	Tn_INT_ROUTE_CNF_SHIFT		(9)
#define	Tn_32MODE_CNF_MASK		(0x0100UL)
#define	Tn_VAL_SET_CNF_MASK		(0x0040UL)
#define	Tn_SIZE_CAP_MASK		(0x0020UL)
#define	Tn_PER_INT_CAP_MASK		(0x0010UL)
#define	Tn_TYPE_CNF_MASK		(0x0008UL)
#define	Tn_INT_ENB_CNF_MASK		(0x0004UL)
#define	Tn_INT_TYPE_CNF_MASK		(0x0002UL)

/*
 * Timer FSB Interrupt Route Register
 */

#define	Tn_FSB_INT_ADDR_MASK		(0xffffffff00000000ULL)
#define	Tn_FSB_INT_ADDR_SHIFT		(32UL)
#define	Tn_FSB_INT_VAL_MASK		(0x00000000ffffffffULL)

/*
 * exported interfaces
 */

struct hpet_data {
	unsigned long hd_phys_address;
	void __iomem *hd_address;
	unsigned short hd_nirqs;
	unsigned int hd_state;	/* timer allocated */
	unsigned int hd_irq[HPET_MAX_TIMERS];
};

static inline void hpet_reserve_timer(struct hpet_data *hd, int timer)
{
	hd->hd_state |= (1 << timer);
	return;
}

int hpet_alloc(struct hpet_data *);

#endif				/* !__HPET__ */
Commit	Line	Data
1da177e4 LT	1	#ifndef __HPET__
	2	#define __HPET__ 1
	3
607ca46e	4	#include <uapi/linux/hpet.h>
1da177e4	5
878a9f30	6
1da177e4 LT	7	/*
	8	* Offsets into HPET Registers
	9	*/
	10
	11	struct hpet {
	12	u64 hpet_cap; /* capabilities */
	13	u64 res0; /* reserved */
	14	u64 hpet_config; /* configuration */
	15	u64 res1; /* reserved */
	16	u64 hpet_isr; /* interrupt status reg */
	17	u64 res2[25]; /* reserved */
	18	union { /* main counter */
	19	u64 _hpet_mc64;
	20	u32 _hpet_mc32;
	21	unsigned long _hpet_mc;
	22	} _u0;
	23	u64 res3; /* reserved */
	24	struct hpet_timer {
	25	u64 hpet_config; /* configuration/cap */
	26	union { /* timer compare register */
	27	u64 _hpet_hc64;
	28	u32 _hpet_hc32;
	29	unsigned long _hpet_compare;
	30	} _u1;
	31	u64 hpet_fsb[2]; /* FSB route */
	32	} hpet_timers[1];
	33	};
	34
	35	#define hpet_mc _u0._hpet_mc
	36	#define hpet_compare _u1._hpet_compare
	37
	38	#define HPET_MAX_TIMERS (32)
70ef6d59	39	#define HPET_MAX_IRQ (32)
1da177e4 LT	40
	41	/*
	42	* HPET general capabilities register
	43	*/
	44
	45	#define HPET_COUNTER_CLK_PERIOD_MASK (0xffffffff00000000ULL)
	46	#define HPET_COUNTER_CLK_PERIOD_SHIFT (32UL)
	47	#define HPET_VENDOR_ID_MASK (0x00000000ffff0000ULL)
	48	#define HPET_VENDOR_ID_SHIFT (16ULL)
	49	#define HPET_LEG_RT_CAP_MASK (0x8000)
	50	#define HPET_COUNTER_SIZE_MASK (0x2000)
	51	#define HPET_NUM_TIM_CAP_MASK (0x1f00)
	52	#define HPET_NUM_TIM_CAP_SHIFT (8ULL)
	53
	54	/*
	55	* HPET general configuration register
	56	*/
	57
	58	#define HPET_LEG_RT_CNF_MASK (2UL)
	59	#define HPET_ENABLE_CNF_MASK (1UL)
	60
	61
	62	/*
	63	* Timer configuration register
	64	*/
	65
	66	#define Tn_INT_ROUTE_CAP_MASK (0xffffffff00000000ULL)
70ef6d59	67	#define Tn_INT_ROUTE_CAP_SHIFT (32UL)
1da177e4 LT	68	#define Tn_FSB_INT_DELCAP_MASK (0x8000UL)
	69	#define Tn_FSB_INT_DELCAP_SHIFT (15)
	70	#define Tn_FSB_EN_CNF_MASK (0x4000UL)
	71	#define Tn_FSB_EN_CNF_SHIFT (14)
	72	#define Tn_INT_ROUTE_CNF_MASK (0x3e00UL)
	73	#define Tn_INT_ROUTE_CNF_SHIFT (9)
	74	#define Tn_32MODE_CNF_MASK (0x0100UL)
	75	#define Tn_VAL_SET_CNF_MASK (0x0040UL)
	76	#define Tn_SIZE_CAP_MASK (0x0020UL)
	77	#define Tn_PER_INT_CAP_MASK (0x0010UL)
	78	#define Tn_TYPE_CNF_MASK (0x0008UL)
	79	#define Tn_INT_ENB_CNF_MASK (0x0004UL)
	80	#define Tn_INT_TYPE_CNF_MASK (0x0002UL)
	81
	82	/*
	83	* Timer FSB Interrupt Route Register
	84	*/
	85
	86	#define Tn_FSB_INT_ADDR_MASK (0xffffffff00000000ULL)
	87	#define Tn_FSB_INT_ADDR_SHIFT (32UL)
	88	#define Tn_FSB_INT_VAL_MASK (0x00000000ffffffffULL)
	89
1da177e4 LT	90	/*
	91	* exported interfaces
	92	*/
	93
1da177e4 LT	94	struct hpet_data {
	95	unsigned long hd_phys_address;
	96	void __iomem *hd_address;
	97	unsigned short hd_nirqs;
1da177e4 LT	98	unsigned int hd_state; /* timer allocated */
	99	unsigned int hd_irq[HPET_MAX_TIMERS];
	100	};
	101
1da177e4 LT	102	static inline void hpet_reserve_timer(struct hpet_data *hd, int timer)
	103	{
	104	hd->hd_state \|= (1 << timer);
	105	return;
	106	}
	107
	108	int hpet_alloc(struct hpet_data *);
1da177e4 LT	109
1da177e4 LT	110	#endif /* !__HPET__ */