[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / dma-mapping.h

#ifndef _LINUX_DMA_MAPPING_H
#define _LINUX_DMA_MAPPING_H

#include <linux/string.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/dma-attrs.h>
#include <linux/dma-direction.h>
#include <linux/scatterlist.h>

struct dma_map_ops {
	void* (*alloc)(struct device *dev, size_t size,
				dma_addr_t *dma_handle, gfp_t gfp,
				struct dma_attrs *attrs);
	void (*free)(struct device *dev, size_t size,
			      void *vaddr, dma_addr_t dma_handle,
			      struct dma_attrs *attrs);
	int (*mmap)(struct device *, struct vm_area_struct *,
			  void *, dma_addr_t, size_t, struct dma_attrs *attrs);

	int (*get_sgtable)(struct device *dev, struct sg_table *sgt, void *,
			   dma_addr_t, size_t, struct dma_attrs *attrs);

	dma_addr_t (*map_page)(struct device *dev, struct page *page,
			       unsigned long offset, size_t size,
			       enum dma_data_direction dir,
			       struct dma_attrs *attrs);
	void (*unmap_page)(struct device *dev, dma_addr_t dma_handle,
			   size_t size, enum dma_data_direction dir,
			   struct dma_attrs *attrs);
	int (*map_sg)(struct device *dev, struct scatterlist *sg,
		      int nents, enum dma_data_direction dir,
		      struct dma_attrs *attrs);
	void (*unmap_sg)(struct device *dev,
			 struct scatterlist *sg, int nents,
			 enum dma_data_direction dir,
			 struct dma_attrs *attrs);
	void (*sync_single_for_cpu)(struct device *dev,
				    dma_addr_t dma_handle, size_t size,
				    enum dma_data_direction dir);
	void (*sync_single_for_device)(struct device *dev,
				       dma_addr_t dma_handle, size_t size,
				       enum dma_data_direction dir);
	void (*sync_sg_for_cpu)(struct device *dev,
				struct scatterlist *sg, int nents,
				enum dma_data_direction dir);
	void (*sync_sg_for_device)(struct device *dev,
				   struct scatterlist *sg, int nents,
				   enum dma_data_direction dir);
	int (*mapping_error)(struct device *dev, dma_addr_t dma_addr);
	int (*dma_supported)(struct device *dev, u64 mask);
	int (*set_dma_mask)(struct device *dev, u64 mask);
#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
	u64 (*get_required_mask)(struct device *dev);
#endif
	int is_phys;
};

#define DMA_BIT_MASK(n)	(((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))

#define DMA_MASK_NONE	0x0ULL

static inline int valid_dma_direction(int dma_direction)
{
	return ((dma_direction == DMA_BIDIRECTIONAL) ||
		(dma_direction == DMA_TO_DEVICE) ||
		(dma_direction == DMA_FROM_DEVICE));
}

static inline int is_device_dma_capable(struct device *dev)
{
	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
}

#ifdef CONFIG_HAS_DMA
#include <asm/dma-mapping.h>
#else
#include <asm-generic/dma-mapping-broken.h>
#endif

static inline u64 dma_get_mask(struct device *dev)
{
	if (dev && dev->dma_mask && *dev->dma_mask)
		return *dev->dma_mask;
	return DMA_BIT_MASK(32);
}

#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
int dma_set_coherent_mask(struct device *dev, u64 mask);
#else
static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
{
	if (!dma_supported(dev, mask))
		return -EIO;
	dev->coherent_dma_mask = mask;
	return 0;
}
#endif

extern u64 dma_get_required_mask(struct device *dev);

static inline unsigned int dma_get_max_seg_size(struct device *dev)
{
	return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
}

static inline unsigned int dma_set_max_seg_size(struct device *dev,
						unsigned int size)
{
	if (dev->dma_parms) {
		dev->dma_parms->max_segment_size = size;
		return 0;
	} else
		return -EIO;
}

static inline unsigned long dma_get_seg_boundary(struct device *dev)
{
	return dev->dma_parms ?
		dev->dma_parms->segment_boundary_mask : 0xffffffff;
}

static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
{
	if (dev->dma_parms) {
		dev->dma_parms->segment_boundary_mask = mask;
		return 0;
	} else
		return -EIO;
}

static inline void *dma_zalloc_coherent(struct device *dev, size_t size,
					dma_addr_t *dma_handle, gfp_t flag)
{
	void *ret = dma_alloc_coherent(dev, size, dma_handle, flag);
	if (ret)
		memset(ret, 0, size);
	return ret;
}

#ifdef CONFIG_HAS_DMA
static inline int dma_get_cache_alignment(void)
{
#ifdef ARCH_DMA_MINALIGN
	return ARCH_DMA_MINALIGN;
#endif
	return 1;
}
#endif

/* flags for the coherent memory api */
#define	DMA_MEMORY_MAP			0x01
#define DMA_MEMORY_IO			0x02
#define DMA_MEMORY_INCLUDES_CHILDREN	0x04
#define DMA_MEMORY_EXCLUSIVE		0x08

#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
static inline int
dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
			    dma_addr_t device_addr, size_t size, int flags)
{
	return 0;
}

static inline void
dma_release_declared_memory(struct device *dev)
{
}

static inline void *
dma_mark_declared_memory_occupied(struct device *dev,
				  dma_addr_t device_addr, size_t size)
{
	return ERR_PTR(-EBUSY);
}
#endif

/*
 * Managed DMA API
 */
extern void *dmam_alloc_coherent(struct device *dev, size_t size,
				 dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
			       dma_addr_t dma_handle);
extern void *dmam_alloc_noncoherent(struct device *dev, size_t size,
				    dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr,
				  dma_addr_t dma_handle);
#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
					dma_addr_t device_addr, size_t size,
					int flags);
extern void dmam_release_declared_memory(struct device *dev);
#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
static inline int dmam_declare_coherent_memory(struct device *dev,
				dma_addr_t bus_addr, dma_addr_t device_addr,
				size_t size, gfp_t gfp)
{
	return 0;
}

static inline void dmam_release_declared_memory(struct device *dev)
{
}
#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */

#ifndef CONFIG_HAVE_DMA_ATTRS
struct dma_attrs;

#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
	dma_map_single(dev, cpu_addr, size, dir)

#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
	dma_unmap_single(dev, dma_addr, size, dir)

#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
	dma_map_sg(dev, sgl, nents, dir)

#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
	dma_unmap_sg(dev, sgl, nents, dir)

#endif /* CONFIG_HAVE_DMA_ATTRS */

#ifdef CONFIG_NEED_DMA_MAP_STATE
#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)        dma_addr_t ADDR_NAME
#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)          __u32 LEN_NAME
#define dma_unmap_addr(PTR, ADDR_NAME)           ((PTR)->ADDR_NAME)
#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL)  (((PTR)->ADDR_NAME) = (VAL))
#define dma_unmap_len(PTR, LEN_NAME)             ((PTR)->LEN_NAME)
#define dma_unmap_len_set(PTR, LEN_NAME, VAL)    (((PTR)->LEN_NAME) = (VAL))
#else
#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
#define dma_unmap_addr(PTR, ADDR_NAME)           (0)
#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL)  do { } while (0)
#define dma_unmap_len(PTR, LEN_NAME)             (0)
#define dma_unmap_len_set(PTR, LEN_NAME, VAL)    do { } while (0)
#endif

#endif
Commit	Line	Data
96532bab RD	1	#ifndef _LINUX_DMA_MAPPING_H
96532bab RD	2	#define _LINUX_DMA_MAPPING_H
1da177e4	3
842fa69f	4	#include <linux/string.h>
1da177e4 LT	5	#include <linux/device.h>
1da177e4 LT	6	#include <linux/err.h>
f0402a26	7	#include <linux/dma-attrs.h>
b7f080cf	8	#include <linux/dma-direction.h>
f0402a26	9	#include <linux/scatterlist.h>
1da177e4	10
f0402a26	11	struct dma_map_ops {
613c4578 MS	12	void* (alloc)(struct device dev, size_t size,
	13	dma_addr_t *dma_handle, gfp_t gfp,
	14	struct dma_attrs *attrs);
	15	void (free)(struct device dev, size_t size,
	16	void *vaddr, dma_addr_t dma_handle,
	17	struct dma_attrs *attrs);
9adc5374 MS	18	int (mmap)(struct device , struct vm_area_struct *,
	19	void , dma_addr_t, size_t, struct dma_attrs attrs);
	20
d2b7428e MS	21	int (get_sgtable)(struct device dev, struct sg_table sgt, void ,
	22	dma_addr_t, size_t, struct dma_attrs *attrs);
	23
f0402a26 FT	24	dma_addr_t (map_page)(struct device dev, struct page *page,
	25	unsigned long offset, size_t size,
	26	enum dma_data_direction dir,
	27	struct dma_attrs *attrs);
	28	void (unmap_page)(struct device dev, dma_addr_t dma_handle,
	29	size_t size, enum dma_data_direction dir,
	30	struct dma_attrs *attrs);
	31	int (map_sg)(struct device dev, struct scatterlist *sg,
	32	int nents, enum dma_data_direction dir,
	33	struct dma_attrs *attrs);
	34	void (unmap_sg)(struct device dev,
	35	struct scatterlist *sg, int nents,
	36	enum dma_data_direction dir,
	37	struct dma_attrs *attrs);
	38	void (sync_single_for_cpu)(struct device dev,
	39	dma_addr_t dma_handle, size_t size,
	40	enum dma_data_direction dir);
	41	void (sync_single_for_device)(struct device dev,
	42	dma_addr_t dma_handle, size_t size,
	43	enum dma_data_direction dir);
f0402a26 FT	44	void (sync_sg_for_cpu)(struct device dev,
	45	struct scatterlist *sg, int nents,
	46	enum dma_data_direction dir);
	47	void (sync_sg_for_device)(struct device dev,
	48	struct scatterlist *sg, int nents,
	49	enum dma_data_direction dir);
	50	int (mapping_error)(struct device dev, dma_addr_t dma_addr);
	51	int (dma_supported)(struct device dev, u64 mask);
f726f30e	52	int (set_dma_mask)(struct device dev, u64 mask);
3a8f7558 MM	53	#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
	54	u64 (get_required_mask)(struct device dev);
	55	#endif
f0402a26 FT	56	int is_phys;
	57	};
	58
8f286c33	59	#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
34c65384	60
32e8f702 JB	61	#define DMA_MASK_NONE 0x0ULL
32e8f702 JB	62
d6bd3a39 REB	63	static inline int valid_dma_direction(int dma_direction)
	64	{
	65	return ((dma_direction == DMA_BIDIRECTIONAL) \|\|
	66	(dma_direction == DMA_TO_DEVICE) \|\|
	67	(dma_direction == DMA_FROM_DEVICE));
	68	}
	69
32e8f702 JB	70	static inline int is_device_dma_capable(struct device *dev)
	71	{
	72	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
	73	}
	74
1b0fac45	75	#ifdef CONFIG_HAS_DMA
1da177e4	76	#include <asm/dma-mapping.h>
1b0fac45 DW	77	#else
	78	#include <asm-generic/dma-mapping-broken.h>
	79	#endif
1da177e4	80
589fc9a6 FT	81	static inline u64 dma_get_mask(struct device *dev)
589fc9a6 FT	82	{
07a2c01a	83	if (dev && dev->dma_mask && *dev->dma_mask)
589fc9a6	84	return *dev->dma_mask;
284901a9	85	return DMA_BIT_MASK(32);
589fc9a6 FT	86	}
589fc9a6 FT	87
58af4a24	88	#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
710224fa FT	89	int dma_set_coherent_mask(struct device *dev, u64 mask);
710224fa FT	90	#else
6a1961f4 FT	91	static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
	92	{
	93	if (!dma_supported(dev, mask))
	94	return -EIO;
	95	dev->coherent_dma_mask = mask;
	96	return 0;
	97	}
710224fa	98	#endif
6a1961f4	99
1da177e4 LT	100	extern u64 dma_get_required_mask(struct device *dev);
1da177e4 LT	101
6b7b6510 FT	102	static inline unsigned int dma_get_max_seg_size(struct device *dev)
	103	{
	104	return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
	105	}
	106
	107	static inline unsigned int dma_set_max_seg_size(struct device *dev,
	108	unsigned int size)
	109	{
	110	if (dev->dma_parms) {
	111	dev->dma_parms->max_segment_size = size;
	112	return 0;
	113	} else
	114	return -EIO;
	115	}
	116
d22a6966 FT	117	static inline unsigned long dma_get_seg_boundary(struct device *dev)
	118	{
	119	return dev->dma_parms ?
	120	dev->dma_parms->segment_boundary_mask : 0xffffffff;
	121	}
	122
	123	static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
	124	{
	125	if (dev->dma_parms) {
	126	dev->dma_parms->segment_boundary_mask = mask;
	127	return 0;
	128	} else
	129	return -EIO;
	130	}
	131
842fa69f AM	132	static inline void dma_zalloc_coherent(struct device dev, size_t size,
	133	dma_addr_t *dma_handle, gfp_t flag)
	134	{
	135	void *ret = dma_alloc_coherent(dev, size, dma_handle, flag);
	136	if (ret)
	137	memset(ret, 0, size);
	138	return ret;
	139	}
	140
e259f191	141	#ifdef CONFIG_HAS_DMA
4565f017 FT	142	static inline int dma_get_cache_alignment(void)
	143	{
	144	#ifdef ARCH_DMA_MINALIGN
	145	return ARCH_DMA_MINALIGN;
	146	#endif
	147	return 1;
	148	}
e259f191	149	#endif
4565f017	150
1da177e4 LT	151	/* flags for the coherent memory api */
	152	#define DMA_MEMORY_MAP 0x01
	153	#define DMA_MEMORY_IO 0x02
	154	#define DMA_MEMORY_INCLUDES_CHILDREN 0x04
	155	#define DMA_MEMORY_EXCLUSIVE 0x08
	156
	157	#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
	158	static inline int
	159	dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
	160	dma_addr_t device_addr, size_t size, int flags)
	161	{
	162	return 0;
	163	}
	164
	165	static inline void
	166	dma_release_declared_memory(struct device *dev)
	167	{
	168	}
	169
	170	static inline void *
	171	dma_mark_declared_memory_occupied(struct device *dev,
	172	dma_addr_t device_addr, size_t size)
	173	{
	174	return ERR_PTR(-EBUSY);
	175	}
	176	#endif
	177
9ac7849e TH	178	/*
	179	* Managed DMA API
	180	*/
	181	extern void dmam_alloc_coherent(struct device dev, size_t size,
	182	dma_addr_t *dma_handle, gfp_t gfp);
	183	extern void dmam_free_coherent(struct device dev, size_t size, void vaddr,
	184	dma_addr_t dma_handle);
	185	extern void dmam_alloc_noncoherent(struct device dev, size_t size,
	186	dma_addr_t *dma_handle, gfp_t gfp);
	187	extern void dmam_free_noncoherent(struct device dev, size_t size, void vaddr,
	188	dma_addr_t dma_handle);
	189	#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
	190	extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
	191	dma_addr_t device_addr, size_t size,
	192	int flags);
	193	extern void dmam_release_declared_memory(struct device *dev);
	194	#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
	195	static inline int dmam_declare_coherent_memory(struct device *dev,
	196	dma_addr_t bus_addr, dma_addr_t device_addr,
	197	size_t size, gfp_t gfp)
	198	{
	199	return 0;
	200	}
1da177e4	201
9ac7849e TH	202	static inline void dmam_release_declared_memory(struct device *dev)
	203	{
	204	}
	205	#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
1da177e4	206
74bc7cee AK	207	#ifndef CONFIG_HAVE_DMA_ATTRS
	208	struct dma_attrs;
	209
	210	#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
	211	dma_map_single(dev, cpu_addr, size, dir)
	212
	213	#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
	214	dma_unmap_single(dev, dma_addr, size, dir)
	215
	216	#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
	217	dma_map_sg(dev, sgl, nents, dir)
	218
	219	#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
	220	dma_unmap_sg(dev, sgl, nents, dir)
	221
	222	#endif /* CONFIG_HAVE_DMA_ATTRS */
	223
0acedc12 FT	224	#ifdef CONFIG_NEED_DMA_MAP_STATE
	225	#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME
	226	#define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME
	227	#define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
	228	#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
	229	#define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
	230	#define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
	231	#else
	232	#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
	233	#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
	234	#define dma_unmap_addr(PTR, ADDR_NAME) (0)
	235	#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
	236	#define dma_unmap_len(PTR, LEN_NAME) (0)
	237	#define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
	238	#endif
	239
9ac7849e	240	#endif