[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / clk-private.h

/*
 *  linux/include/linux/clk-private.h
 *
 *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
 *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __LINUX_CLK_PRIVATE_H
#define __LINUX_CLK_PRIVATE_H

#include <linux/clk-provider.h>
#include <linux/list.h>

/*
 * WARNING: Do not include clk-private.h from any file that implements struct
 * clk_ops.  Doing so is a layering violation!
 *
 * This header exists only to allow for statically initialized clock data.  Any
 * static clock data must be defined in a separate file from the logic that
 * implements the clock operations for that same data.
 */

#ifdef CONFIG_COMMON_CLK

struct clk {
	const char		*name;
	const struct clk_ops	*ops;
	struct clk_hw		*hw;
	struct clk		*parent;
	const char		**parent_names;
	struct clk		**parents;
	u8			num_parents;
	unsigned long		rate;
	unsigned long		new_rate;
	unsigned long		flags;
	unsigned int		enable_count;
	unsigned int		prepare_count;
	struct hlist_head	children;
	struct hlist_node	child_node;
	unsigned int		notifier_count;
#ifdef CONFIG_COMMON_CLK_DEBUG
	struct dentry		*dentry;
#endif
};

/*
 * DOC: Basic clock implementations common to many platforms
 *
 * Each basic clock hardware type is comprised of a structure describing the
 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
 * unique flags for that hardware type, a registration function and an
 * alternative macro for static initialization
 */

#define DEFINE_CLK(_name, _ops, _flags, _parent_names,		\
		_parents)					\
	static struct clk _name = {				\
		.name = #_name,					\
		.ops = &_ops,					\
		.hw = &_name##_hw.hw,				\
		.parent_names = _parent_names,			\
		.num_parents = ARRAY_SIZE(_parent_names),	\
		.parents = _parents,				\
		.flags = _flags | CLK_IS_BASIC,			\
	}

#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,		\
				_fixed_rate_flags)		\
	static struct clk _name;				\
	static const char *_name##_parent_names[] = {};		\
	static struct clk_fixed_rate _name##_hw = {		\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.fixed_rate = _rate,				\
		.flags = _fixed_rate_flags,			\
	};							\
	DEFINE_CLK(_name, clk_fixed_rate_ops, _flags,		\
			_name##_parent_names, NULL);

#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
				_flags, _reg, _bit_idx,		\
				_gate_flags, _lock)		\
	static struct clk _name;				\
	static const char *_name##_parent_names[] = {		\
		_parent_name,					\
	};							\
	static struct clk *_name##_parents[] = {		\
		_parent_ptr,					\
	};							\
	static struct clk_gate _name##_hw = {			\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.reg = _reg,					\
		.bit_idx = _bit_idx,				\
		.flags = _gate_flags,				\
		.lock = _lock,					\
	};							\
	DEFINE_CLK(_name, clk_gate_ops, _flags,			\
			_name##_parent_names, _name##_parents);

#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
				_flags, _reg, _shift, _width,	\
				_divider_flags, _table, _lock)	\
	static struct clk _name;				\
	static const char *_name##_parent_names[] = {		\
		_parent_name,					\
	};							\
	static struct clk *_name##_parents[] = {		\
		_parent_ptr,					\
	};							\
	static struct clk_divider _name##_hw = {		\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.reg = _reg,					\
		.shift = _shift,				\
		.width = _width,				\
		.flags = _divider_flags,			\
		.table = _table,				\
		.lock = _lock,					\
	};							\
	DEFINE_CLK(_name, clk_divider_ops, _flags,		\
			_name##_parent_names, _name##_parents);

#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
				_flags, _reg, _shift, _width,	\
				_divider_flags, _lock)		\
	_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
				_flags, _reg, _shift, _width,	\
				_divider_flags, NULL, _lock)

#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name,		\
				_parent_ptr, _flags, _reg,	\
				_shift, _width, _divider_flags,	\
				_table, _lock)			\
	_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
				_flags, _reg, _shift, _width,	\
				_divider_flags, _table, _lock)	\

#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,	\
				_reg, _shift, _width,		\
				_mux_flags, _lock)		\
	static struct clk _name;				\
	static struct clk_mux _name##_hw = {			\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.reg = _reg,					\
		.shift = _shift,				\
		.mask = BIT(_width) - 1,			\
		.flags = _mux_flags,				\
		.lock = _lock,					\
	};							\
	DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names,	\
			_parents);

#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name,		\
				_parent_ptr, _flags,		\
				_mult, _div)			\
	static struct clk _name;				\
	static const char *_name##_parent_names[] = {		\
		_parent_name,					\
	};							\
	static struct clk *_name##_parents[] = {		\
		_parent_ptr,					\
	};							\
	static struct clk_fixed_factor _name##_hw = {		\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.mult = _mult,					\
		.div = _div,					\
	};							\
	DEFINE_CLK(_name, clk_fixed_factor_ops, _flags,		\
			_name##_parent_names, _name##_parents);

/**
 * __clk_init - initialize the data structures in a struct clk
 * @dev:	device initializing this clk, placeholder for now
 * @clk:	clk being initialized
 *
 * Initializes the lists in struct clk, queries the hardware for the
 * parent and rate and sets them both.
 *
 * Any struct clk passed into __clk_init must have the following members
 * populated:
 * 	.name
 * 	.ops
 * 	.hw
 * 	.parent_names
 * 	.num_parents
 * 	.flags
 *
 * It is not necessary to call clk_register if __clk_init is used directly with
 * statically initialized clock data.
 *
 * Returns 0 on success, otherwise an error code.
 */
int __clk_init(struct device *dev, struct clk *clk);

struct clk *__clk_register(struct device *dev, struct clk_hw *hw);

#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PRIVATE_H */
Commit	Line	Data
b2476490 MT	1	/*
	2	* linux/include/linux/clk-private.h
	3	*
	4	* Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
	5	* Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#ifndef __LINUX_CLK_PRIVATE_H
	12	#define __LINUX_CLK_PRIVATE_H
	13
	14	#include <linux/clk-provider.h>
	15	#include <linux/list.h>
	16
	17	/*
	18	* WARNING: Do not include clk-private.h from any file that implements struct
	19	* clk_ops. Doing so is a layering violation!
	20	*
	21	* This header exists only to allow for statically initialized clock data. Any
	22	* static clock data must be defined in a separate file from the logic that
	23	* implements the clock operations for that same data.
	24	*/
	25
	26	#ifdef CONFIG_COMMON_CLK
	27
	28	struct clk {
	29	const char *name;
	30	const struct clk_ops *ops;
	31	struct clk_hw *hw;
	32	struct clk *parent;
d305fb78	33	const char **parent_names;
b2476490 MT	34	struct clk **parents;
	35	u8 num_parents;
	36	unsigned long rate;
	37	unsigned long new_rate;
	38	unsigned long flags;
	39	unsigned int enable_count;
	40	unsigned int prepare_count;
	41	struct hlist_head children;
	42	struct hlist_node child_node;
	43	unsigned int notifier_count;
	44	#ifdef CONFIG_COMMON_CLK_DEBUG
	45	struct dentry *dentry;
	46	#endif
	47	};
	48
9d9f78ed MT	49	/*
	50	* DOC: Basic clock implementations common to many platforms
	51	*
	52	* Each basic clock hardware type is comprised of a structure describing the
	53	* clock hardware, implementations of the relevant callbacks in struct clk_ops,
	54	* unique flags for that hardware type, a registration function and an
	55	* alternative macro for static initialization
	56	*/
	57
182f9e8c VK	58	#define DEFINE_CLK(_name, _ops, _flags, _parent_names, \
	59	_parents) \
	60	static struct clk _name = { \
	61	.name = #_name, \
	62	.ops = &_ops, \
	63	.hw = &_name##_hw.hw, \
	64	.parent_names = _parent_names, \
	65	.num_parents = ARRAY_SIZE(_parent_names), \
	66	.parents = _parents, \
f7d8caad	67	.flags = _flags \| CLK_IS_BASIC, \
182f9e8c VK	68	}
182f9e8c VK	69
9d9f78ed MT	70	#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \
	71	_fixed_rate_flags) \
	72	static struct clk _name; \
e447c50e	73	static const char *_name##_parent_names[] = {}; \
9d9f78ed MT	74	static struct clk_fixed_rate _name##_hw = { \
	75	.hw = { \
	76	.clk = &_name, \
	77	}, \
	78	.fixed_rate = _rate, \
	79	.flags = _fixed_rate_flags, \
	80	}; \
182f9e8c VK	81	DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \
182f9e8c VK	82	_name##_parent_names, NULL);
9d9f78ed	83
9d9f78ed MT	84	#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \
	85	_flags, _reg, _bit_idx, \
	86	_gate_flags, _lock) \
	87	static struct clk _name; \
e447c50e	88	static const char *_name##_parent_names[] = { \
9d9f78ed MT	89	_parent_name, \
	90	}; \
	91	static struct clk *_name##_parents[] = { \
	92	_parent_ptr, \
	93	}; \
	94	static struct clk_gate _name##_hw = { \
	95	.hw = { \
	96	.clk = &_name, \
	97	}, \
	98	.reg = _reg, \
	99	.bit_idx = _bit_idx, \
	100	.flags = _gate_flags, \
	101	.lock = _lock, \
	102	}; \
182f9e8c VK	103	DEFINE_CLK(_name, clk_gate_ops, _flags, \
182f9e8c VK	104	_name##_parent_names, _name##_parents);
9d9f78ed	105
357c3f0a	106	#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
9d9f78ed	107	_flags, _reg, _shift, _width, \
357c3f0a	108	_divider_flags, _table, _lock) \
9d9f78ed	109	static struct clk _name; \
e447c50e	110	static const char *_name##_parent_names[] = { \
9d9f78ed MT	111	_parent_name, \
	112	}; \
	113	static struct clk *_name##_parents[] = { \
	114	_parent_ptr, \
	115	}; \
	116	static struct clk_divider _name##_hw = { \
	117	.hw = { \
	118	.clk = &_name, \
	119	}, \
	120	.reg = _reg, \
	121	.shift = _shift, \
	122	.width = _width, \
	123	.flags = _divider_flags, \
357c3f0a	124	.table = _table, \
9d9f78ed MT	125	.lock = _lock, \
9d9f78ed MT	126	}; \
182f9e8c VK	127	DEFINE_CLK(_name, clk_divider_ops, _flags, \
182f9e8c VK	128	_name##_parent_names, _name##_parents);
9d9f78ed	129
357c3f0a RN	130	#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
	131	_flags, _reg, _shift, _width, \
	132	_divider_flags, _lock) \
	133	_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
	134	_flags, _reg, _shift, _width, \
	135	_divider_flags, NULL, _lock)
	136
	137	#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \
	138	_parent_ptr, _flags, _reg, \
	139	_shift, _width, _divider_flags, \
	140	_table, _lock) \
	141	_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
	142	_flags, _reg, _shift, _width, \
	143	_divider_flags, _table, _lock) \
	144
9d9f78ed MT	145	#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
	146	_reg, _shift, _width, \
	147	_mux_flags, _lock) \
	148	static struct clk _name; \
	149	static struct clk_mux _name##_hw = { \
	150	.hw = { \
	151	.clk = &_name, \
	152	}, \
	153	.reg = _reg, \
	154	.shift = _shift, \
ce4f3313	155	.mask = BIT(_width) - 1, \
9d9f78ed MT	156	.flags = _mux_flags, \
	157	.lock = _lock, \
	158	}; \
182f9e8c VK	159	DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \
182f9e8c VK	160	_parents);
9d9f78ed	161
f0948f59 SH	162	#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \
	163	_parent_ptr, _flags, \
	164	_mult, _div) \
	165	static struct clk _name; \
	166	static const char *_name##_parent_names[] = { \
	167	_parent_name, \
	168	}; \
	169	static struct clk *_name##_parents[] = { \
	170	_parent_ptr, \
	171	}; \
	172	static struct clk_fixed_factor _name##_hw = { \
	173	.hw = { \
	174	.clk = &_name, \
	175	}, \
	176	.mult = _mult, \
	177	.div = _div, \
	178	}; \
	179	DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \
	180	_name##_parent_names, _name##_parents);
	181
b2476490 MT	182	/**
	183	* __clk_init - initialize the data structures in a struct clk
	184	* @dev: device initializing this clk, placeholder for now
	185	* @clk: clk being initialized
	186	*
	187	* Initializes the lists in struct clk, queries the hardware for the
	188	* parent and rate and sets them both.
	189	*
	190	* Any struct clk passed into __clk_init must have the following members
	191	* populated:
	192	* .name
	193	* .ops
	194	* .hw
	195	* .parent_names
	196	* .num_parents
	197	* .flags
	198	*
	199	* It is not necessary to call clk_register if __clk_init is used directly with
	200	* statically initialized clock data.
d1302a36 MT	201	*
d1302a36 MT	202	* Returns 0 on success, otherwise an error code.
b2476490	203	*/
d1302a36	204	int __clk_init(struct device dev, struct clk clk);
b2476490	205
0197b3ea SK	206	struct clk __clk_register(struct device dev, struct clk_hw *hw);
0197b3ea SK	207
b2476490 MT	208	#endif /* CONFIG_COMMON_CLK */
b2476490 MT	209	#endif /* CLK_PRIVATE_H */