[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / atmel_tc.h

/*
 * Timer/Counter Unit (TC) registers.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef ATMEL_TC_H
#define ATMEL_TC_H

#include <linux/compiler.h>
#include <linux/list.h>

/*
 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
 * three general-purpose 16-bit timers.  These timers share one register bank.
 * Depending on the SOC, each timer may have its own clock and IRQ, or those
 * may be shared by the whole TC block.
 *
 * These TC blocks may have up to nine external pins:  TCLK0..2 signals for
 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
 * or triggering.  Those pins need to be set up for use with the TC block,
 * else they will be used as GPIOs or for a different controller.
 *
 * Although we expect each TC block to have a platform_device node, those
 * nodes are not what drivers bind to.  Instead, they ask for a specific
 * TC block, by number ... which is a common approach on systems with many
 * timers.  Then they use clk_get() and platform_get_irq() to get clock and
 * IRQ resources.
 */

struct clk;

/**
 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
 * @counter_width: size in bits of a timer counter register
 */
struct atmel_tcb_config {
	size_t	counter_width;
};

/**
 * struct atmel_tc - information about a Timer/Counter Block
 * @pdev: physical device
 * @iomem: resource associated with the I/O register
 * @regs: mapping through which the I/O registers can be accessed
 * @tcb_config: configuration data from SoC
 * @irq: irq for each of the three channels
 * @clk: internal clock source for each of the three channels
 * @node: list node, for tclib internal use
 *
 * On some platforms, each TC channel has its own clocks and IRQs,
 * while on others, all TC channels share the same clock and IRQ.
 * Drivers should clk_enable() all the clocks they need even though
 * all the entries in @clk may point to the same physical clock.
 * Likewise, drivers should request irqs independently for each
 * channel, but they must use IRQF_SHARED in case some of the entries
 * in @irq are actually the same IRQ.
 */
struct atmel_tc {
	struct platform_device	*pdev;
	struct resource		*iomem;
	void __iomem		*regs;
	const struct atmel_tcb_config *tcb_config;
	int			irq[3];
	struct clk		*clk[3];
	struct list_head	node;
};

extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
extern void atmel_tc_free(struct atmel_tc *tc);

/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
extern const u8 atmel_tc_divisors[5];


/*
 * Two registers have block-wide controls.  These are: configuring the three
 * "external" clocks (or event sources) used by the timer channels; and
 * synchronizing the timers by resetting them all at once.
 *
 * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
 * signals.  Or, it can mean "external to timer", using the TIOA output from
 * one of the other two timers that's being run in waveform mode.
 */

#define ATMEL_TC_BCR	0xc0		/* TC Block Control Register */
#define     ATMEL_TC_SYNC	(1 << 0)	/* synchronize timers */

#define ATMEL_TC_BMR	0xc4		/* TC Block Mode Register */
#define     ATMEL_TC_TC0XC0S	(3 << 0)	/* external clock 0 source */
#define        ATMEL_TC_TC0XC0S_TCLK0	(0 << 0)
#define        ATMEL_TC_TC0XC0S_NONE	(1 << 0)
#define        ATMEL_TC_TC0XC0S_TIOA1	(2 << 0)
#define        ATMEL_TC_TC0XC0S_TIOA2	(3 << 0)
#define     ATMEL_TC_TC1XC1S	(3 << 2)	/* external clock 1 source */
#define        ATMEL_TC_TC1XC1S_TCLK1	(0 << 2)
#define        ATMEL_TC_TC1XC1S_NONE	(1 << 2)
#define        ATMEL_TC_TC1XC1S_TIOA0	(2 << 2)
#define        ATMEL_TC_TC1XC1S_TIOA2	(3 << 2)
#define     ATMEL_TC_TC2XC2S	(3 << 4)	/* external clock 2 source */
#define        ATMEL_TC_TC2XC2S_TCLK2	(0 << 4)
#define        ATMEL_TC_TC2XC2S_NONE	(1 << 4)
#define        ATMEL_TC_TC2XC2S_TIOA0	(2 << 4)
#define        ATMEL_TC_TC2XC2S_TIOA1	(3 << 4)


/*
 * Each TC block has three "channels", each with one counter and controls.
 *
 * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
 * when it's not "external") is silicon-specific.  AT91 platforms use one
 * set of definitions; AVR32 platforms use a different set.  Don't hard-wire
 * such knowledge into your code, use the global "atmel_tc_divisors" ...
 * where index N is the divisor for clock N+1, else zero to indicate it uses
 * the 32 KiHz clock.
 *
 * The timers can be chained in various ways, and operated in "waveform"
 * generation mode (including PWM) or "capture" mode (to time events).  In
 * both modes, behavior can be configured in many ways.
 *
 * Each timer has two I/O pins, TIOA and TIOB.  Waveform mode uses TIOA as a
 * PWM output, and TIOB as either another PWM or as a trigger.  Capture mode
 * uses them only as inputs.
 */
#define ATMEL_TC_CHAN(idx)	((idx)*0x40)
#define ATMEL_TC_REG(idx, reg)	(ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)

#define ATMEL_TC_CCR	0x00		/* Channel Control Register */
#define     ATMEL_TC_CLKEN	(1 << 0)	/* clock enable */
#define     ATMEL_TC_CLKDIS	(1 << 1)	/* clock disable */
#define     ATMEL_TC_SWTRG	(1 << 2)	/* software trigger */

#define ATMEL_TC_CMR	0x04		/* Channel Mode Register */

/* Both modes share some CMR bits */
#define     ATMEL_TC_TCCLKS	(7 << 0)	/* clock source */
#define        ATMEL_TC_TIMER_CLOCK1	(0 << 0)
#define        ATMEL_TC_TIMER_CLOCK2	(1 << 0)
#define        ATMEL_TC_TIMER_CLOCK3	(2 << 0)
#define        ATMEL_TC_TIMER_CLOCK4	(3 << 0)
#define        ATMEL_TC_TIMER_CLOCK5	(4 << 0)
#define        ATMEL_TC_XC0		(5 << 0)
#define        ATMEL_TC_XC1		(6 << 0)
#define        ATMEL_TC_XC2		(7 << 0)
#define     ATMEL_TC_CLKI	(1 << 3)	/* clock invert */
#define     ATMEL_TC_BURST	(3 << 4)	/* clock gating */
#define        ATMEL_TC_GATE_NONE	(0 << 4)
#define        ATMEL_TC_GATE_XC0	(1 << 4)
#define        ATMEL_TC_GATE_XC1	(2 << 4)
#define        ATMEL_TC_GATE_XC2	(3 << 4)
#define     ATMEL_TC_WAVE	(1 << 15)	/* true = Waveform mode */

/* CAPTURE mode CMR bits */
#define     ATMEL_TC_LDBSTOP	(1 << 6)	/* counter stops on RB load */
#define     ATMEL_TC_LDBDIS	(1 << 7)	/* counter disable on RB load */
#define     ATMEL_TC_ETRGEDG	(3 << 8)	/* external trigger edge */
#define        ATMEL_TC_ETRGEDG_NONE	(0 << 8)
#define        ATMEL_TC_ETRGEDG_RISING	(1 << 8)
#define        ATMEL_TC_ETRGEDG_FALLING	(2 << 8)
#define        ATMEL_TC_ETRGEDG_BOTH	(3 << 8)
#define     ATMEL_TC_ABETRG	(1 << 10)	/* external trigger is TIOA? */
#define     ATMEL_TC_CPCTRG	(1 << 14)	/* RC compare trigger enable */
#define     ATMEL_TC_LDRA	(3 << 16)	/* RA loading edge (of TIOA) */
#define        ATMEL_TC_LDRA_NONE	(0 << 16)
#define        ATMEL_TC_LDRA_RISING	(1 << 16)
#define        ATMEL_TC_LDRA_FALLING	(2 << 16)
#define        ATMEL_TC_LDRA_BOTH	(3 << 16)
#define     ATMEL_TC_LDRB	(3 << 18)	/* RB loading edge (of TIOA) */
#define        ATMEL_TC_LDRB_NONE	(0 << 18)
#define        ATMEL_TC_LDRB_RISING	(1 << 18)
#define        ATMEL_TC_LDRB_FALLING	(2 << 18)
#define        ATMEL_TC_LDRB_BOTH	(3 << 18)

/* WAVEFORM mode CMR bits */
#define     ATMEL_TC_CPCSTOP	(1 <<  6)	/* RC compare stops counter */
#define     ATMEL_TC_CPCDIS	(1 <<  7)	/* RC compare disables counter */
#define     ATMEL_TC_EEVTEDG	(3 <<  8)	/* external event edge */
#define        ATMEL_TC_EEVTEDG_NONE	(0 << 8)
#define        ATMEL_TC_EEVTEDG_RISING	(1 << 8)
#define        ATMEL_TC_EEVTEDG_FALLING	(2 << 8)
#define        ATMEL_TC_EEVTEDG_BOTH	(3 << 8)
#define     ATMEL_TC_EEVT	(3 << 10)	/* external event source */
#define        ATMEL_TC_EEVT_TIOB	(0 << 10)
#define        ATMEL_TC_EEVT_XC0	(1 << 10)
#define        ATMEL_TC_EEVT_XC1	(2 << 10)
#define        ATMEL_TC_EEVT_XC2	(3 << 10)
#define     ATMEL_TC_ENETRG	(1 << 12)	/* external event is trigger */
#define     ATMEL_TC_WAVESEL	(3 << 13)	/* waveform type */
#define        ATMEL_TC_WAVESEL_UP	(0 << 13)
#define        ATMEL_TC_WAVESEL_UPDOWN	(1 << 13)
#define        ATMEL_TC_WAVESEL_UP_AUTO	(2 << 13)
#define        ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
#define     ATMEL_TC_ACPA	(3 << 16)	/* RA compare changes TIOA */
#define        ATMEL_TC_ACPA_NONE	(0 << 16)
#define        ATMEL_TC_ACPA_SET	(1 << 16)
#define        ATMEL_TC_ACPA_CLEAR	(2 << 16)
#define        ATMEL_TC_ACPA_TOGGLE	(3 << 16)
#define     ATMEL_TC_ACPC	(3 << 18)	/* RC compare changes TIOA */
#define        ATMEL_TC_ACPC_NONE	(0 << 18)
#define        ATMEL_TC_ACPC_SET	(1 << 18)
#define        ATMEL_TC_ACPC_CLEAR	(2 << 18)
#define        ATMEL_TC_ACPC_TOGGLE	(3 << 18)
#define     ATMEL_TC_AEEVT	(3 << 20)	/* external event changes TIOA */
#define        ATMEL_TC_AEEVT_NONE	(0 << 20)
#define        ATMEL_TC_AEEVT_SET	(1 << 20)
#define        ATMEL_TC_AEEVT_CLEAR	(2 << 20)
#define        ATMEL_TC_AEEVT_TOGGLE	(3 << 20)
#define     ATMEL_TC_ASWTRG	(3 << 22)	/* software trigger changes TIOA */
#define        ATMEL_TC_ASWTRG_NONE	(0 << 22)
#define        ATMEL_TC_ASWTRG_SET	(1 << 22)
#define        ATMEL_TC_ASWTRG_CLEAR	(2 << 22)
#define        ATMEL_TC_ASWTRG_TOGGLE	(3 << 22)
#define     ATMEL_TC_BCPB	(3 << 24)	/* RB compare changes TIOB */
#define        ATMEL_TC_BCPB_NONE	(0 << 24)
#define        ATMEL_TC_BCPB_SET	(1 << 24)
#define        ATMEL_TC_BCPB_CLEAR	(2 << 24)
#define        ATMEL_TC_BCPB_TOGGLE	(3 << 24)
#define     ATMEL_TC_BCPC	(3 << 26)	/* RC compare changes TIOB */
#define        ATMEL_TC_BCPC_NONE	(0 << 26)
#define        ATMEL_TC_BCPC_SET	(1 << 26)
#define        ATMEL_TC_BCPC_CLEAR	(2 << 26)
#define        ATMEL_TC_BCPC_TOGGLE	(3 << 26)
#define     ATMEL_TC_BEEVT	(3 << 28)	/* external event changes TIOB */
#define        ATMEL_TC_BEEVT_NONE	(0 << 28)
#define        ATMEL_TC_BEEVT_SET	(1 << 28)
#define        ATMEL_TC_BEEVT_CLEAR	(2 << 28)
#define        ATMEL_TC_BEEVT_TOGGLE	(3 << 28)
#define     ATMEL_TC_BSWTRG	(3 << 30)	/* software trigger changes TIOB */
#define        ATMEL_TC_BSWTRG_NONE	(0 << 30)
#define        ATMEL_TC_BSWTRG_SET	(1 << 30)
#define        ATMEL_TC_BSWTRG_CLEAR	(2 << 30)
#define        ATMEL_TC_BSWTRG_TOGGLE	(3 << 30)

#define ATMEL_TC_CV	0x10		/* counter Value */
#define ATMEL_TC_RA	0x14		/* register A */
#define ATMEL_TC_RB	0x18		/* register B */
#define ATMEL_TC_RC	0x1c		/* register C */

#define ATMEL_TC_SR	0x20		/* status (read-only) */
/* Status-only flags */
#define     ATMEL_TC_CLKSTA	(1 << 16)	/* clock enabled */
#define     ATMEL_TC_MTIOA	(1 << 17)	/* TIOA mirror */
#define     ATMEL_TC_MTIOB	(1 << 18)	/* TIOB mirror */

#define ATMEL_TC_IER	0x24		/* interrupt enable (write-only) */
#define ATMEL_TC_IDR	0x28		/* interrupt disable (write-only) */
#define ATMEL_TC_IMR	0x2c		/* interrupt mask (read-only) */

/* Status and IRQ flags */
#define     ATMEL_TC_COVFS	(1 <<  0)	/* counter overflow */
#define     ATMEL_TC_LOVRS	(1 <<  1)	/* load overrun */
#define     ATMEL_TC_CPAS	(1 <<  2)	/* RA compare */
#define     ATMEL_TC_CPBS	(1 <<  3)	/* RB compare */
#define     ATMEL_TC_CPCS	(1 <<  4)	/* RC compare */
#define     ATMEL_TC_LDRAS	(1 <<  5)	/* RA loading */
#define     ATMEL_TC_LDRBS	(1 <<  6)	/* RB loading */
#define     ATMEL_TC_ETRGS	(1 <<  7)	/* external trigger */

#endif
Commit	Line	Data
2a341f5c DB	1	/*
	2	* Timer/Counter Unit (TC) registers.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	#ifndef ATMEL_TC_H
	11	#define ATMEL_TC_H
	12
	13	#include <linux/compiler.h>
	14	#include <linux/list.h>
	15
	16	/*
	17	* Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
	18	* three general-purpose 16-bit timers. These timers share one register bank.
	19	* Depending on the SOC, each timer may have its own clock and IRQ, or those
	20	* may be shared by the whole TC block.
	21	*
	22	* These TC blocks may have up to nine external pins: TCLK0..2 signals for
	23	* clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
	24	* or triggering. Those pins need to be set up for use with the TC block,
	25	* else they will be used as GPIOs or for a different controller.
	26	*
	27	* Although we expect each TC block to have a platform_device node, those
	28	* nodes are not what drivers bind to. Instead, they ask for a specific
	29	* TC block, by number ... which is a common approach on systems with many
	30	* timers. Then they use clk_get() and platform_get_irq() to get clock and
	31	* IRQ resources.
	32	*/
	33
	34	struct clk;
	35
8e315a7b NF	36	/**
	37	* struct atmel_tcb_config - SoC data for a Timer/Counter Block
	38	* @counter_width: size in bits of a timer counter register
	39	*/
	40	struct atmel_tcb_config {
	41	size_t counter_width;
	42	};
	43
2a341f5c DB	44	/**
	45	* struct atmel_tc - information about a Timer/Counter Block
	46	* @pdev: physical device
	47	* @iomem: resource associated with the I/O register
	48	* @regs: mapping through which the I/O registers can be accessed
8e315a7b	49	* @tcb_config: configuration data from SoC
2a341f5c DB	50	* @irq: irq for each of the three channels
	51	* @clk: internal clock source for each of the three channels
	52	* @node: list node, for tclib internal use
	53	*
	54	* On some platforms, each TC channel has its own clocks and IRQs,
	55	* while on others, all TC channels share the same clock and IRQ.
	56	* Drivers should clk_enable() all the clocks they need even though
	57	* all the entries in @clk may point to the same physical clock.
	58	* Likewise, drivers should request irqs independently for each
	59	* channel, but they must use IRQF_SHARED in case some of the entries
	60	* in @irq are actually the same IRQ.
	61	*/
	62	struct atmel_tc {
	63	struct platform_device *pdev;
	64	struct resource *iomem;
	65	void __iomem *regs;
c1411bfa	66	const struct atmel_tcb_config *tcb_config;
2a341f5c DB	67	int irq[3];
	68	struct clk *clk[3];
	69	struct list_head node;
	70	};
	71
	72	extern struct atmel_tc atmel_tc_alloc(unsigned block, const char name);
	73	extern void atmel_tc_free(struct atmel_tc *tc);
	74
	75	/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
	76	extern const u8 atmel_tc_divisors[5];
	77
	78
	79	/*
	80	* Two registers have block-wide controls. These are: configuring the three
	81	* "external" clocks (or event sources) used by the timer channels; and
	82	* synchronizing the timers by resetting them all at once.
	83	*
	84	* "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
	85	* signals. Or, it can mean "external to timer", using the TIOA output from
	86	* one of the other two timers that's being run in waveform mode.
	87	*/
	88
	89	#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
	90	#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
	91
	92	#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
	93	#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
	94	#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
	95	#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
	96	#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
	97	#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
	98	#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
	99	#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
	100	#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
	101	#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
	102	#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
	103	#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
	104	#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
	105	#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
	106	#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
	107	#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
	108
	109
	110	/*
	111	* Each TC block has three "channels", each with one counter and controls.
	112	*
	113	* Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
	114	* when it's not "external") is silicon-specific. AT91 platforms use one
	115	* set of definitions; AVR32 platforms use a different set. Don't hard-wire
	116	* such knowledge into your code, use the global "atmel_tc_divisors" ...
	117	* where index N is the divisor for clock N+1, else zero to indicate it uses
	118	* the 32 KiHz clock.
	119	*
	120	* The timers can be chained in various ways, and operated in "waveform"
	121	* generation mode (including PWM) or "capture" mode (to time events). In
	122	* both modes, behavior can be configured in many ways.
	123	*
	124	* Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
	125	* PWM output, and TIOB as either another PWM or as a trigger. Capture mode
	126	* uses them only as inputs.
	127	*/
	128	#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
	129	#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
	130
131	#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
132	#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
133	#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
134	#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
135
136	#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
137
138	/* Both modes share some CMR bits */
139	#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
140	#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
141	#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
142	#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
143	#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
144	#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
145	#define ATMEL_TC_XC0 (5 << 0)
146	#define ATMEL_TC_XC1 (6 << 0)
147	#define ATMEL_TC_XC2 (7 << 0)
148	#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
149	#define ATMEL_TC_BURST (3 << 4) /* clock gating */
150	#define ATMEL_TC_GATE_NONE (0 << 4)
151	#define ATMEL_TC_GATE_XC0 (1 << 4)
152	#define ATMEL_TC_GATE_XC1 (2 << 4)
153	#define ATMEL_TC_GATE_XC2 (3 << 4)
154	#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
155
156	/* CAPTURE mode CMR bits */
157	#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
158	#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
159	#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
160	#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
161	#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
162	#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
163	#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
164	#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
165	#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
166	#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
167	#define ATMEL_TC_LDRA_NONE (0 << 16)
168	#define ATMEL_TC_LDRA_RISING (1 << 16)
169	#define ATMEL_TC_LDRA_FALLING (2 << 16)
170	#define ATMEL_TC_LDRA_BOTH (3 << 16)
171	#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
172	#define ATMEL_TC_LDRB_NONE (0 << 18)
173	#define ATMEL_TC_LDRB_RISING (1 << 18)
174	#define ATMEL_TC_LDRB_FALLING (2 << 18)
175	#define ATMEL_TC_LDRB_BOTH (3 << 18)
176
177	/* WAVEFORM mode CMR bits */
178	#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
179	#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
180	#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
181	#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
182	#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
183	#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
184	#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
185	#define ATMEL_TC_EEVT (3 << 10) /* external event source */
186	#define ATMEL_TC_EEVT_TIOB (0 << 10)
187	#define ATMEL_TC_EEVT_XC0 (1 << 10)
188	#define ATMEL_TC_EEVT_XC1 (2 << 10)
189	#define ATMEL_TC_EEVT_XC2 (3 << 10)
190	#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
191	#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
192	#define ATMEL_TC_WAVESEL_UP (0 << 13)
193	#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
194	#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
195	#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
196	#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
197	#define ATMEL_TC_ACPA_NONE (0 << 16)
198	#define ATMEL_TC_ACPA_SET (1 << 16)
199	#define ATMEL_TC_ACPA_CLEAR (2 << 16)
200	#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
201	#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
202	#define ATMEL_TC_ACPC_NONE (0 << 18)
203	#define ATMEL_TC_ACPC_SET (1 << 18)
204	#define ATMEL_TC_ACPC_CLEAR (2 << 18)
205	#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
206	#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
207	#define ATMEL_TC_AEEVT_NONE (0 << 20)
208	#define ATMEL_TC_AEEVT_SET (1 << 20)
209	#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
210	#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
211	#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
212	#define ATMEL_TC_ASWTRG_NONE (0 << 22)
213	#define ATMEL_TC_ASWTRG_SET (1 << 22)
214	#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
215	#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
216	#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
217	#define ATMEL_TC_BCPB_NONE (0 << 24)
218	#define ATMEL_TC_BCPB_SET (1 << 24)
219	#define ATMEL_TC_BCPB_CLEAR (2 << 24)
220	#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
221	#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
222	#define ATMEL_TC_BCPC_NONE (0 << 26)
223	#define ATMEL_TC_BCPC_SET (1 << 26)
224	#define ATMEL_TC_BCPC_CLEAR (2 << 26)
225	#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
226	#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
227	#define ATMEL_TC_BEEVT_NONE (0 << 28)
228	#define ATMEL_TC_BEEVT_SET (1 << 28)
229	#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
230	#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
231	#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
232	#define ATMEL_TC_BSWTRG_NONE (0 << 30)
233	#define ATMEL_TC_BSWTRG_SET (1 << 30)
234	#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
235	#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
236
237	#define ATMEL_TC_CV 0x10 /* counter Value */
238	#define ATMEL_TC_RA 0x14 /* register A */
239	#define ATMEL_TC_RB 0x18 /* register B */
240	#define ATMEL_TC_RC 0x1c /* register C */
241
242	#define ATMEL_TC_SR 0x20 /* status (read-only) */
243	/* Status-only flags */
244	#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
245	#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
246	#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
247
248	#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
249	#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
250	#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
251
252	/* Status and IRQ flags */
253	#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
254	#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
255	#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
256	#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
257	#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
258	#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
259	#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
260	#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
261
262	#endif