[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-x86 / i387.h

/*
 * Copyright (C) 1994 Linus Torvalds
 *
 * Pentium III FXSR, SSE support
 * General FPU state handling cleanups
 *	Gareth Hughes <gareth@valinux.com>, May 2000
 * x86-64 work by Andi Kleen 2002
 */

#ifndef ASM_X86__I387_H
#define ASM_X86__I387_H

#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <linux/regset.h>
#include <asm/asm.h>
#include <asm/processor.h>
#include <asm/sigcontext.h>
#include <asm/user.h>
#include <asm/uaccess.h>

extern void fpu_init(void);
extern void mxcsr_feature_mask_init(void);
extern int init_fpu(struct task_struct *child);
extern asmlinkage void math_state_restore(void);
extern void init_thread_xstate(void);

extern user_regset_active_fn fpregs_active, xfpregs_active;
extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;

#ifdef CONFIG_IA32_EMULATION
struct _fpstate_ia32;
extern int save_i387_ia32(struct _fpstate_ia32 __user *buf);
extern int restore_i387_ia32(struct _fpstate_ia32 __user *buf);
#endif

#ifdef CONFIG_X86_64

/* Ignore delayed exceptions from user space */
static inline void tolerant_fwait(void)
{
	asm volatile("1: fwait\n"
		     "2:\n"
		     _ASM_EXTABLE(1b, 2b));
}

static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
{
	int err;

	asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
		     "2:\n"
		     ".section .fixup,\"ax\"\n"
		     "3:  movl $-1,%[err]\n"
		     "    jmp  2b\n"
		     ".previous\n"
		     _ASM_EXTABLE(1b, 3b)
		     : [err] "=r" (err)
#if 0 /* See comment in __save_init_fpu() below. */
		     : [fx] "r" (fx), "m" (*fx), "0" (0));
#else
		     : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
#endif
	if (unlikely(err))
		init_fpu(current);
	return err;
}

#define X87_FSW_ES (1 << 7)	/* Exception Summary */

/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
   is pending. Clear the x87 state here by setting it to fixed
   values. The kernel data segment can be sometimes 0 and sometimes
   new user value. Both should be ok.
   Use the PDA as safe address because it should be already in L1. */
static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
{
	if (unlikely(fx->swd & X87_FSW_ES))
		asm volatile("fnclex");
	alternative_input(ASM_NOP8 ASM_NOP2,
			  "    emms\n"		/* clear stack tags */
			  "    fildl %%gs:0",	/* load to clear state */
			  X86_FEATURE_FXSAVE_LEAK);
}

static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
{
	int err;

	asm volatile("1:  rex64/fxsave (%[fx])\n\t"
		     "2:\n"
		     ".section .fixup,\"ax\"\n"
		     "3:  movl $-1,%[err]\n"
		     "    jmp  2b\n"
		     ".previous\n"
		     _ASM_EXTABLE(1b, 3b)
		     : [err] "=r" (err), "=m" (*fx)
#if 0 /* See comment in __fxsave_clear() below. */
		     : [fx] "r" (fx), "0" (0));
#else
		     : [fx] "cdaSDb" (fx), "0" (0));
#endif
	if (unlikely(err) &&
	    __clear_user(fx, sizeof(struct i387_fxsave_struct)))
		err = -EFAULT;
	/* No need to clear here because the caller clears USED_MATH */
	return err;
}

static inline void __save_init_fpu(struct task_struct *tsk)
{
	/* Using "rex64; fxsave %0" is broken because, if the memory operand
	   uses any extended registers for addressing, a second REX prefix
	   will be generated (to the assembler, rex64 followed by semicolon
	   is a separate instruction), and hence the 64-bitness is lost. */
#if 0
	/* Using "fxsaveq %0" would be the ideal choice, but is only supported
	   starting with gas 2.16. */
	__asm__ __volatile__("fxsaveq %0"
			     : "=m" (tsk->thread.xstate->fxsave));
#elif 0
	/* Using, as a workaround, the properly prefixed form below isn't
	   accepted by any binutils version so far released, complaining that
	   the same type of prefix is used twice if an extended register is
	   needed for addressing (fix submitted to mainline 2005-11-21). */
	__asm__ __volatile__("rex64/fxsave %0"
			     : "=m" (tsk->thread.xstate->fxsave));
#else
	/* This, however, we can work around by forcing the compiler to select
	   an addressing mode that doesn't require extended registers. */
	__asm__ __volatile__("rex64/fxsave (%1)"
			     : "=m" (tsk->thread.xstate->fxsave)
			     : "cdaSDb" (&tsk->thread.xstate->fxsave));
#endif
	clear_fpu_state(&tsk->thread.xstate->fxsave);
	task_thread_info(tsk)->status &= ~TS_USEDFPU;
}

/*
 * Signal frame handlers.
 */

static inline int save_i387(struct _fpstate __user *buf)
{
	struct task_struct *tsk = current;
	int err = 0;

	BUILD_BUG_ON(sizeof(struct user_i387_struct) !=
			sizeof(tsk->thread.xstate->fxsave));

	if ((unsigned long)buf % 16)
		printk("save_i387: bad fpstate %p\n", buf);

	if (!used_math())
		return 0;
	clear_used_math(); /* trigger finit */
	if (task_thread_info(tsk)->status & TS_USEDFPU) {
		err = save_i387_checking((struct i387_fxsave_struct __user *)
					 buf);
		if (err)
			return err;
		task_thread_info(tsk)->status &= ~TS_USEDFPU;
		stts();
	} else {
		if (__copy_to_user(buf, &tsk->thread.xstate->fxsave,
				   sizeof(struct i387_fxsave_struct)))
			return -1;
	}
	return 1;
}

/*
 * This restores directly out of user space. Exceptions are handled.
 */
static inline int restore_i387(struct _fpstate __user *buf)
{
	struct task_struct *tsk = current;
	int err;

	if (!used_math()) {
		err = init_fpu(tsk);
		if (err)
			return err;
	}

	if (!(task_thread_info(current)->status & TS_USEDFPU)) {
		clts();
		task_thread_info(current)->status |= TS_USEDFPU;
	}
	return restore_fpu_checking((__force struct i387_fxsave_struct *)buf);
}

#else  /* CONFIG_X86_32 */

extern void finit(void);

static inline void tolerant_fwait(void)
{
	asm volatile("fnclex ; fwait");
}

static inline void restore_fpu(struct task_struct *tsk)
{
	/*
	 * The "nop" is needed to make the instructions the same
	 * length.
	 */
	alternative_input(
		"nop ; frstor %1",
		"fxrstor %1",
		X86_FEATURE_FXSR,
		"m" (tsk->thread.xstate->fxsave));
}

/* We need a safe address that is cheap to find and that is already
   in L1 during context switch. The best choices are unfortunately
   different for UP and SMP */
#ifdef CONFIG_SMP
#define safe_address (__per_cpu_offset[0])
#else
#define safe_address (kstat_cpu(0).cpustat.user)
#endif

/*
 * These must be called with preempt disabled
 */
static inline void __save_init_fpu(struct task_struct *tsk)
{
	/* Use more nops than strictly needed in case the compiler
	   varies code */
	alternative_input(
		"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
		"fxsave %[fx]\n"
		"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
		X86_FEATURE_FXSR,
		[fx] "m" (tsk->thread.xstate->fxsave),
		[fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
	   is pending.  Clear the x87 state here by setting it to fixed
	   values. safe_address is a random variable that should be in L1 */
	alternative_input(
		GENERIC_NOP8 GENERIC_NOP2,
		"emms\n\t"	  	/* clear stack tags */
		"fildl %[addr]", 	/* set F?P to defined value */
		X86_FEATURE_FXSAVE_LEAK,
		[addr] "m" (safe_address));
	task_thread_info(tsk)->status &= ~TS_USEDFPU;
}

/*
 * Signal frame handlers...
 */
extern int save_i387(struct _fpstate __user *buf);
extern int restore_i387(struct _fpstate __user *buf);

#endif	/* CONFIG_X86_64 */

static inline void __unlazy_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_USEDFPU) {
		__save_init_fpu(tsk);
		stts();
	} else
		tsk->fpu_counter = 0;
}

static inline void __clear_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_USEDFPU) {
		tolerant_fwait();
		task_thread_info(tsk)->status &= ~TS_USEDFPU;
		stts();
	}
}

static inline void kernel_fpu_begin(void)
{
	struct thread_info *me = current_thread_info();
	preempt_disable();
	if (me->status & TS_USEDFPU)
		__save_init_fpu(me->task);
	else
		clts();
}

static inline void kernel_fpu_end(void)
{
	stts();
	preempt_enable();
}

#ifdef CONFIG_X86_64

static inline void save_init_fpu(struct task_struct *tsk)
{
	__save_init_fpu(tsk);
	stts();
}

#define unlazy_fpu	__unlazy_fpu
#define clear_fpu	__clear_fpu

#else  /* CONFIG_X86_32 */

/*
 * These disable preemption on their own and are safe
 */
static inline void save_init_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__save_init_fpu(tsk);
	stts();
	preempt_enable();
}

static inline void unlazy_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__unlazy_fpu(tsk);
	preempt_enable();
}

static inline void clear_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__clear_fpu(tsk);
	preempt_enable();
}

#endif	/* CONFIG_X86_64 */

/*
 * i387 state interaction
 */
static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
{
	if (cpu_has_fxsr) {
		return tsk->thread.xstate->fxsave.cwd;
	} else {
		return (unsigned short)tsk->thread.xstate->fsave.cwd;
	}
}

static inline unsigned short get_fpu_swd(struct task_struct *tsk)
{
	if (cpu_has_fxsr) {
		return tsk->thread.xstate->fxsave.swd;
	} else {
		return (unsigned short)tsk->thread.xstate->fsave.swd;
	}
}

static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
{
	if (cpu_has_xmm) {
		return tsk->thread.xstate->fxsave.mxcsr;
	} else {
		return MXCSR_DEFAULT;
	}
}

#endif /* ASM_X86__I387_H */
Commit	Line	Data
1eeaed76 RM	1	/*
	2	* Copyright (C) 1994 Linus Torvalds
	3	*
	4	* Pentium III FXSR, SSE support
	5	* General FPU state handling cleanups
	6	* Gareth Hughes <gareth@valinux.com>, May 2000
	7	* x86-64 work by Andi Kleen 2002
	8	*/
	9
77ef50a5 VN	10	#ifndef ASM_X86__I387_H
77ef50a5 VN	11	#define ASM_X86__I387_H
1eeaed76 RM	12
	13	#include <linux/sched.h>
	14	#include <linux/kernel_stat.h>
	15	#include <linux/regset.h>
92c37fa3	16	#include <asm/asm.h>
1eeaed76 RM	17	#include <asm/processor.h>
	18	#include <asm/sigcontext.h>
	19	#include <asm/user.h>
	20	#include <asm/uaccess.h>
	21
	22	extern void fpu_init(void);
1eeaed76	23	extern void mxcsr_feature_mask_init(void);
aa283f49	24	extern int init_fpu(struct task_struct *child);
1eeaed76	25	extern asmlinkage void math_state_restore(void);
61c4628b	26	extern void init_thread_xstate(void);
1eeaed76 RM	27
	28	extern user_regset_active_fn fpregs_active, xfpregs_active;
	29	extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
	30	extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
	31
	32	#ifdef CONFIG_IA32_EMULATION
	33	struct _fpstate_ia32;
	34	extern int save_i387_ia32(struct _fpstate_ia32 __user *buf);
	35	extern int restore_i387_ia32(struct _fpstate_ia32 __user *buf);
	36	#endif
	37
	38	#ifdef CONFIG_X86_64
	39
	40	/* Ignore delayed exceptions from user space */
	41	static inline void tolerant_fwait(void)
	42	{
	43	asm volatile("1: fwait\n"
	44	"2:\n"
affe6637	45	_ASM_EXTABLE(1b, 2b));
1eeaed76 RM	46	}
	47
	48	static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
	49	{
	50	int err;
	51
	52	asm volatile("1: rex64/fxrstor (%[fx])\n\t"
	53	"2:\n"
	54	".section .fixup,\"ax\"\n"
	55	"3: movl $-1,%[err]\n"
	56	" jmp 2b\n"
	57	".previous\n"
affe6637	58	_ASM_EXTABLE(1b, 3b)
1eeaed76 RM	59	: [err] "=r" (err)
	60	#if 0 /* See comment in __save_init_fpu() below. */
	61	: [fx] "r" (fx), "m" (*fx), "0" (0));
	62	#else
	63	: [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
	64	#endif
	65	if (unlikely(err))
	66	init_fpu(current);
	67	return err;
	68	}
	69
	70	#define X87_FSW_ES (1 << 7) /* Exception Summary */
	71
	72	/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
	73	is pending. Clear the x87 state here by setting it to fixed
	74	values. The kernel data segment can be sometimes 0 and sometimes
	75	new user value. Both should be ok.
	76	Use the PDA as safe address because it should be already in L1. */
	77	static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
	78	{
	79	if (unlikely(fx->swd & X87_FSW_ES))
affe6637	80	asm volatile("fnclex");
1eeaed76	81	alternative_input(ASM_NOP8 ASM_NOP2,
affe6637 JP	82	" emms\n" /* clear stack tags */
	83	" fildl %%gs:0", /* load to clear state */
	84	X86_FEATURE_FXSAVE_LEAK);
1eeaed76 RM	85	}
	86
	87	static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
	88	{
	89	int err;
	90
	91	asm volatile("1: rex64/fxsave (%[fx])\n\t"
	92	"2:\n"
	93	".section .fixup,\"ax\"\n"
	94	"3: movl $-1,%[err]\n"
	95	" jmp 2b\n"
	96	".previous\n"
affe6637	97	_ASM_EXTABLE(1b, 3b)
1eeaed76 RM	98	: [err] "=r" (err), "=m" (*fx)
	99	#if 0 /* See comment in __fxsave_clear() below. */
	100	: [fx] "r" (fx), "0" (0));
	101	#else
	102	: [fx] "cdaSDb" (fx), "0" (0));
	103	#endif
affe6637 JP	104	if (unlikely(err) &&
affe6637 JP	105	__clear_user(fx, sizeof(struct i387_fxsave_struct)))
1eeaed76 RM	106	err = -EFAULT;
	107	/* No need to clear here because the caller clears USED_MATH */
	108	return err;
	109	}
	110
	111	static inline void __save_init_fpu(struct task_struct *tsk)
	112	{
	113	/* Using "rex64; fxsave %0" is broken because, if the memory operand
	114	uses any extended registers for addressing, a second REX prefix
	115	will be generated (to the assembler, rex64 followed by semicolon
	116	is a separate instruction), and hence the 64-bitness is lost. */
	117	#if 0
	118	/* Using "fxsaveq %0" would be the ideal choice, but is only supported
	119	starting with gas 2.16. */
	120	__asm__ __volatile__("fxsaveq %0"
61c4628b	121	: "=m" (tsk->thread.xstate->fxsave));
1eeaed76 RM	122	#elif 0
	123	/* Using, as a workaround, the properly prefixed form below isn't
	124	accepted by any binutils version so far released, complaining that
	125	the same type of prefix is used twice if an extended register is
	126	needed for addressing (fix submitted to mainline 2005-11-21). */
	127	__asm__ __volatile__("rex64/fxsave %0"
61c4628b	128	: "=m" (tsk->thread.xstate->fxsave));
1eeaed76 RM	129	#else
	130	/* This, however, we can work around by forcing the compiler to select
	131	an addressing mode that doesn't require extended registers. */
61c4628b SS	132	__asm__ __volatile__("rex64/fxsave (%1)"
	133	: "=m" (tsk->thread.xstate->fxsave)
	134	: "cdaSDb" (&tsk->thread.xstate->fxsave));
1eeaed76	135	#endif
61c4628b	136	clear_fpu_state(&tsk->thread.xstate->fxsave);
1eeaed76 RM	137	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	138	}
	139
	140	/*
	141	* Signal frame handlers.
	142	*/
	143
	144	static inline int save_i387(struct _fpstate __user *buf)
	145	{
	146	struct task_struct *tsk = current;
	147	int err = 0;
	148
	149	BUILD_BUG_ON(sizeof(struct user_i387_struct) !=
61c4628b	150	sizeof(tsk->thread.xstate->fxsave));
1eeaed76 RM	151
	152	if ((unsigned long)buf % 16)
	153	printk("save_i387: bad fpstate %p\n", buf);
	154
	155	if (!used_math())
	156	return 0;
	157	clear_used_math(); /* trigger finit */
	158	if (task_thread_info(tsk)->status & TS_USEDFPU) {
affe6637 JP	159	err = save_i387_checking((struct i387_fxsave_struct __user *)
	160	buf);
	161	if (err)
	162	return err;
1eeaed76 RM	163	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	164	stts();
	165	} else {
61c4628b	166	if (__copy_to_user(buf, &tsk->thread.xstate->fxsave,
1eeaed76 RM	167	sizeof(struct i387_fxsave_struct)))
	168	return -1;
	169	}
	170	return 1;
	171	}
	172
	173	/*
	174	* This restores directly out of user space. Exceptions are handled.
	175	*/
	176	static inline int restore_i387(struct _fpstate __user *buf)
	177	{
fd3c3ed5 SS	178	struct task_struct *tsk = current;
	179	int err;
	180
	181	if (!used_math()) {
	182	err = init_fpu(tsk);
	183	if (err)
	184	return err;
	185	}
	186
1eeaed76 RM	187	if (!(task_thread_info(current)->status & TS_USEDFPU)) {
	188	clts();
	189	task_thread_info(current)->status \|= TS_USEDFPU;
	190	}
	191	return restore_fpu_checking((__force struct i387_fxsave_struct *)buf);
	192	}
	193
	194	#else /* CONFIG_X86_32 */
	195
e8a496ac SS	196	extern void finit(void);
e8a496ac SS	197
1eeaed76 RM	198	static inline void tolerant_fwait(void)
	199	{
	200	asm volatile("fnclex ; fwait");
	201	}
	202
	203	static inline void restore_fpu(struct task_struct *tsk)
	204	{
	205	/*
	206	* The "nop" is needed to make the instructions the same
	207	* length.
	208	*/
	209	alternative_input(
	210	"nop ; frstor %1",
	211	"fxrstor %1",
	212	X86_FEATURE_FXSR,
61c4628b	213	"m" (tsk->thread.xstate->fxsave));
1eeaed76 RM	214	}
	215
	216	/* We need a safe address that is cheap to find and that is already
	217	in L1 during context switch. The best choices are unfortunately
	218	different for UP and SMP */
	219	#ifdef CONFIG_SMP
	220	#define safe_address (__per_cpu_offset[0])
	221	#else
	222	#define safe_address (kstat_cpu(0).cpustat.user)
	223	#endif
	224
	225	/*
	226	* These must be called with preempt disabled
	227	*/
	228	static inline void __save_init_fpu(struct task_struct *tsk)
	229	{
	230	/* Use more nops than strictly needed in case the compiler
	231	varies code */
	232	alternative_input(
	233	"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
	234	"fxsave %[fx]\n"
	235	"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
	236	X86_FEATURE_FXSR,
61c4628b SS	237	[fx] "m" (tsk->thread.xstate->fxsave),
61c4628b SS	238	[fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
1eeaed76 RM	239	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
	240	is pending. Clear the x87 state here by setting it to fixed
	241	values. safe_address is a random variable that should be in L1 */
	242	alternative_input(
	243	GENERIC_NOP8 GENERIC_NOP2,
	244	"emms\n\t" /* clear stack tags */
	245	"fildl %[addr]", /* set F?P to defined value */
	246	X86_FEATURE_FXSAVE_LEAK,
	247	[addr] "m" (safe_address));
	248	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	249	}
	250
	251	/*
	252	* Signal frame handlers...
	253	*/
	254	extern int save_i387(struct _fpstate __user *buf);
	255	extern int restore_i387(struct _fpstate __user *buf);
	256
	257	#endif /* CONFIG_X86_64 */
	258
	259	static inline void __unlazy_fpu(struct task_struct *tsk)
	260	{
	261	if (task_thread_info(tsk)->status & TS_USEDFPU) {
	262	__save_init_fpu(tsk);
	263	stts();
	264	} else
	265	tsk->fpu_counter = 0;
	266	}
	267
	268	static inline void __clear_fpu(struct task_struct *tsk)
	269	{
	270	if (task_thread_info(tsk)->status & TS_USEDFPU) {
	271	tolerant_fwait();
	272	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	273	stts();
	274	}
	275	}
	276
	277	static inline void kernel_fpu_begin(void)
	278	{
	279	struct thread_info *me = current_thread_info();
	280	preempt_disable();
	281	if (me->status & TS_USEDFPU)
	282	__save_init_fpu(me->task);
	283	else
	284	clts();
	285	}
	286
	287	static inline void kernel_fpu_end(void)
	288	{
	289	stts();
	290	preempt_enable();
	291	}
	292
	293	#ifdef CONFIG_X86_64
	294
	295	static inline void save_init_fpu(struct task_struct *tsk)
	296	{
	297	__save_init_fpu(tsk);
	298	stts();
	299	}
	300
	301	#define unlazy_fpu __unlazy_fpu
	302	#define clear_fpu __clear_fpu
303
304	#else /* CONFIG_X86_32 */
305
306	/*
307	* These disable preemption on their own and are safe
308	*/
309	static inline void save_init_fpu(struct task_struct *tsk)
310	{
311	preempt_disable();
312	__save_init_fpu(tsk);
313	stts();
314	preempt_enable();
315	}
316
317	static inline void unlazy_fpu(struct task_struct *tsk)
318	{
319	preempt_disable();
320	__unlazy_fpu(tsk);
321	preempt_enable();
322	}
323
324	static inline void clear_fpu(struct task_struct *tsk)
325	{
326	preempt_disable();
327	__clear_fpu(tsk);
328	preempt_enable();
329	}
330
331	#endif /* CONFIG_X86_64 */
332
1eeaed76 RM	333	/*
	334	* i387 state interaction
	335	*/
	336	static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
	337	{
	338	if (cpu_has_fxsr) {
61c4628b	339	return tsk->thread.xstate->fxsave.cwd;
1eeaed76	340	} else {
1679f271	341	return (unsigned short)tsk->thread.xstate->fsave.cwd;
1eeaed76 RM	342	}
	343	}
	344
	345	static inline unsigned short get_fpu_swd(struct task_struct *tsk)
	346	{
	347	if (cpu_has_fxsr) {
61c4628b	348	return tsk->thread.xstate->fxsave.swd;
1eeaed76	349	} else {
1679f271	350	return (unsigned short)tsk->thread.xstate->fsave.swd;
1eeaed76 RM	351	}
	352	}
	353
	354	static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
	355	{
	356	if (cpu_has_xmm) {
61c4628b	357	return tsk->thread.xstate->fxsave.mxcsr;
1eeaed76 RM	358	} else {
	359	return MXCSR_DEFAULT;
	360	}
	361	}
	362
77ef50a5	363	#endif /* ASM_X86__I387_H */