[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-x86 / geode.h

/*
 * AMD Geode definitions
 * Copyright (C) 2006, Advanced Micro Devices, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 */

#ifndef ASM_X86__GEODE_H
#define ASM_X86__GEODE_H

#include <asm/processor.h>
#include <linux/io.h>

/* Generic southbridge functions */

#define GEODE_DEV_PMS 0
#define GEODE_DEV_ACPI 1
#define GEODE_DEV_GPIO 2
#define GEODE_DEV_MFGPT 3

extern int geode_get_dev_base(unsigned int dev);

/* Useful macros */
#define geode_pms_base()	geode_get_dev_base(GEODE_DEV_PMS)
#define geode_acpi_base()	geode_get_dev_base(GEODE_DEV_ACPI)
#define geode_gpio_base()	geode_get_dev_base(GEODE_DEV_GPIO)
#define geode_mfgpt_base()	geode_get_dev_base(GEODE_DEV_MFGPT)

/* MSRS */

#define MSR_GLIU_P2D_RO0	0x10000029

#define MSR_LX_GLD_MSR_CONFIG	0x48002001
#define MSR_LX_MSR_PADSEL	0x48002011	/* NOT 0x48000011; the data
						 * sheet has the wrong value */
#define MSR_GLCP_SYS_RSTPLL	0x4C000014
#define MSR_GLCP_DOTPLL		0x4C000015

#define MSR_LBAR_SMB		0x5140000B
#define MSR_LBAR_GPIO		0x5140000C
#define MSR_LBAR_MFGPT		0x5140000D
#define MSR_LBAR_ACPI		0x5140000E
#define MSR_LBAR_PMS		0x5140000F

#define MSR_DIVIL_SOFT_RESET	0x51400017

#define MSR_PIC_YSEL_LOW	0x51400020
#define MSR_PIC_YSEL_HIGH	0x51400021
#define MSR_PIC_ZSEL_LOW	0x51400022
#define MSR_PIC_ZSEL_HIGH	0x51400023

#define MSR_MFGPT_IRQ		0x51400028
#define MSR_MFGPT_NR		0x51400029
#define MSR_MFGPT_SETUP		0x5140002B

#define MSR_LX_SPARE_MSR	0x80000011	/* DC-specific */

#define MSR_GX_GLD_MSR_CONFIG	0xC0002001
#define MSR_GX_MSR_PADSEL	0xC0002011

/* Resource Sizes */

#define LBAR_GPIO_SIZE		0xFF
#define LBAR_MFGPT_SIZE		0x40
#define LBAR_ACPI_SIZE		0x40
#define LBAR_PMS_SIZE		0x80

/* ACPI registers (PMS block) */

/*
 * PM1_EN is only valid when VSA is enabled for 16 bit reads.
 * When VSA is not enabled, *always* read both PM1_STS and PM1_EN
 * with a 32 bit read at offset 0x0
 */

#define PM1_STS			0x00
#define PM1_EN			0x02
#define PM1_CNT			0x08
#define PM2_CNT			0x0C
#define PM_TMR			0x10
#define PM_GPE0_STS		0x18
#define PM_GPE0_EN		0x1C

/* PMC registers (PMS block) */

#define PM_SSD			0x00
#define PM_SCXA			0x04
#define PM_SCYA			0x08
#define PM_OUT_SLPCTL		0x0C
#define PM_SCLK			0x10
#define PM_SED			0x1
#define PM_SCXD			0x18
#define PM_SCYD			0x1C
#define PM_IN_SLPCTL		0x20
#define PM_WKD			0x30
#define PM_WKXD			0x34
#define PM_RD			0x38
#define PM_WKXA			0x3C
#define PM_FSD			0x40
#define PM_TSD			0x44
#define PM_PSD			0x48
#define PM_NWKD			0x4C
#define PM_AWKD			0x50
#define PM_SSC			0x54

/* VSA2 magic values */

#define VSA_VRC_INDEX		0xAC1C
#define VSA_VRC_DATA		0xAC1E
#define VSA_VR_UNLOCK		0xFC53	/* unlock virtual register */
#define VSA_VR_SIGNATURE	0x0003
#define VSA_VR_MEM_SIZE		0x0200
#define AMD_VSA_SIG		0x4132	/* signature is ascii 'VSA2' */
#define GSW_VSA_SIG		0x534d  /* General Software signature */
/* GPIO */

#define GPIO_OUTPUT_VAL		0x00
#define GPIO_OUTPUT_ENABLE	0x04
#define GPIO_OUTPUT_OPEN_DRAIN	0x08
#define GPIO_OUTPUT_INVERT	0x0C
#define GPIO_OUTPUT_AUX1	0x10
#define GPIO_OUTPUT_AUX2	0x14
#define GPIO_PULL_UP		0x18
#define GPIO_PULL_DOWN		0x1C
#define GPIO_INPUT_ENABLE	0x20
#define GPIO_INPUT_INVERT	0x24
#define GPIO_INPUT_FILTER	0x28
#define GPIO_INPUT_EVENT_COUNT	0x2C
#define GPIO_READ_BACK		0x30
#define GPIO_INPUT_AUX1		0x34
#define GPIO_EVENTS_ENABLE	0x38
#define GPIO_LOCK_ENABLE	0x3C
#define GPIO_POSITIVE_EDGE_EN	0x40
#define GPIO_NEGATIVE_EDGE_EN	0x44
#define GPIO_POSITIVE_EDGE_STS	0x48
#define GPIO_NEGATIVE_EDGE_STS	0x4C

#define GPIO_MAP_X		0xE0
#define GPIO_MAP_Y		0xE4
#define GPIO_MAP_Z		0xE8
#define GPIO_MAP_W		0xEC

static inline u32 geode_gpio(unsigned int nr)
{
	BUG_ON(nr > 28);
	return 1 << nr;
}

extern void geode_gpio_set(u32, unsigned int);
extern void geode_gpio_clear(u32, unsigned int);
extern int geode_gpio_isset(u32, unsigned int);
extern void geode_gpio_setup_event(unsigned int, int, int);
extern void geode_gpio_set_irq(unsigned int, unsigned int);

static inline void geode_gpio_event_irq(unsigned int gpio, int pair)
{
	geode_gpio_setup_event(gpio, pair, 0);
}

static inline void geode_gpio_event_pme(unsigned int gpio, int pair)
{
	geode_gpio_setup_event(gpio, pair, 1);
}

/* Specific geode tests */

static inline int is_geode_gx(void)
{
	return ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC) &&
		(boot_cpu_data.x86 == 5) &&
		(boot_cpu_data.x86_model == 5));
}

static inline int is_geode_lx(void)
{
	return ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
		(boot_cpu_data.x86 == 5) &&
		(boot_cpu_data.x86_model == 10));
}

static inline int is_geode(void)
{
	return (is_geode_gx() || is_geode_lx());
}

#ifdef CONFIG_MGEODE_LX
extern int geode_has_vsa2(void);
#else
static inline int geode_has_vsa2(void)
{
	return 0;
}
#endif

/* MFGPTs */

#define MFGPT_MAX_TIMERS	8
#define MFGPT_TIMER_ANY		(-1)

#define MFGPT_DOMAIN_WORKING	1
#define MFGPT_DOMAIN_STANDBY	2
#define MFGPT_DOMAIN_ANY	(MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)

#define MFGPT_CMP1		0
#define MFGPT_CMP2		1

#define MFGPT_EVENT_IRQ		0
#define MFGPT_EVENT_NMI		1
#define MFGPT_EVENT_RESET	3

#define MFGPT_REG_CMP1		0
#define MFGPT_REG_CMP2		2
#define MFGPT_REG_COUNTER	4
#define MFGPT_REG_SETUP		6

#define MFGPT_SETUP_CNTEN	(1 << 15)
#define MFGPT_SETUP_CMP2	(1 << 14)
#define MFGPT_SETUP_CMP1	(1 << 13)
#define MFGPT_SETUP_SETUP	(1 << 12)
#define MFGPT_SETUP_STOPEN	(1 << 11)
#define MFGPT_SETUP_EXTEN	(1 << 10)
#define MFGPT_SETUP_REVEN	(1 << 5)
#define MFGPT_SETUP_CLKSEL	(1 << 4)

static inline void geode_mfgpt_write(int timer, u16 reg, u16 value)
{
	u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
	outw(value, base + reg + (timer * 8));
}

static inline u16 geode_mfgpt_read(int timer, u16 reg)
{
	u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
	return inw(base + reg + (timer * 8));
}

extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable);
extern int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable);
extern int geode_mfgpt_alloc_timer(int timer, int domain);

#define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1)
#define geode_mfgpt_release_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 0)

#ifdef CONFIG_GEODE_MFGPT_TIMER
extern int __init mfgpt_timer_setup(void);
#else
static inline int mfgpt_timer_setup(void) { return 0; }
#endif

#endif /* ASM_X86__GEODE_H */
Commit	Line	Data
f62e5184 AS	1	/*
	2	* AMD Geode definitions
	3	* Copyright (C) 2006, Advanced Micro Devices, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of version 2 of the GNU General Public License
	7	* as published by the Free Software Foundation.
	8	*/
	9
77ef50a5 VN	10	#ifndef ASM_X86__GEODE_H
77ef50a5 VN	11	#define ASM_X86__GEODE_H
f62e5184 AS	12
	13	#include <asm/processor.h>
	14	#include <linux/io.h>
	15
	16	/* Generic southbridge functions */
	17
	18	#define GEODE_DEV_PMS 0
	19	#define GEODE_DEV_ACPI 1
	20	#define GEODE_DEV_GPIO 2
	21	#define GEODE_DEV_MFGPT 3
	22
	23	extern int geode_get_dev_base(unsigned int dev);
	24
	25	/* Useful macros */
	26	#define geode_pms_base() geode_get_dev_base(GEODE_DEV_PMS)
	27	#define geode_acpi_base() geode_get_dev_base(GEODE_DEV_ACPI)
	28	#define geode_gpio_base() geode_get_dev_base(GEODE_DEV_GPIO)
	29	#define geode_mfgpt_base() geode_get_dev_base(GEODE_DEV_MFGPT)
	30
	31	/* MSRS */
	32
fd967956 AS	33	#define MSR_GLIU_P2D_RO0 0x10000029
fd967956 AS	34
32bf87e3 AS	35	#define MSR_LX_GLD_MSR_CONFIG 0x48002001
	36	#define MSR_LX_MSR_PADSEL 0x48002011 /* NOT 0x48000011; the data
	37	* sheet has the wrong value */
	38	#define MSR_GLCP_SYS_RSTPLL 0x4C000014
	39	#define MSR_GLCP_DOTPLL 0x4C000015
f62e5184 AS	40
	41	#define MSR_LBAR_SMB 0x5140000B
	42	#define MSR_LBAR_GPIO 0x5140000C
	43	#define MSR_LBAR_MFGPT 0x5140000D
	44	#define MSR_LBAR_ACPI 0x5140000E
	45	#define MSR_LBAR_PMS 0x5140000F
	46
0387f451 AS	47	#define MSR_DIVIL_SOFT_RESET 0x51400017
0387f451 AS	48
f62e5184 AS	49	#define MSR_PIC_YSEL_LOW 0x51400020
	50	#define MSR_PIC_YSEL_HIGH 0x51400021
	51	#define MSR_PIC_ZSEL_LOW 0x51400022
	52	#define MSR_PIC_ZSEL_HIGH 0x51400023
	53
32bf87e3 AS	54	#define MSR_MFGPT_IRQ 0x51400028
	55	#define MSR_MFGPT_NR 0x51400029
	56	#define MSR_MFGPT_SETUP 0x5140002B
	57
	58	#define MSR_LX_SPARE_MSR 0x80000011 /* DC-specific */
	59
	60	#define MSR_GX_GLD_MSR_CONFIG 0xC0002001
	61	#define MSR_GX_MSR_PADSEL 0xC0002011
f62e5184 AS	62
	63	/* Resource Sizes */
	64
	65	#define LBAR_GPIO_SIZE 0xFF
	66	#define LBAR_MFGPT_SIZE 0x40
	67	#define LBAR_ACPI_SIZE 0x40
	68	#define LBAR_PMS_SIZE 0x80
	69
	70	/* ACPI registers (PMS block) */
	71
	72	/*
	73	* PM1_EN is only valid when VSA is enabled for 16 bit reads.
	74	* When VSA is not enabled, always read both PM1_STS and PM1_EN
	75	* with a 32 bit read at offset 0x0
	76	*/
	77
	78	#define PM1_STS 0x00
	79	#define PM1_EN 0x02
	80	#define PM1_CNT 0x08
	81	#define PM2_CNT 0x0C
	82	#define PM_TMR 0x10
	83	#define PM_GPE0_STS 0x18
	84	#define PM_GPE0_EN 0x1C
	85
	86	/* PMC registers (PMS block) */
	87
	88	#define PM_SSD 0x00
	89	#define PM_SCXA 0x04
	90	#define PM_SCYA 0x08
	91	#define PM_OUT_SLPCTL 0x0C
	92	#define PM_SCLK 0x10
	93	#define PM_SED 0x1
	94	#define PM_SCXD 0x18
	95	#define PM_SCYD 0x1C
	96	#define PM_IN_SLPCTL 0x20
	97	#define PM_WKD 0x30
	98	#define PM_WKXD 0x34
	99	#define PM_RD 0x38
	100	#define PM_WKXA 0x3C
	101	#define PM_FSD 0x40
	102	#define PM_TSD 0x44
	103	#define PM_PSD 0x48
	104	#define PM_NWKD 0x4C
	105	#define PM_AWKD 0x50
	106	#define PM_SSC 0x54
	107
e9338364 AS	108	/* VSA2 magic values */
	109
	110	#define VSA_VRC_INDEX 0xAC1C
	111	#define VSA_VRC_DATA 0xAC1E
	112	#define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */
	113	#define VSA_VR_SIGNATURE 0x0003
61a517a0	114	#define VSA_VR_MEM_SIZE 0x0200
ffe6e1da JC	115	#define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
ffe6e1da JC	116	#define GSW_VSA_SIG 0x534d /* General Software signature */
f62e5184 AS	117	/* GPIO */
	118
	119	#define GPIO_OUTPUT_VAL 0x00
	120	#define GPIO_OUTPUT_ENABLE 0x04
	121	#define GPIO_OUTPUT_OPEN_DRAIN 0x08
	122	#define GPIO_OUTPUT_INVERT 0x0C
	123	#define GPIO_OUTPUT_AUX1 0x10
	124	#define GPIO_OUTPUT_AUX2 0x14
	125	#define GPIO_PULL_UP 0x18
	126	#define GPIO_PULL_DOWN 0x1C
	127	#define GPIO_INPUT_ENABLE 0x20
	128	#define GPIO_INPUT_INVERT 0x24
	129	#define GPIO_INPUT_FILTER 0x28
	130	#define GPIO_INPUT_EVENT_COUNT 0x2C
	131	#define GPIO_READ_BACK 0x30
	132	#define GPIO_INPUT_AUX1 0x34
	133	#define GPIO_EVENTS_ENABLE 0x38
	134	#define GPIO_LOCK_ENABLE 0x3C
	135	#define GPIO_POSITIVE_EDGE_EN 0x40
	136	#define GPIO_NEGATIVE_EDGE_EN 0x44
	137	#define GPIO_POSITIVE_EDGE_STS 0x48
	138	#define GPIO_NEGATIVE_EDGE_STS 0x4C
	139
	140	#define GPIO_MAP_X 0xE0
	141	#define GPIO_MAP_Y 0xE4
	142	#define GPIO_MAP_Z 0xE8
	143	#define GPIO_MAP_W 0xEC
	144
ade76149 AS	145	static inline u32 geode_gpio(unsigned int nr)
	146	{
	147	BUG_ON(nr > 28);
	148	return 1 << nr;
	149	}
	150
	151	extern void geode_gpio_set(u32, unsigned int);
	152	extern void geode_gpio_clear(u32, unsigned int);
	153	extern int geode_gpio_isset(u32, unsigned int);
f62e5184 AS	154	extern void geode_gpio_setup_event(unsigned int, int, int);
	155	extern void geode_gpio_set_irq(unsigned int, unsigned int);
	156
	157	static inline void geode_gpio_event_irq(unsigned int gpio, int pair)
	158	{
	159	geode_gpio_setup_event(gpio, pair, 0);
	160	}
	161
	162	static inline void geode_gpio_event_pme(unsigned int gpio, int pair)
	163	{
	164	geode_gpio_setup_event(gpio, pair, 1);
	165	}
	166
	167	/* Specific geode tests */
	168
	169	static inline int is_geode_gx(void)
	170	{
	171	return ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC) &&
	172	(boot_cpu_data.x86 == 5) &&
	173	(boot_cpu_data.x86_model == 5));
	174	}
	175
	176	static inline int is_geode_lx(void)
	177	{
	178	return ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
	179	(boot_cpu_data.x86 == 5) &&
	180	(boot_cpu_data.x86_model == 10));
	181	}
	182
	183	static inline int is_geode(void)
	184	{
	185	return (is_geode_gx() \|\| is_geode_lx());
	186	}
	187
cb3f43b2	188	#ifdef CONFIG_MGEODE_LX
547acec7	189	extern int geode_has_vsa2(void);
cb3f43b2 AS	190	#else
	191	static inline int geode_has_vsa2(void)
	192	{
	193	return 0;
	194	}
	195	#endif
e9338364	196
83d7384f AS	197	/* MFGPTs */
	198
	199	#define MFGPT_MAX_TIMERS 8
6394d982	200	#define MFGPT_TIMER_ANY (-1)
83d7384f AS	201
	202	#define MFGPT_DOMAIN_WORKING 1
	203	#define MFGPT_DOMAIN_STANDBY 2
	204	#define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING \| MFGPT_DOMAIN_STANDBY)
	205
	206	#define MFGPT_CMP1 0
	207	#define MFGPT_CMP2 1
	208
	209	#define MFGPT_EVENT_IRQ 0
	210	#define MFGPT_EVENT_NMI 1
	211	#define MFGPT_EVENT_RESET 3
	212
	213	#define MFGPT_REG_CMP1 0
	214	#define MFGPT_REG_CMP2 2
	215	#define MFGPT_REG_COUNTER 4
	216	#define MFGPT_REG_SETUP 6
	217
	218	#define MFGPT_SETUP_CNTEN (1 << 15)
	219	#define MFGPT_SETUP_CMP2 (1 << 14)
	220	#define MFGPT_SETUP_CMP1 (1 << 13)
	221	#define MFGPT_SETUP_SETUP (1 << 12)
	222	#define MFGPT_SETUP_STOPEN (1 << 11)
	223	#define MFGPT_SETUP_EXTEN (1 << 10)
	224	#define MFGPT_SETUP_REVEN (1 << 5)
	225	#define MFGPT_SETUP_CLKSEL (1 << 4)
	226
	227	static inline void geode_mfgpt_write(int timer, u16 reg, u16 value)
	228	{
	229	u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
	230	outw(value, base + reg + (timer * 8));
	231	}
	232
	233	static inline u16 geode_mfgpt_read(int timer, u16 reg)
	234	{
	235	u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
	236	return inw(base + reg + (timer * 8));
	237	}
	238
83d7384f AS	239	extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable);
83d7384f AS	240	extern int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable);
fa28e067	241	extern int geode_mfgpt_alloc_timer(int timer, int domain);
83d7384f AS	242
	243	#define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1)
	244	#define geode_mfgpt_release_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 0)
	245
b0e6bf25 AS	246	#ifdef CONFIG_GEODE_MFGPT_TIMER
	247	extern int __init mfgpt_timer_setup(void);
	248	#else
	249	static inline int mfgpt_timer_setup(void) { return 0; }
	250	#endif
	251
77ef50a5	252	#endif /* ASM_X86__GEODE_H */