[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-x86 / cache.h

#ifndef ASM_X86__CACHE_H
#define ASM_X86__CACHE_H

/* L1 cache line size */
#define L1_CACHE_SHIFT	(CONFIG_X86_L1_CACHE_SHIFT)
#define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)

#define __read_mostly __attribute__((__section__(".data.read_mostly")))

#ifdef CONFIG_X86_VSMP
/* vSMP Internode cacheline shift */
#define INTERNODE_CACHE_SHIFT (12)
#ifdef CONFIG_SMP
#define __cacheline_aligned_in_smp					\
	__attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))	\
	__attribute__((__section__(".data.page_aligned")))
#endif
#endif

#endif /* ASM_X86__CACHE_H */
Commit	Line	Data
77ef50a5 VN	1	#ifndef ASM_X86__CACHE_H
77ef50a5 VN	2	#define ASM_X86__CACHE_H
9bfa23df TG	3
	4	/* L1 cache line size */
	5	#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
	6	#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
	7
	8	#define __read_mostly __attribute__((__section__(".data.read_mostly")))
	9
	10	#ifdef CONFIG_X86_VSMP
	11	/* vSMP Internode cacheline shift */
	12	#define INTERNODE_CACHE_SHIFT (12)
	13	#ifdef CONFIG_SMP
	14	#define __cacheline_aligned_in_smp \
	15	__attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT)))) \
	16	__attribute__((__section__(".data.page_aligned")))
	17	#endif
	18	#endif
	19
77ef50a5	20	#endif /* ASM_X86__CACHE_H */