projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 88278ca2 | 1 | /* |
| 1da177e4 LT |
2 | * cypress.h: Cypress module specific definitions and defines. |
| 3 | * | |
| 4 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef _SPARC_CYPRESS_H | |
| 8 | #define _SPARC_CYPRESS_H | |
| 9 | ||
| 10 | /* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */ | |
| 11 | ||
| 12 | /* The MMU control register fields on the Sparc Cypress 604/605 MMU's. | |
| 13 | * | |
| 14 | * --------------------------------------------------------------- | |
| 15 | * |implvers| MCA | MCM |MV| MID |BM| C|RSV|MR|CM|CL|CE|RSV|NF|ME| | |
| 16 | * --------------------------------------------------------------- | |
| 17 | * 31 24 23-22 21-20 19 18-15 14 13 12 11 10 9 8 7-2 1 0 | |
| 18 | * | |
| 19 | * MCA: MultiChip Access -- Used for configuration of multiple | |
| 20 | * CY7C604/605 cache units. | |
| 21 | * MCM: MultiChip Mask -- Again, for multiple cache unit config. | |
| 22 | * MV: MultiChip Valid -- Indicates MCM and MCA have valid settings. | |
| 23 | * MID: ModuleID -- Unique processor ID for MBus transactions. (605 only) | |
| 24 | * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode | |
| 25 | * C: Cacheable -- Indicates whether accesses are cacheable while | |
| 26 | * the MMU is off. 0=no 1=yes | |
| 27 | * MR: MemoryReflection -- Indicates whether the bus attached to the | |
| 28 | * MBus supports memory reflection. 0=no 1=yes (605 only) | |
| 29 | * CM: CacheMode -- Indicates whether the cache is operating in write | |
| 30 | * through or copy-back mode. 0=write-through 1=copy-back | |
| 31 | * CL: CacheLock -- Indicates if the entire cache is locked or not. | |
| 32 | * 0=not-locked 1=locked (604 only) | |
| 33 | * CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes | |
| 34 | * NF: NoFault -- Do faults generate traps? 0=yes 1=no | |
| 35 | * ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes | |
| 36 | */ | |
| 37 | ||
| 38 | #define CYPRESS_MCA 0x00c00000 | |
| 39 | #define CYPRESS_MCM 0x00300000 | |
| 40 | #define CYPRESS_MVALID 0x00080000 | |
| 41 | #define CYPRESS_MIDMASK 0x00078000 /* Only on 605 */ | |
| 42 | #define CYPRESS_BMODE 0x00004000 | |
| 43 | #define CYPRESS_ACENABLE 0x00002000 | |
| 44 | #define CYPRESS_MRFLCT 0x00000800 /* Only on 605 */ | |
| 45 | #define CYPRESS_CMODE 0x00000400 | |
| 46 | #define CYPRESS_CLOCK 0x00000200 /* Only on 604 */ | |
| 47 | #define CYPRESS_CENABLE 0x00000100 | |
| 48 | #define CYPRESS_NFAULT 0x00000002 | |
| 49 | #define CYPRESS_MENABLE 0x00000001 | |
| 50 | ||
| 3115624e | 51 | static inline void cypress_flush_page(unsigned long page) |
| 1da177e4 LT |
52 | { |
| 53 | __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : | |
| 54 | "r" (page), "i" (ASI_M_FLUSH_PAGE)); | |
| 55 | } | |
| 56 | ||
| 3115624e | 57 | static inline void cypress_flush_segment(unsigned long addr) |
| 1da177e4 LT |
58 | { |
| 59 | __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : | |
| 60 | "r" (addr), "i" (ASI_M_FLUSH_SEG)); | |
| 61 | } | |
| 62 | ||
| 3115624e | 63 | static inline void cypress_flush_region(unsigned long addr) |
| 1da177e4 LT |
64 | { |
| 65 | __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : | |
| 66 | "r" (addr), "i" (ASI_M_FLUSH_REGION)); | |
| 67 | } | |
| 68 | ||
| 3115624e | 69 | static inline void cypress_flush_context(void) |
| 1da177e4 LT |
70 | { |
| 71 | __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : : | |
| 72 | "i" (ASI_M_FLUSH_CTX)); | |
| 73 | } | |
| 74 | ||
| 75 | /* XXX Displacement flushes for buggy chips and initial testing | |
| 76 | * XXX go here. | |
| 77 | */ | |
| 78 | ||
| 79 | #endif /* !(_SPARC_CYPRESS_H) */ |