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| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * include/asm-sh/cpu-sh3/cache.h | |
| 3 | * | |
| 4 | * Copyright (C) 1999 Niibe Yutaka | |
| 5 | * | |
| 6 | * This file is subject to the terms and conditions of the GNU General Public | |
| 7 | * License. See the file "COPYING" in the main directory of this archive | |
| 8 | * for more details. | |
| 9 | */ | |
| 10 | #ifndef __ASM_CPU_SH3_CACHE_H | |
| 11 | #define __ASM_CPU_SH3_CACHE_H | |
| 12 | ||
| 13 | #define L1_CACHE_SHIFT 4 | |
| 14 | ||
| 15 | #define CCR 0xffffffec /* Address of Cache Control Register */ | |
| 16 | ||
| 17 | #define CCR_CACHE_CE 0x01 /* Cache Enable */ | |
| 18 | #define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ | |
| 19 | #define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */ | |
| 20 | #define CCR_CACHE_CF 0x08 /* Cache Flush */ | |
| 21 | #define CCR_CACHE_ORA 0x20 /* RAM mode */ | |
| 22 | ||
| 23 | #define CACHE_OC_ADDRESS_ARRAY 0xf0000000 | |
| 24 | #define CACHE_PHYSADDR_MASK 0x1ffffc00 | |
| 25 | ||
| 26 | #define CCR_CACHE_ENABLE CCR_CACHE_CE | |
| 27 | #define CCR_CACHE_INVALIDATE CCR_CACHE_CF | |
| 28 | ||
| 29 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) | |
| 30 | #define CCR3 0xa40000b4 | |
| 31 | #define CCR_CACHE_16KB 0x00010000 | |
| 32 | #define CCR_CACHE_32KB 0x00020000 | |
| 33 | #endif | |
| 34 | ||
| 35 | ||
| 36 | #endif /* __ASM_CPU_SH3_CACHE_H */ | |
| 37 |