projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * include/asm-ppc/mpc83xx.h | |
| 3 | * | |
| 4 | * MPC83xx definitions | |
| 5 | * | |
| 4c8d3d99 | 6 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
| 1da177e4 LT |
7 | * |
| 8 | * Copyright 2005 Freescale Semiconductor, Inc | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify it | |
| 11 | * under the terms of the GNU General Public License as published by the | |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 13 | * option) any later version. | |
| 14 | */ | |
| 15 | ||
| 16 | #ifdef __KERNEL__ | |
| 17 | #ifndef __ASM_MPC83xx_H__ | |
| 18 | #define __ASM_MPC83xx_H__ | |
| 19 | ||
| 20 | #include <linux/config.h> | |
| 21 | #include <asm/mmu.h> | |
| 22 | ||
| 23 | #ifdef CONFIG_83xx | |
| 24 | ||
| 25 | #ifdef CONFIG_MPC834x_SYS | |
| 26 | #include <platforms/83xx/mpc834x_sys.h> | |
| 27 | #endif | |
| 28 | ||
| 29 | #define _IO_BASE isa_io_base | |
| 30 | #define _ISA_MEM_BASE isa_mem_base | |
| 31 | #ifdef CONFIG_PCI | |
| 32 | #define PCI_DRAM_OFFSET pci_dram_offset | |
| 33 | #else | |
| 34 | #define PCI_DRAM_OFFSET 0 | |
| 35 | #endif | |
| 36 | ||
| 37 | /* | |
| 38 | * The "residual" board information structure the boot loader passes | |
| 39 | * into the kernel. | |
| 40 | */ | |
| 41 | extern unsigned char __res[]; | |
| 42 | ||
| 43 | /* Internal IRQs on MPC83xx OpenPIC */ | |
| 44 | /* Not all of these exist on all MPC83xx implementations */ | |
| 45 | ||
| 46 | #ifndef MPC83xx_IPIC_IRQ_OFFSET | |
| 47 | #define MPC83xx_IPIC_IRQ_OFFSET 0 | |
| 48 | #endif | |
| 49 | ||
| 50 | #define NR_IPIC_INTS 128 | |
| 51 | ||
| 52 | #define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 53 | #define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 54 | #define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 55 | #define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 56 | #define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 57 | #define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 58 | #define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 59 | #define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 60 | #define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 61 | #define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 62 | #define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 63 | #define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 64 | #define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 65 | #define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 66 | #define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 67 | #define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 68 | #define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 69 | #define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 70 | #define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 71 | #define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 72 | #define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 73 | #define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 74 | #define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 75 | #define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 76 | #define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 77 | #define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 78 | #define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 79 | #define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 80 | #define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 81 | #define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 82 | #define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 83 | #define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 84 | #define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 85 | #define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 86 | #define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 87 | #define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 88 | #define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 89 | #define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 90 | #define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 91 | #define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 92 | #define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 93 | #define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 94 | #define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET) | |
| 95 | ||
| 96 | #define MPC83xx_CCSRBAR_SIZE (1024*1024) | |
| 97 | ||
| 98 | /* Let modules/drivers get at immrbar (physical) */ | |
| 99 | extern phys_addr_t immrbar; | |
| 100 | ||
| 101 | enum ppc_sys_devices { | |
| 102 | MPC83xx_TSEC1, | |
| 103 | MPC83xx_TSEC2, | |
| 104 | MPC83xx_IIC1, | |
| 105 | MPC83xx_IIC2, | |
| 106 | MPC83xx_DUART, | |
| 107 | MPC83xx_SEC2, | |
| 108 | MPC83xx_USB2_DR, | |
| 109 | MPC83xx_USB2_MPH, | |
| 78b33121 | 110 | MPC83xx_MDIO, |
| 1da177e4 LT |
111 | }; |
| 112 | ||
| 113 | #endif /* CONFIG_83xx */ | |
| 114 | #endif /* __ASM_MPC83xx_H__ */ | |
| 115 | #endif /* __KERNEL__ */ |