projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 14cf11af PM |
1 | /* |
| 2 | * Contains the definition of registers common to all PowerPC variants. | |
| 3 | * If a register definition has been changed in a different PowerPC | |
| 4 | * variant, we will case it in #ifndef XXX ... #endif, and have the | |
| 5 | * number used in the Programming Environments Manual For 32-Bit | |
| 6 | * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. | |
| 7 | */ | |
| 8 | ||
| 9f04b9e3 PM |
9 | #ifndef _ASM_POWERPC_REG_H |
| 10 | #define _ASM_POWERPC_REG_H | |
| 14cf11af | 11 | #ifdef __KERNEL__ |
| 14cf11af PM |
12 | |
| 13 | #include <linux/stringify.h> | |
| 9f04b9e3 | 14 | #include <asm/cputable.h> |
| 14cf11af PM |
15 | |
| 16 | /* Pickup Book E specific registers. */ | |
| 17 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) | |
| 18 | #include <asm/reg_booke.h> | |
| 26ef5c09 DG |
19 | #endif /* CONFIG_BOOKE || CONFIG_40x */ |
| 20 | ||
| 21 | #ifdef CONFIG_8xx | |
| 22 | #include <asm/reg_8xx.h> | |
| 23 | #endif /* CONFIG_8xx */ | |
| 14cf11af | 24 | |
| 9f04b9e3 PM |
25 | #define MSR_SF_LG 63 /* Enable 64 bit mode */ |
| 26 | #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ | |
| 27 | #define MSR_HV_LG 60 /* Hypervisor state */ | |
| 28 | #define MSR_VEC_LG 25 /* Enable AltiVec */ | |
| 29 | #define MSR_POW_LG 18 /* Enable Power Management */ | |
| 30 | #define MSR_WE_LG 18 /* Wait State Enable */ | |
| 31 | #define MSR_TGPR_LG 17 /* TLB Update registers in use */ | |
| 32 | #define MSR_CE_LG 17 /* Critical Interrupt Enable */ | |
| 33 | #define MSR_ILE_LG 16 /* Interrupt Little Endian */ | |
| 34 | #define MSR_EE_LG 15 /* External Interrupt Enable */ | |
| 35 | #define MSR_PR_LG 14 /* Problem State / Privilege Level */ | |
| 36 | #define MSR_FP_LG 13 /* Floating Point enable */ | |
| 37 | #define MSR_ME_LG 12 /* Machine Check Enable */ | |
| 38 | #define MSR_FE0_LG 11 /* Floating Exception mode 0 */ | |
| 39 | #define MSR_SE_LG 10 /* Single Step */ | |
| 40 | #define MSR_BE_LG 9 /* Branch Trace */ | |
| 41 | #define MSR_DE_LG 9 /* Debug Exception Enable */ | |
| 42 | #define MSR_FE1_LG 8 /* Floating Exception mode 1 */ | |
| 43 | #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */ | |
| 44 | #define MSR_IR_LG 5 /* Instruction Relocate */ | |
| 45 | #define MSR_DR_LG 4 /* Data Relocate */ | |
| 46 | #define MSR_PE_LG 3 /* Protection Enable */ | |
| 47 | #define MSR_PX_LG 2 /* Protection Exclusive Mode */ | |
| 48 | #define MSR_PMM_LG 2 /* Performance monitor */ | |
| 49 | #define MSR_RI_LG 1 /* Recoverable Exception */ | |
| 50 | #define MSR_LE_LG 0 /* Little Endian */ | |
| 14cf11af | 51 | |
| 9f04b9e3 PM |
52 | #ifdef __ASSEMBLY__ |
| 53 | #define __MASK(X) (1<<(X)) | |
| 54 | #else | |
| 55 | #define __MASK(X) (1UL<<(X)) | |
| 56 | #endif | |
| 57 | ||
| c032524f | 58 | #ifdef CONFIG_PPC64 |
| 9f04b9e3 PM |
59 | #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ |
| 60 | #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ | |
| 61 | #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ | |
| c032524f PM |
62 | #else |
| 63 | /* so tests for these bits fail on 32-bit */ | |
| 64 | #define MSR_SF 0 | |
| 65 | #define MSR_ISF 0 | |
| 66 | #define MSR_HV 0 | |
| 67 | #endif | |
| 68 | ||
| 9f04b9e3 PM |
69 | #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ |
| 70 | #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ | |
| 71 | #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ | |
| 72 | #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ | |
| 73 | #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ | |
| 74 | #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */ | |
| 75 | #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */ | |
| 76 | #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */ | |
| 77 | #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */ | |
| 78 | #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */ | |
| 79 | #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ | |
| 80 | #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */ | |
| 81 | #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */ | |
| 82 | #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */ | |
| 83 | #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */ | |
| 84 | #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */ | |
| 85 | #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ | |
| 86 | #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */ | |
| 87 | #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */ | |
| 88 | #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */ | |
| fd582ec8 | 89 | #ifndef MSR_PMM |
| 9f04b9e3 | 90 | #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */ |
| fd582ec8 | 91 | #endif |
| 9f04b9e3 PM |
92 | #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ |
| 93 | #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ | |
| 94 | ||
| 95 | #ifdef CONFIG_PPC64 | |
| 96 | #define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF | |
| 97 | #define MSR_KERNEL MSR_ | MSR_SF | MSR_HV | |
| 98 | ||
| 99 | #define MSR_USER32 MSR_ | MSR_PR | MSR_EE | |
| 100 | #define MSR_USER64 MSR_USER32 | MSR_SF | |
| 101 | ||
| 102 | #else /* 32-bit */ | |
| 14cf11af | 103 | /* Default MSR for kernel mode. */ |
| fd582ec8 | 104 | #ifndef MSR_KERNEL /* reg_booke.h also defines this */ |
| 14cf11af PM |
105 | #ifdef CONFIG_APUS_FAST_EXCEPT |
| 106 | #define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR) | |
| 9f04b9e3 | 107 | #else |
| 14cf11af PM |
108 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) |
| 109 | #endif | |
| fd582ec8 | 110 | #endif |
| 14cf11af PM |
111 | |
| 112 | #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) | |
| 9f04b9e3 | 113 | #endif |
| 14cf11af PM |
114 | |
| 115 | /* Floating Point Status and Control Register (FPSCR) Fields */ | |
| 116 | #define FPSCR_FX 0x80000000 /* FPU exception summary */ | |
| 117 | #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ | |
| 118 | #define FPSCR_VX 0x20000000 /* Invalid operation summary */ | |
| 119 | #define FPSCR_OX 0x10000000 /* Overflow exception summary */ | |
| 120 | #define FPSCR_UX 0x08000000 /* Underflow exception summary */ | |
| 121 | #define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */ | |
| 122 | #define FPSCR_XX 0x02000000 /* Inexact exception summary */ | |
| 123 | #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ | |
| 124 | #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ | |
| 125 | #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ | |
| 126 | #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ | |
| 127 | #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ | |
| 128 | #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ | |
| 129 | #define FPSCR_FR 0x00040000 /* Fraction rounded */ | |
| 130 | #define FPSCR_FI 0x00020000 /* Fraction inexact */ | |
| 131 | #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ | |
| 132 | #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ | |
| 133 | #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ | |
| 134 | #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ | |
| 135 | #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ | |
| 136 | #define FPSCR_VE 0x00000080 /* Invalid op exception enable */ | |
| 137 | #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ | |
| 138 | #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ | |
| 139 | #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ | |
| 140 | #define FPSCR_XE 0x00000008 /* FP inexact exception enable */ | |
| 141 | #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ | |
| 142 | #define FPSCR_RN 0x00000003 /* FPU rounding control */ | |
| 143 | ||
| 144 | /* Special Purpose Registers (SPRNs)*/ | |
| 145 | #define SPRN_CTR 0x009 /* Count Register */ | |
| 9f04b9e3 PM |
146 | #define SPRN_CTRLF 0x088 |
| 147 | #define SPRN_CTRLT 0x098 | |
| c902be71 AB |
148 | #define CTRL_CT 0xc0000000 /* current thread */ |
| 149 | #define CTRL_CT0 0x80000000 /* thread 0 */ | |
| 150 | #define CTRL_CT1 0x40000000 /* thread 1 */ | |
| 151 | #define CTRL_TE 0x00c00000 /* thread enable */ | |
| 9f04b9e3 | 152 | #define CTRL_RUNLATCH 0x1 |
| 14cf11af PM |
153 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ |
| 154 | #define DABR_TRANSLATION (1UL << 2) | |
| 155 | #define SPRN_DAR 0x013 /* Data Address Register */ | |
| 156 | #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ | |
| 157 | #define DSISR_NOHPTE 0x40000000 /* no translation found */ | |
| 158 | #define DSISR_PROTFAULT 0x08000000 /* protection fault */ | |
| 159 | #define DSISR_ISSTORE 0x02000000 /* access was a store */ | |
| 160 | #define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ | |
| 161 | #define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */ | |
| 162 | #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ | |
| 163 | #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ | |
| 164 | #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ | |
| 165 | #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ | |
| 166 | #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ | |
| 167 | #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ | |
| 168 | #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ | |
| 169 | #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ | |
| 170 | #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ | |
| 171 | #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ | |
| 172 | #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ | |
| 173 | #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ | |
| 174 | #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ | |
| 175 | #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ | |
| 176 | #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ | |
| 177 | #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ | |
| 178 | #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ | |
| 179 | #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ | |
| 180 | #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ | |
| 181 | #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ | |
| 182 | #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ | |
| 183 | ||
| 184 | #define SPRN_DEC 0x016 /* Decrement Register */ | |
| 185 | #define SPRN_DER 0x095 /* Debug Enable Regsiter */ | |
| 186 | #define DER_RSTE 0x40000000 /* Reset Interrupt */ | |
| 187 | #define DER_CHSTPE 0x20000000 /* Check Stop */ | |
| 188 | #define DER_MCIE 0x10000000 /* Machine Check Interrupt */ | |
| 189 | #define DER_EXTIE 0x02000000 /* External Interrupt */ | |
| 190 | #define DER_ALIE 0x01000000 /* Alignment Interrupt */ | |
| 191 | #define DER_PRIE 0x00800000 /* Program Interrupt */ | |
| 192 | #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */ | |
| 193 | #define DER_DECIE 0x00200000 /* Decrementer Interrupt */ | |
| 194 | #define DER_SYSIE 0x00040000 /* System Call Interrupt */ | |
| 195 | #define DER_TRE 0x00020000 /* Trace Interrupt */ | |
| 196 | #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */ | |
| 197 | #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */ | |
| 198 | #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */ | |
| 199 | #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */ | |
| 200 | #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */ | |
| 201 | #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */ | |
| 202 | #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */ | |
| 203 | #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ | |
| 204 | #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ | |
| 205 | #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ | |
| 206 | #define SPRN_EAR 0x11A /* External Address Register */ | |
| 207 | #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ | |
| 208 | #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ | |
| 209 | #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ | |
| 210 | #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ | |
| 211 | #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ | |
| 212 | #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ | |
| 213 | #define HID0_SBCLK (1<<27) | |
| 214 | #define HID0_EICE (1<<26) | |
| 215 | #define HID0_TBEN (1<<26) /* Timebase enable - 745x */ | |
| 216 | #define HID0_ECLK (1<<25) | |
| 217 | #define HID0_PAR (1<<24) | |
| 218 | #define HID0_STEN (1<<24) /* Software table search enable - 745x */ | |
| 219 | #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */ | |
| 220 | #define HID0_DOZE (1<<23) | |
| 221 | #define HID0_NAP (1<<22) | |
| 222 | #define HID0_SLEEP (1<<21) | |
| 223 | #define HID0_DPM (1<<20) | |
| 224 | #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ | |
| 225 | #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ | |
| 226 | #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ | |
| 227 | #define HID0_ICE (1<<15) /* Instruction Cache Enable */ | |
| 228 | #define HID0_DCE (1<<14) /* Data Cache Enable */ | |
| 229 | #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ | |
| 230 | #define HID0_DLOCK (1<<12) /* Data Cache Lock */ | |
| 231 | #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ | |
| 232 | #define HID0_DCI (1<<10) /* Data Cache Invalidate */ | |
| 233 | #define HID0_SPD (1<<9) /* Speculative disable */ | |
| 234 | #define HID0_DAPUEN (1<<8) /* Debug APU enable */ | |
| 235 | #define HID0_SGE (1<<7) /* Store Gathering Enable */ | |
| 236 | #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ | |
| 237 | #define HID0_DFCA (1<<6) /* Data Cache Flush Assist */ | |
| 238 | #define HID0_LRSTK (1<<4) /* Link register stack - 745x */ | |
| 239 | #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ | |
| 240 | #define HID0_ABE (1<<3) /* Address Broadcast Enable */ | |
| 241 | #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */ | |
| 242 | #define HID0_BHTE (1<<2) /* Branch History Table Enable */ | |
| 243 | #define HID0_BTCD (1<<1) /* Branch target cache disable */ | |
| 244 | #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ | |
| 245 | #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ | |
| 246 | ||
| 247 | #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ | |
| 248 | #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ | |
| 249 | #define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ | |
| 250 | #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ | |
| 251 | #define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ | |
| 252 | #define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ | |
| 253 | #define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ | |
| 254 | #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ | |
| 255 | #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ | |
| 256 | #define HID1_PS (1<<16) /* 750FX PLL selection */ | |
| 257 | #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ | |
| 258 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ | |
| 259 | #define SPRN_HID4 0x3F4 /* 970 HID4 */ | |
| 260 | #define SPRN_HID5 0x3F6 /* 970 HID5 */ | |
| 9f04b9e3 PM |
261 | #define SPRN_HID6 0x3F9 /* BE HID 6 */ |
| 262 | #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ | |
| 263 | #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ | |
| c902be71 AB |
264 | #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ |
| 265 | #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ | |
| 266 | #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ | |
| 267 | #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ | |
| 268 | #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ | |
| 9f04b9e3 PM |
269 | #define SPRN_TSC 0x3FD /* Thread switch control on others */ |
| 270 | #define SPRN_TST 0x3FC /* Thread switch timeout on others */ | |
| 14cf11af PM |
271 | #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) |
| 272 | #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ | |
| 273 | #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ | |
| 274 | #endif | |
| 275 | #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ | |
| 276 | #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ | |
| 277 | #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ | |
| 278 | #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ | |
| 279 | #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ | |
| 280 | #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ | |
| 281 | #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ | |
| 282 | #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ | |
| 283 | #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ | |
| 284 | #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ | |
| 285 | #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ | |
| 286 | #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ | |
| 287 | #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ | |
| 288 | #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ | |
| 289 | #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ | |
| 290 | #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ | |
| 291 | #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ | |
| 292 | #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ | |
| 293 | #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ | |
| 294 | #define ICTRL_EICE 0x08000000 /* enable icache parity errs */ | |
| 295 | #define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ | |
| 296 | #define ICTRL_EICP 0x00000100 /* enable icache par. check */ | |
| 297 | #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ | |
| 298 | #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ | |
| 299 | #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ | |
| 300 | #define SPRN_L2CR2 0x3f8 | |
| 301 | #define L2CR_L2E 0x80000000 /* L2 enable */ | |
| 302 | #define L2CR_L2PE 0x40000000 /* L2 parity enable */ | |
| 303 | #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */ | |
| 304 | #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */ | |
| 305 | #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */ | |
| 306 | #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */ | |
| 307 | #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */ | |
| 308 | #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */ | |
| 309 | #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */ | |
| 310 | #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */ | |
| 311 | #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */ | |
| 312 | #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */ | |
| 313 | #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */ | |
| 314 | #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */ | |
| 315 | #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */ | |
| 316 | #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */ | |
| 317 | #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */ | |
| 318 | #define L2CR_L2DO 0x00400000 /* L2 data only */ | |
| 319 | #define L2CR_L2I 0x00200000 /* L2 global invalidate */ | |
| 320 | #define L2CR_L2CTL 0x00100000 /* L2 RAM control */ | |
| 321 | #define L2CR_L2WT 0x00080000 /* L2 write-through */ | |
| 322 | #define L2CR_L2TS 0x00040000 /* L2 test support */ | |
| 323 | #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */ | |
| 324 | #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */ | |
| 325 | #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */ | |
| 326 | #define L2CR_L2SL 0x00008000 /* L2 DLL slow */ | |
| 327 | #define L2CR_L2DF 0x00004000 /* L2 differential clock */ | |
| 328 | #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ | |
| 329 | #define L2CR_L2IP 0x00000001 /* L2 GI in progress */ | |
| 330 | #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */ | |
| 331 | #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */ | |
| 332 | #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */ | |
| 333 | #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */ | |
| 334 | #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */ | |
| 335 | #define L3CR_L3E 0x80000000 /* L3 enable */ | |
| 336 | #define L3CR_L3PE 0x40000000 /* L3 data parity enable */ | |
| 337 | #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ | |
| 338 | #define L3CR_L3SIZ 0x10000000 /* L3 size */ | |
| 339 | #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ | |
| 340 | #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ | |
| 341 | #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ | |
| 342 | #define L3CR_L3IO 0x00400000 /* L3 instruction only */ | |
| 343 | #define L3CR_L3SPO 0x00040000 /* L3 sample point override */ | |
| 344 | #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ | |
| 345 | #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ | |
| 346 | #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ | |
| 347 | #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ | |
| 348 | #define L3CR_L3I 0x00000400 /* L3 global invalidate */ | |
| 349 | #define L3CR_L3RT 0x00000300 /* L3 SRAM type */ | |
| 350 | #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ | |
| 351 | #define L3CR_L3DO 0x00000040 /* L3 data only mode */ | |
| 352 | #define L3CR_PMEN 0x00000004 /* L3 private memory enable */ | |
| 353 | #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */ | |
| 9f04b9e3 | 354 | |
| 14cf11af PM |
355 | #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ |
| 356 | #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ | |
| 357 | #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ | |
| 358 | #define SPRN_LDSTDB 0x3f4 /* */ | |
| 359 | #define SPRN_LR 0x008 /* Link Register */ | |
| 14cf11af PM |
360 | #ifndef SPRN_PIR |
| 361 | #define SPRN_PIR 0x3FF /* Processor Identification Register */ | |
| 362 | #endif | |
| 14cf11af PM |
363 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ |
| 364 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ | |
| 9f04b9e3 | 365 | #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ |
| 14cf11af PM |
366 | #define SPRN_PVR 0x11F /* Processor Version Register */ |
| 367 | #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ | |
| 368 | #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ | |
| 369 | #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ | |
| 799d6046 | 370 | #define SPRN_ASR 0x118 /* Address Space Register */ |
| 14cf11af PM |
371 | #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ |
| 372 | #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ | |
| 373 | #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ | |
| 374 | #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ | |
| 375 | #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ | |
| 376 | #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ | |
| 377 | #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ | |
| 378 | #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ | |
| 379 | #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ | |
| 380 | #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ | |
| 381 | #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ | |
| c902be71 AB |
382 | #define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ |
| 383 | #define SRR1_WAKERESET 0x00380000 /* System reset */ | |
| 384 | #define SRR1_WAKESYSERR 0x00300000 /* System error */ | |
| 385 | #define SRR1_WAKEEE 0x00200000 /* External interrupt */ | |
| 386 | #define SRR1_WAKEMT 0x00280000 /* mtctrl */ | |
| 387 | #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ | |
| 388 | #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ | |
| 389 | ||
| 14cf11af PM |
390 | #ifndef SPRN_SVR |
| 391 | #define SPRN_SVR 0x11E /* System Version Register */ | |
| 392 | #endif | |
| 393 | #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ | |
| 394 | /* these bits were defined in inverted endian sense originally, ugh, confusing */ | |
| 395 | #define THRM1_TIN (1 << 31) | |
| 396 | #define THRM1_TIV (1 << 30) | |
| 397 | #define THRM1_THRES(x) ((x&0x7f)<<23) | |
| 398 | #define THRM3_SITV(x) ((x&0x3fff)<<1) | |
| 399 | #define THRM1_TID (1<<2) | |
| 400 | #define THRM1_TIE (1<<1) | |
| 401 | #define THRM1_V (1<<0) | |
| 402 | #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ | |
| 403 | #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ | |
| 404 | #define THRM3_E (1<<0) | |
| 405 | #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ | |
| 406 | #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ | |
| 407 | #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ | |
| 408 | #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ | |
| 409 | #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ | |
| 410 | #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ | |
| 411 | #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ | |
| 412 | #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ | |
| 413 | #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ | |
| 414 | #define SPRN_XER 0x001 /* Fixed Point Exception Register */ | |
| 415 | ||
| 4350147a BH |
416 | #define SPRN_SCOMC 0x114 /* SCOM Access Control */ |
| 417 | #define SPRN_SCOMD 0x115 /* SCOM Access DATA */ | |
| 418 | ||
| 9f04b9e3 PM |
419 | /* Performance monitor SPRs */ |
| 420 | #ifdef CONFIG_PPC64 | |
| 421 | #define SPRN_MMCR0 795 | |
| 422 | #define MMCR0_FC 0x80000000UL /* freeze counters */ | |
| 423 | #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ | |
| 424 | #define MMCR0_KERNEL_DISABLE MMCR0_FCS | |
| 425 | #define MMCR0_FCP 0x20000000UL /* freeze in problem state */ | |
| 426 | #define MMCR0_PROBLEM_DISABLE MMCR0_FCP | |
| 427 | #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ | |
| 428 | #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ | |
| 429 | #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ | |
| 430 | #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ | |
| 431 | #define MMCR0_TBEE 0x00400000UL /* time base exception enable */ | |
| 432 | #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ | |
| 433 | #define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/ | |
| 434 | #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ | |
| 435 | #define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */ | |
| 436 | #define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ | |
| 437 | #define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ | |
| 438 | #define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ | |
| 439 | #define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ | |
| 440 | #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ | |
| 441 | #define SPRN_MMCR1 798 | |
| 442 | #define SPRN_MMCRA 0x312 | |
| 443 | #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ | |
| 444 | #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ | |
| 445 | #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ | |
| 446 | #define SPRN_PMC1 787 | |
| 447 | #define SPRN_PMC2 788 | |
| 448 | #define SPRN_PMC3 789 | |
| 449 | #define SPRN_PMC4 790 | |
| 450 | #define SPRN_PMC5 791 | |
| 451 | #define SPRN_PMC6 792 | |
| 452 | #define SPRN_PMC7 793 | |
| 453 | #define SPRN_PMC8 794 | |
| 454 | #define SPRN_SIAR 780 | |
| 455 | #define SPRN_SDAR 781 | |
| 456 | ||
| 457 | #else /* 32-bit */ | |
| 555d97ac AF |
458 | #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ |
| 459 | #define MMCR0_FC 0x80000000UL /* freeze counters */ | |
| 460 | #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ | |
| 461 | #define MMCR0_FCP 0x20000000UL /* freeze in problem state */ | |
| 462 | #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ | |
| 463 | #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ | |
| 464 | #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ | |
| 465 | #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ | |
| 466 | #define MMCR0_TBEE 0x00400000UL /* time base exception enable */ | |
| 467 | #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ | |
| 468 | #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/ | |
| 469 | #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ | |
| 470 | #define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */ | |
| 471 | #define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */ | |
| 472 | ||
| 473 | #define SPRN_MMCR1 956 | |
| 474 | #define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */ | |
| 475 | #define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */ | |
| 476 | #define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */ | |
| 477 | #define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */ | |
| 478 | #define SPRN_MMCR2 944 | |
| 479 | #define SPRN_PMC1 953 /* Performance Counter Register 1 */ | |
| 480 | #define SPRN_PMC2 954 /* Performance Counter Register 2 */ | |
| 481 | #define SPRN_PMC3 957 /* Performance Counter Register 3 */ | |
| 482 | #define SPRN_PMC4 958 /* Performance Counter Register 4 */ | |
| 483 | #define SPRN_PMC5 945 /* Performance Counter Register 5 */ | |
| 484 | #define SPRN_PMC6 946 /* Performance Counter Register 6 */ | |
| 485 | ||
| 486 | #define SPRN_SIAR 955 /* Sampled Instruction Address Register */ | |
| 9f04b9e3 | 487 | |
| 14cf11af PM |
488 | /* Bit definitions for MMCR0 and PMC1 / PMC2. */ |
| 489 | #define MMCR0_PMC1_CYCLES (1 << 7) | |
| 490 | #define MMCR0_PMC1_ICACHEMISS (5 << 7) | |
| 491 | #define MMCR0_PMC1_DTLB (6 << 7) | |
| 492 | #define MMCR0_PMC2_DCACHEMISS 0x6 | |
| 493 | #define MMCR0_PMC2_CYCLES 0x1 | |
| 494 | #define MMCR0_PMC2_ITLB 0x7 | |
| 495 | #define MMCR0_PMC2_LOADMISSTIME 0x5 | |
| 9f04b9e3 | 496 | #endif |
| 14cf11af PM |
497 | |
| 498 | /* Processor Version Register (PVR) field extraction */ | |
| 499 | ||
| 500 | #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ | |
| 501 | #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ | |
| 502 | ||
| 9f04b9e3 PM |
503 | #define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv)) |
| 504 | ||
| 14cf11af PM |
505 | /* |
| 506 | * IBM has further subdivided the standard PowerPC 16-bit version and | |
| 507 | * revision subfields of the PVR for the PowerPC 403s into the following: | |
| 508 | */ | |
| 509 | ||
| 510 | #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ | |
| 511 | #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ | |
| 512 | #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ | |
| 513 | #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ | |
| 514 | #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ | |
| 515 | #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ | |
| 516 | ||
| 517 | /* Processor Version Numbers */ | |
| 518 | ||
| 519 | #define PVR_403GA 0x00200000 | |
| 520 | #define PVR_403GB 0x00200100 | |
| 521 | #define PVR_403GC 0x00200200 | |
| 522 | #define PVR_403GCX 0x00201400 | |
| 523 | #define PVR_405GP 0x40110000 | |
| 524 | #define PVR_STB03XXX 0x40310000 | |
| 525 | #define PVR_NP405H 0x41410000 | |
| 526 | #define PVR_NP405L 0x41610000 | |
| 527 | #define PVR_601 0x00010000 | |
| 528 | #define PVR_602 0x00050000 | |
| 529 | #define PVR_603 0x00030000 | |
| 530 | #define PVR_603e 0x00060000 | |
| 531 | #define PVR_603ev 0x00070000 | |
| 532 | #define PVR_603r 0x00071000 | |
| 533 | #define PVR_604 0x00040000 | |
| 534 | #define PVR_604e 0x00090000 | |
| 535 | #define PVR_604r 0x000A0000 | |
| 536 | #define PVR_620 0x00140000 | |
| 537 | #define PVR_740 0x00080000 | |
| 538 | #define PVR_750 PVR_740 | |
| 539 | #define PVR_740P 0x10080000 | |
| 540 | #define PVR_750P PVR_740P | |
| 541 | #define PVR_7400 0x000C0000 | |
| 542 | #define PVR_7410 0x800C0000 | |
| 543 | #define PVR_7450 0x80000000 | |
| 544 | #define PVR_8540 0x80200000 | |
| 545 | #define PVR_8560 0x80200000 | |
| 546 | /* | |
| 547 | * For the 8xx processors, all of them report the same PVR family for | |
| 548 | * the PowerPC core. The various versions of these processors must be | |
| 549 | * differentiated by the version number in the Communication Processor | |
| 550 | * Module (CPM). | |
| 551 | */ | |
| 552 | #define PVR_821 0x00500000 | |
| 553 | #define PVR_823 PVR_821 | |
| 554 | #define PVR_850 PVR_821 | |
| 555 | #define PVR_860 PVR_821 | |
| 556 | #define PVR_8240 0x00810100 | |
| 557 | #define PVR_8245 0x80811014 | |
| 558 | #define PVR_8260 PVR_8240 | |
| 559 | ||
| 9f04b9e3 PM |
560 | /* 64-bit processors */ |
| 561 | /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */ | |
| 562 | #define PV_NORTHSTAR 0x0033 | |
| 563 | #define PV_PULSAR 0x0034 | |
| 564 | #define PV_POWER4 0x0035 | |
| 565 | #define PV_ICESTAR 0x0036 | |
| 566 | #define PV_SSTAR 0x0037 | |
| 567 | #define PV_POWER4p 0x0038 | |
| 568 | #define PV_970 0x0039 | |
| 569 | #define PV_POWER5 0x003A | |
| 570 | #define PV_POWER5p 0x003B | |
| 571 | #define PV_970FX 0x003C | |
| 572 | #define PV_630 0x0040 | |
| 573 | #define PV_630p 0x0041 | |
| 574 | #define PV_970MP 0x0044 | |
| 575 | #define PV_BE 0x0070 | |
| 576 | ||
| 577 | /* | |
| 578 | * Number of entries in the SLB. If this ever changes we should handle | |
| 579 | * it with a use a cpu feature fixup. | |
| 580 | */ | |
| 581 | #define SLB_NUM_ENTRIES 64 | |
| 14cf11af PM |
582 | |
| 583 | /* Macros for setting and retrieving special purpose registers */ | |
| 584 | #ifndef __ASSEMBLY__ | |
| 9f04b9e3 | 585 | #define mfmsr() ({unsigned long rval; \ |
| 14cf11af | 586 | asm volatile("mfmsr %0" : "=r" (rval)); rval;}) |
| 9f04b9e3 PM |
587 | #ifdef CONFIG_PPC64 |
| 588 | #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ | |
| 589 | : : "r" (v)) | |
| 590 | #define mtmsrd(v) __mtmsrd((v), 0) | |
| f78541dc | 591 | #define mtmsr(v) mtmsrd(v) |
| 9f04b9e3 | 592 | #else |
| 14cf11af | 593 | #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) |
| 9f04b9e3 | 594 | #endif |
| 14cf11af | 595 | |
| 9f04b9e3 | 596 | #define mfspr(rn) ({unsigned long rval; \ |
| 14cf11af PM |
597 | asm volatile("mfspr %0," __stringify(rn) \ |
| 598 | : "=r" (rval)); rval;}) | |
| 599 | #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) | |
| 600 | ||
| 9f04b9e3 PM |
601 | #define mftb() ({unsigned long rval; \ |
| 602 | asm volatile("mftb %0" : "=r" (rval)); rval;}) | |
| 603 | #define mftbl() ({unsigned long rval; \ | |
| 604 | asm volatile("mftbl %0" : "=r" (rval)); rval;}) | |
| 605 | ||
| 606 | #define mttbl(v) asm volatile("mttbl %0":: "r"(v)) | |
| 607 | #define mttbu(v) asm volatile("mttbu %0":: "r"(v)) | |
| 608 | ||
| 609 | #ifdef CONFIG_PPC32 | |
| 14cf11af PM |
610 | #define mfsrin(v) ({unsigned int rval; \ |
| 611 | asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ | |
| 612 | rval;}) | |
| 9f04b9e3 | 613 | #endif |
| 14cf11af PM |
614 | |
| 615 | #define proc_trap() asm volatile("trap") | |
| 9f04b9e3 PM |
616 | |
| 617 | #ifdef CONFIG_PPC64 | |
| 618 | static inline void ppc64_runlatch_on(void) | |
| 619 | { | |
| 620 | unsigned long ctrl; | |
| 621 | ||
| 622 | if (cpu_has_feature(CPU_FTR_CTRL)) { | |
| 623 | ctrl = mfspr(SPRN_CTRLF); | |
| 624 | ctrl |= CTRL_RUNLATCH; | |
| 625 | mtspr(SPRN_CTRLT, ctrl); | |
| 626 | } | |
| 627 | } | |
| 628 | ||
| 629 | static inline void ppc64_runlatch_off(void) | |
| 630 | { | |
| 631 | unsigned long ctrl; | |
| 632 | ||
| 633 | if (cpu_has_feature(CPU_FTR_CTRL)) { | |
| 634 | ctrl = mfspr(SPRN_CTRLF); | |
| 635 | ctrl &= ~CTRL_RUNLATCH; | |
| 636 | mtspr(SPRN_CTRLT, ctrl); | |
| 637 | } | |
| 638 | } | |
| 4350147a BH |
639 | |
| 640 | extern unsigned long scom970_read(unsigned int address); | |
| 641 | extern void scom970_write(unsigned int address, unsigned long value); | |
| 642 | ||
| 643 | #endif /* CONFIG_PPC64 */ | |
| 9f04b9e3 PM |
644 | |
| 645 | #define __get_SP() ({unsigned long sp; \ | |
| 646 | asm volatile("mr %0,1": "=r" (sp)); sp;}) | |
| 647 | ||
| 648 | #else /* __ASSEMBLY__ */ | |
| 649 | ||
| 650 | #define RUNLATCH_ON(REG) \ | |
| 651 | BEGIN_FTR_SECTION \ | |
| 652 | mfspr (REG),SPRN_CTRLF; \ | |
| 653 | ori (REG),(REG),CTRL_RUNLATCH; \ | |
| 654 | mtspr SPRN_CTRLT,(REG); \ | |
| 655 | END_FTR_SECTION_IFSET(CPU_FTR_CTRL) | |
| 656 | ||
| 14cf11af | 657 | #endif /* __ASSEMBLY__ */ |
| 14cf11af | 658 | #endif /* __KERNEL__ */ |
| 9f04b9e3 | 659 | #endif /* _ASM_POWERPC_REG_H */ |