projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 40afa531 | 1 | /* |
| afea3278 | 2 | * Copyright (C) 2006-2008 PA Semi, Inc |
| 40afa531 OJ |
3 | * |
| 4 | * Hardware register layout and descriptor formats for the on-board | |
| 5 | * DMA engine on PA Semi PWRficient. Used by ethernet, function and security | |
| 6 | * drivers. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef ASM_PASEMI_DMA_H | |
| 23 | #define ASM_PASEMI_DMA_H | |
| 24 | ||
| 25 | /* status register layout in IOB region, at 0xfb800000 */ | |
| 26 | struct pasdma_status { | |
| 27 | u64 rx_sta[64]; /* RX channel status */ | |
| 28 | u64 tx_sta[20]; /* TX channel status */ | |
| 29 | }; | |
| 30 | ||
| 31 | ||
| 32 | /* All these registers live in the PCI configuration space for the DMA PCI | |
| 33 | * device. Use the normal PCI config access functions for them. | |
| 34 | */ | |
| 35 | enum { | |
| 8ee9d857 OJ |
36 | PAS_DMA_CAP_TXCH = 0x44, /* Transmit Channel Info */ |
| 37 | PAS_DMA_CAP_RXCH = 0x48, /* Transmit Channel Info */ | |
| 38 | PAS_DMA_CAP_IFI = 0x4c, /* Interface Info */ | |
| 40afa531 OJ |
39 | PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ |
| 40 | PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ | |
| 41 | PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ | |
| 42 | PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ | |
| afea3278 OJ |
43 | PAS_DMA_COM_CFG = 0x114, /* Common config reg */ |
| 44 | PAS_DMA_TXF_SFLG0 = 0x140, /* Set flags */ | |
| 45 | PAS_DMA_TXF_SFLG1 = 0x144, /* Set flags */ | |
| 46 | PAS_DMA_TXF_CFLG0 = 0x148, /* Set flags */ | |
| 47 | PAS_DMA_TXF_CFLG1 = 0x14c, /* Set flags */ | |
| 40afa531 | 48 | }; |
| 8ee9d857 OJ |
49 | |
| 50 | ||
| 51 | #define PAS_DMA_CAP_TXCH_TCHN_M 0x00ff0000 /* # of TX channels */ | |
| 52 | #define PAS_DMA_CAP_TXCH_TCHN_S 16 | |
| 53 | ||
| 54 | #define PAS_DMA_CAP_RXCH_RCHN_M 0x00ff0000 /* # of RX channels */ | |
| 55 | #define PAS_DMA_CAP_RXCH_RCHN_S 16 | |
| 56 | ||
| 57 | #define PAS_DMA_CAP_IFI_IOFF_M 0xff000000 /* Cfg reg for intf pointers */ | |
| 58 | #define PAS_DMA_CAP_IFI_IOFF_S 24 | |
| 59 | #define PAS_DMA_CAP_IFI_NIN_M 0x00ff0000 /* # of interfaces */ | |
| 60 | #define PAS_DMA_CAP_IFI_NIN_S 16 | |
| 61 | ||
| 40afa531 OJ |
62 | #define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ |
| 63 | #define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ | |
| 64 | #define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ | |
| 65 | #define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ | |
| 66 | ||
| 67 | ||
| 68 | /* Per-interface and per-channel registers */ | |
| 69 | #define _PAS_DMA_RXINT_STRIDE 0x20 | |
| 70 | #define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE) | |
| 71 | #define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001 | |
| 72 | #define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002 | |
| 73 | #define PAS_DMA_RXINT_RCMDSTA_MBT 0x00000008 | |
| 74 | #define PAS_DMA_RXINT_RCMDSTA_MDR 0x00000010 | |
| 75 | #define PAS_DMA_RXINT_RCMDSTA_MOO 0x00000020 | |
| 76 | #define PAS_DMA_RXINT_RCMDSTA_MBP 0x00000040 | |
| 77 | #define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800 | |
| 78 | #define PAS_DMA_RXINT_RCMDSTA_DR 0x00001000 | |
| 79 | #define PAS_DMA_RXINT_RCMDSTA_OO 0x00002000 | |
| 80 | #define PAS_DMA_RXINT_RCMDSTA_BP 0x00004000 | |
| 81 | #define PAS_DMA_RXINT_RCMDSTA_TB 0x00008000 | |
| 82 | #define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000 | |
| 83 | #define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000 | |
| 84 | #define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17 | |
| 85 | #define PAS_DMA_RXINT_CFG(i) (0x204+(i)*_PAS_DMA_RXINT_STRIDE) | |
| 86 | #define PAS_DMA_RXINT_CFG_RBP 0x80000000 | |
| 87 | #define PAS_DMA_RXINT_CFG_ITRR 0x40000000 | |
| 88 | #define PAS_DMA_RXINT_CFG_DHL_M 0x07000000 | |
| 89 | #define PAS_DMA_RXINT_CFG_DHL_S 24 | |
| 90 | #define PAS_DMA_RXINT_CFG_DHL(x) (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \ | |
| 91 | PAS_DMA_RXINT_CFG_DHL_M) | |
| 92 | #define PAS_DMA_RXINT_CFG_ITR 0x00400000 | |
| 93 | #define PAS_DMA_RXINT_CFG_LW 0x00200000 | |
| 94 | #define PAS_DMA_RXINT_CFG_L2 0x00100000 | |
| 95 | #define PAS_DMA_RXINT_CFG_HEN 0x00080000 | |
| 96 | #define PAS_DMA_RXINT_CFG_WIF 0x00000002 | |
| 97 | #define PAS_DMA_RXINT_CFG_WIL 0x00000001 | |
| 98 | ||
| 99 | #define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE) | |
| 100 | #define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff | |
| 101 | #define PAS_DMA_RXINT_INCR_INCR_S 0 | |
| 102 | #define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff) | |
| 103 | #define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE) | |
| 104 | #define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f) | |
| 105 | #define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE) | |
| 106 | #define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff) | |
| 107 | #define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */ | |
| 108 | #define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */ | |
| 109 | #define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \ | |
| 110 | PAS_DMA_RXINT_BASEU_SIZ_M) | |
| 111 | ||
| 112 | ||
| 113 | #define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ | |
| 114 | #define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ | |
| 115 | #define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ | |
| 116 | #define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ | |
| 117 | #define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ | |
| 118 | #define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ | |
| 119 | #define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ | |
| 120 | #define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ | |
| 121 | #define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) | |
| 122 | #define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ | |
| 123 | #define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ | |
| 124 | #define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ | |
| 125 | #define PAS_DMA_TXCHAN_TCMDSTA_SZ 0x00000800 | |
| 126 | #define PAS_DMA_TXCHAN_TCMDSTA_DB 0x00000400 | |
| 127 | #define PAS_DMA_TXCHAN_TCMDSTA_DE 0x00000200 | |
| 128 | #define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100 | |
| 129 | #define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) | |
| 130 | #define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ | |
| 131 | #define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c | |
| 132 | #define PAS_DMA_TXCHAN_CFG_TATTR_S 2 | |
| 133 | #define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ | |
| 134 | PAS_DMA_TXCHAN_CFG_TATTR_M) | |
| 135 | #define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 | |
| 136 | #define PAS_DMA_TXCHAN_CFG_WT_S 6 | |
| 137 | #define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ | |
| 138 | PAS_DMA_TXCHAN_CFG_WT_M) | |
| 139 | #define PAS_DMA_TXCHAN_CFG_TRD 0x00010000 /* translate data */ | |
| 140 | #define PAS_DMA_TXCHAN_CFG_TRR 0x00008000 /* translate rings */ | |
| 141 | #define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ | |
| 142 | #define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ | |
| 143 | #define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ | |
| 144 | #define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) | |
| 145 | #define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) | |
| 146 | #define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 | |
| 147 | #define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 | |
| 148 | #define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ | |
| 149 | PAS_DMA_TXCHAN_BASEL_BRBL_M) | |
| 150 | #define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) | |
| 151 | #define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff | |
| 152 | #define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 | |
| 153 | #define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ | |
| 154 | PAS_DMA_TXCHAN_BASEU_BRBH_M) | |
| 155 | /* # of cache lines worth of buffer ring */ | |
| 156 | #define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 | |
| 157 | #define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ | |
| 158 | #define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ | |
| 159 | PAS_DMA_TXCHAN_BASEU_SIZ_M) | |
| 160 | ||
| 161 | #define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */ | |
| 162 | #define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */ | |
| 163 | #define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */ | |
| 164 | #define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */ | |
| 165 | #define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */ | |
| 166 | #define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */ | |
| 167 | #define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */ | |
| 168 | #define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE) | |
| 169 | #define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */ | |
| 170 | #define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */ | |
| 171 | #define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */ | |
| 172 | #define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000 | |
| 173 | #define PAS_DMA_RXCHAN_CCMDSTA_OD 0x00002000 | |
| 174 | #define PAS_DMA_RXCHAN_CCMDSTA_FD 0x00001000 | |
| 175 | #define PAS_DMA_RXCHAN_CCMDSTA_DT 0x00000800 | |
| 176 | #define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE) | |
| 177 | #define PAS_DMA_RXCHAN_CFG_CTR 0x00000400 | |
| 178 | #define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380 | |
| 179 | #define PAS_DMA_RXCHAN_CFG_HBU_S 7 | |
| 180 | #define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \ | |
| 181 | PAS_DMA_RXCHAN_CFG_HBU_M) | |
| 182 | #define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE) | |
| 183 | #define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE) | |
| 184 | #define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0 | |
| 185 | #define PAS_DMA_RXCHAN_BASEL_BRBL_S 0 | |
| 186 | #define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \ | |
| 187 | PAS_DMA_RXCHAN_BASEL_BRBL_M) | |
| 188 | #define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE) | |
| 189 | #define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff | |
| 190 | #define PAS_DMA_RXCHAN_BASEU_BRBH_S 0 | |
| 191 | #define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \ | |
| 192 | PAS_DMA_RXCHAN_BASEU_BRBH_M) | |
| 193 | /* # of cache lines worth of buffer ring */ | |
| 194 | #define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000 | |
| 195 | #define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ | |
| 196 | #define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \ | |
| 197 | PAS_DMA_RXCHAN_BASEU_SIZ_M) | |
| 198 | ||
| 199 | #define PAS_STATUS_PCNT_M 0x000000000000ffffull | |
| 200 | #define PAS_STATUS_PCNT_S 0 | |
| 201 | #define PAS_STATUS_DCNT_M 0x00000000ffff0000ull | |
| 202 | #define PAS_STATUS_DCNT_S 16 | |
| 203 | #define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull | |
| 204 | #define PAS_STATUS_BPCNT_S 32 | |
| 205 | #define PAS_STATUS_CAUSE_M 0xf000000000000000ull | |
| 206 | #define PAS_STATUS_TIMER 0x1000000000000000ull | |
| 207 | #define PAS_STATUS_ERROR 0x2000000000000000ull | |
| 208 | #define PAS_STATUS_SOFT 0x4000000000000000ull | |
| 209 | #define PAS_STATUS_INT 0x8000000000000000ull | |
| 210 | ||
| 211 | #define PAS_IOB_COM_PKTHDRCNT 0x120 | |
| 212 | #define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M 0x0fff0000 | |
| 213 | #define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S 16 | |
| 214 | #define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M 0x00000fff | |
| 215 | #define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S 0 | |
| 216 | ||
| 217 | #define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) | |
| 218 | #define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff | |
| 219 | #define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 | |
| 220 | #define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ | |
| 221 | PAS_IOB_DMA_RXCH_CFG_CNTTH_M) | |
| 222 | #define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) | |
| 223 | #define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff | |
| 224 | #define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 | |
| 225 | #define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ | |
| 226 | PAS_IOB_DMA_TXCH_CFG_CNTTH_M) | |
| 227 | #define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) | |
| 228 | #define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 | |
| 229 | #define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff | |
| 230 | #define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 | |
| 231 | #define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ | |
| 232 | PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) | |
| 233 | #define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) | |
| 234 | #define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 | |
| 235 | #define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff | |
| 236 | #define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 | |
| 237 | #define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ | |
| 238 | PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) | |
| 239 | #define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) | |
| 240 | #define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 | |
| 241 | #define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 | |
| 242 | #define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ | |
| 243 | PAS_IOB_DMA_RXCH_RESET_PCNT_M) | |
| 244 | #define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 | |
| 245 | #define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 | |
| 246 | #define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 | |
| 247 | #define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 | |
| 248 | #define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 | |
| 249 | #define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 | |
| 250 | #define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) | |
| 251 | #define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 | |
| 252 | #define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 | |
| 253 | #define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ | |
| 254 | PAS_IOB_DMA_TXCH_RESET_PCNT_M) | |
| 255 | #define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 | |
| 256 | #define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 | |
| 257 | #define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 | |
| 258 | #define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 | |
| 259 | #define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 | |
| 260 | #define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 | |
| 261 | ||
| 262 | #define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 | |
| 263 | #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff | |
| 264 | #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 | |
| 265 | #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ | |
| 266 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) | |
| 267 | ||
| 268 | /* Transmit descriptor fields */ | |
| 269 | #define XCT_MACTX_T 0x8000000000000000ull | |
| 270 | #define XCT_MACTX_ST 0x4000000000000000ull | |
| 271 | #define XCT_MACTX_NORES 0x0000000000000000ull | |
| 272 | #define XCT_MACTX_8BRES 0x1000000000000000ull | |
| 273 | #define XCT_MACTX_24BRES 0x2000000000000000ull | |
| 274 | #define XCT_MACTX_40BRES 0x3000000000000000ull | |
| 275 | #define XCT_MACTX_I 0x0800000000000000ull | |
| 276 | #define XCT_MACTX_O 0x0400000000000000ull | |
| 277 | #define XCT_MACTX_E 0x0200000000000000ull | |
| 278 | #define XCT_MACTX_VLAN_M 0x0180000000000000ull | |
| 279 | #define XCT_MACTX_VLAN_NOP 0x0000000000000000ull | |
| 280 | #define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull | |
| 281 | #define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull | |
| 282 | #define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull | |
| 283 | #define XCT_MACTX_CRC_M 0x0060000000000000ull | |
| 284 | #define XCT_MACTX_CRC_NOP 0x0000000000000000ull | |
| 285 | #define XCT_MACTX_CRC_INSERT 0x0020000000000000ull | |
| 286 | #define XCT_MACTX_CRC_PAD 0x0040000000000000ull | |
| 287 | #define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull | |
| 288 | #define XCT_MACTX_SS 0x0010000000000000ull | |
| 289 | #define XCT_MACTX_LLEN_M 0x00007fff00000000ull | |
| 290 | #define XCT_MACTX_LLEN_S 32ull | |
| 291 | #define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ | |
| 292 | XCT_MACTX_LLEN_M) | |
| 293 | #define XCT_MACTX_IPH_M 0x00000000f8000000ull | |
| 294 | #define XCT_MACTX_IPH_S 27ull | |
| 295 | #define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ | |
| 296 | XCT_MACTX_IPH_M) | |
| 297 | #define XCT_MACTX_IPO_M 0x0000000007c00000ull | |
| 298 | #define XCT_MACTX_IPO_S 22ull | |
| 299 | #define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ | |
| 300 | XCT_MACTX_IPO_M) | |
| 301 | #define XCT_MACTX_CSUM_M 0x0000000000000060ull | |
| 302 | #define XCT_MACTX_CSUM_NOP 0x0000000000000000ull | |
| 303 | #define XCT_MACTX_CSUM_TCP 0x0000000000000040ull | |
| 304 | #define XCT_MACTX_CSUM_UDP 0x0000000000000060ull | |
| 305 | #define XCT_MACTX_V6 0x0000000000000010ull | |
| 306 | #define XCT_MACTX_C 0x0000000000000004ull | |
| 307 | #define XCT_MACTX_AL2 0x0000000000000002ull | |
| 308 | ||
| 309 | /* Receive descriptor fields */ | |
| 310 | #define XCT_MACRX_T 0x8000000000000000ull | |
| 311 | #define XCT_MACRX_ST 0x4000000000000000ull | |
| 312 | #define XCT_MACRX_RR_M 0x3000000000000000ull | |
| 313 | #define XCT_MACRX_RR_NORES 0x0000000000000000ull | |
| 314 | #define XCT_MACRX_RR_8BRES 0x1000000000000000ull | |
| 315 | #define XCT_MACRX_O 0x0400000000000000ull | |
| 316 | #define XCT_MACRX_E 0x0200000000000000ull | |
| 317 | #define XCT_MACRX_FF 0x0100000000000000ull | |
| 318 | #define XCT_MACRX_PF 0x0080000000000000ull | |
| 319 | #define XCT_MACRX_OB 0x0040000000000000ull | |
| 320 | #define XCT_MACRX_OD 0x0020000000000000ull | |
| 321 | #define XCT_MACRX_FS 0x0010000000000000ull | |
| 322 | #define XCT_MACRX_NB_M 0x000fc00000000000ull | |
| 323 | #define XCT_MACRX_NB_S 46ULL | |
| 324 | #define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \ | |
| 325 | XCT_MACRX_NB_M) | |
| 326 | #define XCT_MACRX_LLEN_M 0x00003fff00000000ull | |
| 327 | #define XCT_MACRX_LLEN_S 32ULL | |
| 328 | #define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \ | |
| 329 | XCT_MACRX_LLEN_M) | |
| 330 | #define XCT_MACRX_CRC 0x0000000080000000ull | |
| 331 | #define XCT_MACRX_LEN_M 0x0000000060000000ull | |
| 332 | #define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull | |
| 333 | #define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull | |
| 334 | #define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull | |
| 335 | #define XCT_MACRX_CAST_M 0x0000000018000000ull | |
| 336 | #define XCT_MACRX_CAST_UNI 0x0000000000000000ull | |
| 337 | #define XCT_MACRX_CAST_MULTI 0x0000000008000000ull | |
| 338 | #define XCT_MACRX_CAST_BROAD 0x0000000010000000ull | |
| 339 | #define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull | |
| 340 | #define XCT_MACRX_VLC_M 0x0000000006000000ull | |
| 341 | #define XCT_MACRX_FM 0x0000000001000000ull | |
| 342 | #define XCT_MACRX_HTY_M 0x0000000000c00000ull | |
| 343 | #define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull | |
| 344 | #define XCT_MACRX_HTY_IPV6 0x0000000000400000ull | |
| 345 | #define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull | |
| 346 | #define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull | |
| 347 | #define XCT_MACRX_IPP_M 0x00000000003f0000ull | |
| 348 | #define XCT_MACRX_IPP_S 16 | |
| 349 | #define XCT_MACRX_CSUM_M 0x000000000000ffffull | |
| 350 | #define XCT_MACRX_CSUM_S 0 | |
| 351 | ||
| 352 | #define XCT_PTR_T 0x8000000000000000ull | |
| 353 | #define XCT_PTR_LEN_M 0x7ffff00000000000ull | |
| 354 | #define XCT_PTR_LEN_S 44 | |
| 355 | #define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ | |
| 356 | XCT_PTR_LEN_M) | |
| 357 | #define XCT_PTR_ADDR_M 0x00000fffffffffffull | |
| 358 | #define XCT_PTR_ADDR_S 0 | |
| 359 | #define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ | |
| 360 | XCT_PTR_ADDR_M) | |
| 361 | ||
| 362 | /* Receive interface 8byte result fields */ | |
| 363 | #define XCT_RXRES_8B_L4O_M 0xff00000000000000ull | |
| 364 | #define XCT_RXRES_8B_L4O_S 56 | |
| 365 | #define XCT_RXRES_8B_RULE_M 0x00ffff0000000000ull | |
| 366 | #define XCT_RXRES_8B_RULE_S 40 | |
| 367 | #define XCT_RXRES_8B_EVAL_M 0x000000ffff000000ull | |
| 368 | #define XCT_RXRES_8B_EVAL_S 24 | |
| 369 | #define XCT_RXRES_8B_HTYPE_M 0x0000000000f00000ull | |
| 370 | #define XCT_RXRES_8B_HASH_M 0x00000000000fffffull | |
| 371 | #define XCT_RXRES_8B_HASH_S 0 | |
| 372 | ||
| 373 | /* Receive interface buffer fields */ | |
| 374 | #define XCT_RXB_LEN_M 0x0ffff00000000000ull | |
| 375 | #define XCT_RXB_LEN_S 44 | |
| 376 | #define XCT_RXB_LEN(x) ((((long)(x)) << XCT_RXB_LEN_S) & \ | |
| 377 | XCT_RXB_LEN_M) | |
| 378 | #define XCT_RXB_ADDR_M 0x00000fffffffffffull | |
| 379 | #define XCT_RXB_ADDR_S 0 | |
| 380 | #define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_RXB_ADDR_S) & \ | |
| 381 | XCT_RXB_ADDR_M) | |
| 382 | ||
| 383 | /* Copy descriptor fields */ | |
| 384 | #define XCT_COPY_T 0x8000000000000000ull | |
| 385 | #define XCT_COPY_ST 0x4000000000000000ull | |
| 386 | #define XCT_COPY_RR_M 0x3000000000000000ull | |
| 387 | #define XCT_COPY_RR_NORES 0x0000000000000000ull | |
| 388 | #define XCT_COPY_RR_8BRES 0x1000000000000000ull | |
| 389 | #define XCT_COPY_RR_24BRES 0x2000000000000000ull | |
| 390 | #define XCT_COPY_RR_40BRES 0x3000000000000000ull | |
| 391 | #define XCT_COPY_I 0x0800000000000000ull | |
| 392 | #define XCT_COPY_O 0x0400000000000000ull | |
| 393 | #define XCT_COPY_E 0x0200000000000000ull | |
| 394 | #define XCT_COPY_STY_ZERO 0x01c0000000000000ull | |
| 395 | #define XCT_COPY_DTY_PREF 0x0038000000000000ull | |
| 396 | #define XCT_COPY_LLEN_M 0x0007ffff00000000ull | |
| 397 | #define XCT_COPY_LLEN_S 32 | |
| 398 | #define XCT_COPY_LLEN(x) ((((long)(x)) << XCT_COPY_LLEN_S) & \ | |
| 399 | XCT_COPY_LLEN_M) | |
| 400 | #define XCT_COPY_SE 0x0000000000000001ull | |
| 401 | ||
| 402 | /* Control descriptor fields */ | |
| 403 | #define CTRL_CMD_T 0x8000000000000000ull | |
| 404 | #define CTRL_CMD_META_EVT 0x2000000000000000ull | |
| 405 | #define CTRL_CMD_O 0x0400000000000000ull | |
| 406 | #define CTRL_CMD_REG_M 0x000000000000000full | |
| 407 | #define CTRL_CMD_REG_S 0 | |
| 408 | #define CTRL_CMD_REG(x) ((((long)(x)) << CTRL_CMD_REG_S) & \ | |
| 409 | CTRL_CMD_REG_M) | |
| 410 | ||
| 411 | ||
| 8ee9d857 OJ |
412 | |
| 413 | /* Prototypes for the shared DMA functions in the platform code. */ | |
| 414 | ||
| 415 | /* DMA TX Channel type. Right now only limitations used are event types 0/1, | |
| 416 | * for event-triggered DMA transactions. | |
| 417 | */ | |
| 418 | ||
| 419 | enum pasemi_dmachan_type { | |
| 420 | RXCHAN = 0, /* Any RX chan */ | |
| 421 | TXCHAN = 1, /* Any TX chan */ | |
| 422 | TXCHAN_EVT0 = 0x1001, /* TX chan in event class 0 (chan 0-9) */ | |
| 423 | TXCHAN_EVT1 = 0x2001, /* TX chan in event class 1 (chan 10-19) */ | |
| 424 | }; | |
| 425 | ||
| 426 | struct pasemi_dmachan { | |
| 427 | int chno; /* Channel number */ | |
| 428 | enum pasemi_dmachan_type chan_type; /* TX / RX */ | |
| 429 | u64 *status; /* Ptr to cacheable status */ | |
| 430 | int irq; /* IRQ used by channel */ | |
| 431 | unsigned int ring_size; /* size of allocated ring */ | |
| 432 | dma_addr_t ring_dma; /* DMA address for ring */ | |
| 433 | u64 *ring_virt; /* Virt address for ring */ | |
| 434 | void *priv; /* Ptr to start of client struct */ | |
| 435 | }; | |
| 436 | ||
| 437 | /* Read/write the different registers in the I/O Bridge, Ethernet | |
| 438 | * and DMA Controller | |
| 439 | */ | |
| 440 | extern unsigned int pasemi_read_iob_reg(unsigned int reg); | |
| 441 | extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val); | |
| 442 | ||
| 443 | extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg); | |
| 444 | extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val); | |
| 445 | ||
| 446 | extern unsigned int pasemi_read_dma_reg(unsigned int reg); | |
| 447 | extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val); | |
| 448 | ||
| 449 | /* Channel management routines */ | |
| 450 | ||
| 451 | extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type, | |
| 452 | int total_size, int offset); | |
| 453 | extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan); | |
| 454 | ||
| 455 | extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan, | |
| 456 | const u32 cmdsta); | |
| 457 | extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan); | |
| 458 | ||
| 459 | /* Common routines to allocate rings and buffers */ | |
| 460 | ||
| 461 | extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size); | |
| 462 | extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan); | |
| 463 | ||
| 464 | extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size, | |
| 465 | dma_addr_t *handle); | |
| 466 | extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size, | |
| 467 | dma_addr_t *handle); | |
| 468 | ||
| f37203b5 OJ |
469 | /* Routines to allocate flags (events) for channel syncronization */ |
| 470 | extern int pasemi_dma_alloc_flag(void); | |
| 471 | extern void pasemi_dma_free_flag(int flag); | |
| 472 | extern void pasemi_dma_set_flag(int flag); | |
| 473 | extern void pasemi_dma_clear_flag(int flag); | |
| 474 | ||
| dda56df0 OJ |
475 | /* Routines to allocate function engines */ |
| 476 | extern int pasemi_dma_alloc_fun(void); | |
| 477 | extern void pasemi_dma_free_fun(int fun); | |
| 478 | ||
| 8ee9d857 OJ |
479 | /* Initialize the library, must be called before any other functions */ |
| 480 | extern int pasemi_dma_init(void); | |
| 481 | ||
| 40afa531 | 482 | #endif /* ASM_PASEMI_DMA_H */ |