[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-i386 / apic.h

#ifndef __ASM_APIC_H
#define __ASM_APIC_H

#include <linux/config.h>
#include <linux/pm.h>
#include <asm/fixmap.h>
#include <asm/apicdef.h>
#include <asm/processor.h>
#include <asm/system.h>

#define Dprintk(x...)

/*
 * Debugging macros
 */
#define APIC_QUIET   0
#define APIC_VERBOSE 1
#define APIC_DEBUG   2

extern int enable_local_apic;
extern int apic_verbosity;

static inline void lapic_disable(void)
{
	enable_local_apic = -1;
	clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
}

static inline void lapic_enable(void)
{
	enable_local_apic = 1;
}

/*
 * Define the default level of output to be very little
 * This can be turned up by using apic=verbose for more
 * information and apic=debug for _lots_ of information.
 * apic_verbosity is defined in apic.c
 */
#define apic_printk(v, s, a...) do {       \
		if ((v) <= apic_verbosity) \
			printk(s, ##a);    \
	} while (0)


#ifdef CONFIG_X86_LOCAL_APIC

/*
 * Basic functions accessing APICs.
 */

static __inline void apic_write(unsigned long reg, unsigned long v)
{
	*((volatile unsigned long *)(APIC_BASE+reg)) = v;
}

static __inline void apic_write_atomic(unsigned long reg, unsigned long v)
{
	xchg((volatile unsigned long *)(APIC_BASE+reg), v);
}

static __inline unsigned long apic_read(unsigned long reg)
{
	return *((volatile unsigned long *)(APIC_BASE+reg));
}

static __inline__ void apic_wait_icr_idle(void)
{
	while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY )
		cpu_relax();
}

int get_physical_broadcast(void);

#ifdef CONFIG_X86_GOOD_APIC
# define FORCE_READ_AROUND_WRITE 0
# define apic_read_around(x)
# define apic_write_around(x,y) apic_write((x),(y))
#else
# define FORCE_READ_AROUND_WRITE 1
# define apic_read_around(x) apic_read(x)
# define apic_write_around(x,y) apic_write_atomic((x),(y))
#endif

static inline void ack_APIC_irq(void)
{
	/*
	 * ack_APIC_irq() actually gets compiled as a single instruction:
	 * - a single rmw on Pentium/82489DX
	 * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
	 * ... yummie.
	 */

	/* Docs say use 0 for future compatibility */
	apic_write_around(APIC_EOI, 0);
}

extern void (*wait_timer_tick)(void);

extern int get_maxlvt(void);
extern void clear_local_APIC(void);
extern void connect_bsp_APIC (void);
extern void disconnect_bsp_APIC (int virt_wire_setup);
extern void disable_local_APIC (void);
extern void lapic_shutdown (void);
extern int verify_local_APIC (void);
extern void cache_APIC_registers (void);
extern void sync_Arb_IDs (void);
extern void init_bsp_APIC (void);
extern void setup_local_APIC (void);
extern void init_apic_mappings (void);
extern void smp_local_timer_interrupt (struct pt_regs * regs);
extern void setup_boot_APIC_clock (void);
extern void setup_secondary_APIC_clock (void);
extern void setup_apic_nmi_watchdog (void);
extern int reserve_lapic_nmi(void);
extern void release_lapic_nmi(void);
extern void disable_timer_nmi_watchdog(void);
extern void enable_timer_nmi_watchdog(void);
extern void nmi_watchdog_tick (struct pt_regs * regs);
extern int APIC_init_uniprocessor (void);
extern void disable_APIC_timer(void);
extern void enable_APIC_timer(void);

extern void enable_NMI_through_LVT0 (void * dummy);

extern unsigned int nmi_watchdog;
#define NMI_NONE	0
#define NMI_IO_APIC	1
#define NMI_LOCAL_APIC	2
#define NMI_INVALID	3

extern int disable_timer_pin_1;

void smp_send_timer_broadcast_ipi(struct pt_regs *regs);
void switch_APIC_timer_to_ipi(void *cpumask);
void switch_ipi_to_APIC_timer(void *cpumask);
#define ARCH_APICTIMER_STOPS_ON_C3	1

#else /* !CONFIG_X86_LOCAL_APIC */
static inline void lapic_shutdown(void) { }

#endif /* !CONFIG_X86_LOCAL_APIC */

#endif /* __ASM_APIC_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_APIC_H
	2	#define __ASM_APIC_H
	3
	4	#include <linux/config.h>
	5	#include <linux/pm.h>
	6	#include <asm/fixmap.h>
	7	#include <asm/apicdef.h>
9635b47d	8	#include <asm/processor.h>
1da177e4 LT	9	#include <asm/system.h>
	10
	11	#define Dprintk(x...)
	12
	13	/*
	14	* Debugging macros
	15	*/
	16	#define APIC_QUIET 0
	17	#define APIC_VERBOSE 1
	18	#define APIC_DEBUG 2
	19
9635b47d	20	extern int enable_local_apic;
1da177e4 LT	21	extern int apic_verbosity;
1da177e4 LT	22
9635b47d EB	23	static inline void lapic_disable(void)
	24	{
	25	enable_local_apic = -1;
	26	clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
	27	}
	28
	29	static inline void lapic_enable(void)
	30	{
	31	enable_local_apic = 1;
	32	}
	33
1da177e4 LT	34	/*
	35	* Define the default level of output to be very little
	36	* This can be turned up by using apic=verbose for more
	37	* information and apic=debug for _lots_ of information.
	38	* apic_verbosity is defined in apic.c
	39	*/
	40	#define apic_printk(v, s, a...) do { \
	41	if ((v) <= apic_verbosity) \
	42	printk(s, ##a); \
	43	} while (0)
	44
	45
	46	#ifdef CONFIG_X86_LOCAL_APIC
	47
	48	/*
	49	* Basic functions accessing APICs.
	50	*/
	51
	52	static __inline void apic_write(unsigned long reg, unsigned long v)
	53	{
	54	((volatile unsigned long )(APIC_BASE+reg)) = v;
	55	}
	56
	57	static __inline void apic_write_atomic(unsigned long reg, unsigned long v)
	58	{
	59	xchg((volatile unsigned long *)(APIC_BASE+reg), v);
	60	}
	61
	62	static __inline unsigned long apic_read(unsigned long reg)
	63	{
	64	return ((volatile unsigned long )(APIC_BASE+reg));
	65	}
	66
	67	static __inline__ void apic_wait_icr_idle(void)
	68	{
	69	while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY )
	70	cpu_relax();
	71	}
	72
	73	int get_physical_broadcast(void);
	74
	75	#ifdef CONFIG_X86_GOOD_APIC
	76	# define FORCE_READ_AROUND_WRITE 0
	77	# define apic_read_around(x)
	78	# define apic_write_around(x,y) apic_write((x),(y))
	79	#else
	80	# define FORCE_READ_AROUND_WRITE 1
	81	# define apic_read_around(x) apic_read(x)
	82	# define apic_write_around(x,y) apic_write_atomic((x),(y))
	83	#endif
	84
	85	static inline void ack_APIC_irq(void)
	86	{
	87	/*
	88	* ack_APIC_irq() actually gets compiled as a single instruction:
	89	* - a single rmw on Pentium/82489DX
	90	* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
	91	* ... yummie.
	92	*/
	93
	94	/* Docs say use 0 for future compatibility */
	95	apic_write_around(APIC_EOI, 0);
	96	}
	97
98	extern void (*wait_timer_tick)(void);
99
100	extern int get_maxlvt(void);
101	extern void clear_local_APIC(void);
102	extern void connect_bsp_APIC (void);
650927ef	103	extern void disconnect_bsp_APIC (int virt_wire_setup);
1da177e4 LT	104	extern void disable_local_APIC (void);
	105	extern void lapic_shutdown (void);
	106	extern int verify_local_APIC (void);
	107	extern void cache_APIC_registers (void);
	108	extern void sync_Arb_IDs (void);
	109	extern void init_bsp_APIC (void);
	110	extern void setup_local_APIC (void);
	111	extern void init_apic_mappings (void);
	112	extern void smp_local_timer_interrupt (struct pt_regs * regs);
	113	extern void setup_boot_APIC_clock (void);
	114	extern void setup_secondary_APIC_clock (void);
	115	extern void setup_apic_nmi_watchdog (void);
	116	extern int reserve_lapic_nmi(void);
	117	extern void release_lapic_nmi(void);
	118	extern void disable_timer_nmi_watchdog(void);
	119	extern void enable_timer_nmi_watchdog(void);
	120	extern void nmi_watchdog_tick (struct pt_regs * regs);
	121	extern int APIC_init_uniprocessor (void);
	122	extern void disable_APIC_timer(void);
	123	extern void enable_APIC_timer(void);
	124
1da177e4 LT	125	extern void enable_NMI_through_LVT0 (void * dummy);
	126
	127	extern unsigned int nmi_watchdog;
	128	#define NMI_NONE 0
	129	#define NMI_IO_APIC 1
	130	#define NMI_LOCAL_APIC 2
	131	#define NMI_INVALID 3
	132
66759a01 CE	133	extern int disable_timer_pin_1;
66759a01 CE	134
6eb0a0fd VP	135	void smp_send_timer_broadcast_ipi(struct pt_regs *regs);
	136	void switch_APIC_timer_to_ipi(void *cpumask);
	137	void switch_ipi_to_APIC_timer(void *cpumask);
	138	#define ARCH_APICTIMER_STOPS_ON_C3 1
	139
1da177e4 LT	140	#else /* !CONFIG_X86_LOCAL_APIC */
	141	static inline void lapic_shutdown(void) { }
	142
	143	#endif /* !CONFIG_X86_LOCAL_APIC */
	144
	145	#endif /* __ASM_APIC_H */