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1da177e4 LT |
1 | #ifndef __ETHER00_H |
2 | #define __ETHER00_H | |
3 | ||
4 | ||
5 | ||
6 | /* | |
7 | * Register definitions for the Ethernet MAC | |
8 | */ | |
9 | ||
10 | /* | |
11 | * Copyright (c) Altera Corporation 2000. | |
12 | * All rights reserved. | |
13 | */ | |
14 | ||
15 | /* | |
16 | * Structures for the DMA controller | |
17 | */ | |
18 | typedef struct fda_desc | |
19 | { | |
20 | struct fda_desc * FDNext; | |
21 | long FDSystem; | |
22 | long FDStat; | |
23 | short FDLength; | |
24 | short FDCtl; | |
25 | }FDA_DESC; | |
26 | ||
27 | typedef struct buf_desc | |
28 | { | |
29 | char * BuffData; | |
30 | short BuffLength; | |
31 | char BDStat; | |
32 | char BDCtl; | |
33 | }BUF_DESC; | |
34 | ||
35 | /* | |
36 | * Control masks for the DMA controller | |
37 | */ | |
38 | #define FDCTL_BDCOUNT_MSK (0x1F) | |
39 | #define FDCTL_BDCOUNT_OFST (0) | |
40 | #define FDCTL_FRMOPT_MSK (0x7C00) | |
41 | #define FDCTL_FRMOPT_OFST (10) | |
42 | #define FDCTL_COWNSFD_MSK (0x8000) | |
43 | #define FDCTL_COWNSFD_OFST (15) | |
44 | ||
45 | #define BDCTL_RXBDSEQN_MSK (0x7F) | |
46 | #define BDCTL_RXBDSEQN_OFST (0) | |
47 | #define BDCTL_COWNSBD_MSK (0x80) | |
48 | #define BDCTL_COWNSBD_OFST (7) | |
49 | ||
50 | #define FDNEXT_EOL_MSK (0x1) | |
51 | #define FDNEXT_EOL_OFST (0) | |
52 | #define FDNEXT_EOL_POINTER_MSK (0xFFFFFFF0) | |
53 | #define FDNEXT_EOL_POINTER_OFST (4) | |
54 | ||
55 | #define ETHER_ARC_SIZE (21) | |
56 | ||
57 | /* | |
58 | * Register definitions and masks | |
59 | */ | |
60 | #define ETHER_DMA_CTL(base) (ETHER00_TYPE (base + 0x100)) | |
61 | #define ETHER_DMA_CTL_DMBURST_OFST (2) | |
62 | #define ETHER_DMA_CTL_DMBURST_MSK (0x1FC) | |
63 | #define ETHER_DMA_CTL_POWRMGMNT_OFST (11) | |
64 | #define ETHER_DMA_CTL_POWRMGMNT_MSK (0x1000) | |
65 | #define ETHER_DMA_CTL_TXBIGE_OFST (14) | |
66 | #define ETHER_DMA_CTL_TXBIGE_MSK (0x4000) | |
67 | #define ETHER_DMA_CTL_RXBIGE_OFST (15) | |
68 | #define ETHER_DMA_CTL_RXBIGE_MSK (0x8000) | |
69 | #define ETHER_DMA_CTL_TXWAKEUP_OFST (16) | |
70 | #define ETHER_DMA_CTL_TXWAKEUP_MSK (0x10000) | |
71 | #define ETHER_DMA_CTL_SWINTREQ_OFST (17) | |
72 | #define ETHER_DMA_CTL_SWINTREQ_MSK (0x20000) | |
73 | #define ETHER_DMA_CTL_INTMASK_OFST (18) | |
74 | #define ETHER_DMA_CTL_INTMASK_MSK (0x40000) | |
75 | #define ETHER_DMA_CTL_M66ENSTAT_OFST (19) | |
76 | #define ETHER_DMA_CTL_M66ENSTAT_MSK (0x80000) | |
77 | #define ETHER_DMA_CTL_RMTXINIT_OFST (20) | |
78 | #define ETHER_DMA_CTL_RMTXINIT_MSK (0x100000) | |
79 | #define ETHER_DMA_CTL_RMRXINIT_OFST (21) | |
80 | #define ETHER_DMA_CTL_RMRXINIT_MSK (0x200000) | |
81 | #define ETHER_DMA_CTL_RXALIGN_OFST (22) | |
82 | #define ETHER_DMA_CTL_RXALIGN_MSK (0xC00000) | |
83 | #define ETHER_DMA_CTL_RMSWRQ_OFST (24) | |
84 | #define ETHER_DMA_CTL_RMSWRQ_MSK (0x1000000) | |
85 | #define ETHER_DMA_CTL_RMEMBANK_OFST (25) | |
86 | #define ETHER_DMA_CTL_RMEMBANK_MSK (0x2000000) | |
87 | ||
88 | #define ETHER_TXFRMPTR(base) (ETHER00_TYPE (base + 0x104)) | |
89 | ||
90 | #define ETHER_TXTHRSH(base) (ETHER00_TYPE (base + 0x308)) | |
91 | ||
92 | #define ETHER_TXPOLLCTR(base) (ETHER00_TYPE (base + 0x30c)) | |
93 | ||
94 | #define ETHER_BLFRMPTR(base) (ETHER00_TYPE (base + 0x110)) | |
95 | #define ETHER_BLFFRMPTR_EOL_OFST (0) | |
96 | #define ETHER_BLFFRMPTR_EOL_MSK (0x1) | |
97 | #define ETHER_BLFFRMPTR_ADDRESS_OFST (4) | |
98 | #define ETHER_BLFFRMPTR_ADDRESS_MSK (0xFFFFFFF0) | |
99 | ||
100 | #define ETHER_RXFRAGSIZE(base) (ETHER00_TYPE (base + 0x114)) | |
101 | #define ETHER_RXFRAGSIZE_MINFRAG_OFST (2) | |
102 | #define ETHER_RXFRAGSIZE_MINFRAG_MSK (0xFFC) | |
103 | #define ETHER_RXFRAGSIZE_ENPACK_OFST (15) | |
104 | #define ETHER_RXFRAGSIZE_ENPACK_MSK (0x8000) | |
105 | ||
106 | #define ETHER_INT_EN(base) (ETHER00_TYPE (base + 0x118)) | |
107 | #define ETHER_INT_EN_FDAEXEN_OFST (0) | |
108 | #define ETHER_INT_EN_FDAEXEN_MSK (0x1) | |
109 | #define ETHER_INT_EN_BLEXEN_OFST (1) | |
110 | #define ETHER_INT_EN_BLEXN_MSK (0x2) | |
111 | #define ETHER_INT_EN_STARGABTEN_OFST (2) | |
112 | #define ETHER_INT_EN_STARGABTEN_MSK (0x4) | |
113 | #define ETHER_INT_EN_RTARGABTEN_OFST (3) | |
114 | #define ETHER_INT_EN_RTARGABTEN_MSK (0x8) | |
115 | #define ETHER_INT_EN_RMASABTEN_OFST (4) | |
116 | #define ETHER_INT_EN_RMASABTEN_MSK (0x10) | |
117 | #define ETHER_INT_EN_SSYSERREN_OFST (5) | |
118 | #define ETHER_INT_EN_SSYSERREN_MSK (0x20) | |
119 | #define ETHER_INT_EN_DPARERREN_OFST (6) | |
120 | #define ETHER_INT_EN_DPARERREN_MSK (0x40) | |
121 | #define ETHER_INT_EN_EARNOTEN_OFST (7) | |
122 | #define ETHER_INT_EN_EARNOTEN_MSK (0x80) | |
123 | #define ETHER_INT_EN_DPARDEN_OFST (8) | |
124 | #define ETHER_INT_EN_DPARDEN_MSK (0x100) | |
125 | #define ETHER_INT_EN_DMPARERREN_OFST (9) | |
126 | #define ETHER_INT_EN_DMPARERREN_MSK (0x200) | |
127 | #define ETHER_INT_EN_TXCTLCMPEN_OFST (10) | |
128 | #define ETHER_INT_EN_TXCTLCMPEN_MSK (0x400) | |
129 | #define ETHER_INT_EN_NRABTEN_OFST (11) | |
130 | #define ETHER_INT_EN_NRABTEN_MSK (0x800) | |
131 | ||
132 | #define ETHER_FDA_BAS(base) (ETHER00_TYPE (base + 0x11C)) | |
133 | #define ETHER_FDA_BAS_ADDRESS_OFST (4) | |
134 | #define ETHER_FDA_BAS_ADDRESS_MSK (0xFFFFFFF0) | |
135 | ||
136 | #define ETHER_FDA_LIM(base) (ETHER00_TYPE (base + 0x120)) | |
137 | #define ETHER_FDA_LIM_COUNT_OFST (4) | |
138 | #define ETHER_FDA_LIM_COUNT_MSK (0xFFF0) | |
139 | ||
140 | #define ETHER_INT_SRC(base) (ETHER00_TYPE (base + 0x124)) | |
141 | #define ETHER_INT_SRC_INTMACTX_OFST (0) | |
142 | #define ETHER_INT_SRC_INTMACTX_MSK (0x1) | |
143 | #define ETHER_INT_SRC_INTMACRX_OFST (1) | |
144 | #define ETHER_INT_SRC_INTMACRX_MSK (0x2) | |
145 | #define ETHER_INT_SRC_INTSBUS_OFST (2) | |
146 | #define ETHER_INT_SRC_INTSBUS_MSK (0x4) | |
147 | #define ETHER_INT_SRC_INTFDAEX_OFST (3) | |
148 | #define ETHER_INT_SRC_INTFDAEX_MSK (0x8) | |
149 | #define ETHER_INT_SRC_INTBLEX_OFST (4) | |
150 | #define ETHER_INT_SRC_INTBLEX_MSK (0x10) | |
151 | #define ETHER_INT_SRC_SWINT_OFST (5) | |
152 | #define ETHER_INT_SRC_SWINT_MSK (0x20) | |
153 | #define ETHER_INT_SRC_INTEARNOT_OFST (6) | |
154 | #define ETHER_INT_SRC_INTEARNOT_MSK (0x40) | |
155 | #define ETHER_INT_SRC_DMPARERR_OFST (7) | |
156 | #define ETHER_INT_SRC_DMPARERR_MSK (0x80) | |
157 | #define ETHER_INT_SRC_INTEXBD_OFST (8) | |
158 | #define ETHER_INT_SRC_INTEXBD_MSK (0x100) | |
159 | #define ETHER_INT_SRC_INTTXCTLCMP_OFST (9) | |
160 | #define ETHER_INT_SRC_INTTXCTLCMP_MSK (0x200) | |
161 | #define ETHER_INT_SRC_INTNRABT_OFST (10) | |
162 | #define ETHER_INT_SRC_INTNRABT_MSK (0x400) | |
163 | #define ETHER_INT_SRC_FDAEX_OFST (11) | |
164 | #define ETHER_INT_SRC_FDAEX_MSK (0x800) | |
165 | #define ETHER_INT_SRC_BLEX_OFST (12) | |
166 | #define ETHER_INT_SRC_BLEX_MSK (0x1000) | |
167 | #define ETHER_INT_SRC_DMPARERRSTAT_OFST (13) | |
168 | #define ETHER_INT_SRC_DMPARERRSTAT_MSK (0x2000) | |
169 | #define ETHER_INT_SRC_NRABT_OFST (14) | |
170 | #define ETHER_INT_SRC_NRABT_MSK (0x4000) | |
171 | #define ETHER_INT_SRC_INTLINK_OFST (15) | |
172 | #define ETHER_INT_SRC_INTLINK_MSK (0x8000) | |
173 | #define ETHER_INT_SRC_INTEXDEFER_OFST (16) | |
174 | #define ETHER_INT_SRC_INTEXDEFER_MSK (0x10000) | |
175 | #define ETHER_INT_SRC_INTRMON_OFST (17) | |
176 | #define ETHER_INT_SRC_INTRMON_MSK (0x20000) | |
177 | #define ETHER_INT_SRC_IRQ_MSK (0x83FF) | |
178 | ||
179 | #define ETHER_PAUSECNT(base) (ETHER00_TYPE (base + 0x40)) | |
180 | #define ETHER_PAUSECNT_COUNT_OFST (0) | |
181 | #define ETHER_PAUSECNT_COUNT_MSK (0xFFFF) | |
182 | ||
183 | #define ETHER_REMPAUCNT(base) (ETHER00_TYPE (base + 0x44)) | |
184 | #define ETHER_REMPAUCNT_COUNT_OFST (0) | |
185 | #define ETHER_REMPAUCNT_COUNT_MSK (0xFFFF) | |
186 | ||
187 | #define ETHER_TXCONFRMSTAT(base) (ETHER00_TYPE (base + 0x348)) | |
188 | #define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST (0) | |
189 | #define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK (0x3FFFFF) | |
190 | ||
191 | #define ETHER_MAC_CTL(base) (ETHER00_TYPE (base + 0)) | |
192 | #define ETHER_MAC_CTL_HALTREQ_OFST (0) | |
193 | #define ETHER_MAC_CTL_HALTREQ_MSK (0x1) | |
194 | #define ETHER_MAC_CTL_HALTIMM_OFST (1) | |
195 | #define ETHER_MAC_CTL_HALTIMM_MSK (0x2) | |
196 | #define ETHER_MAC_CTL_RESET_OFST (2) | |
197 | #define ETHER_MAC_CTL_RESET_MSK (0x4) | |
198 | #define ETHER_MAC_CTL_FULLDUP_OFST (3) | |
199 | #define ETHER_MAC_CTL_FULLDUP_MSK (0x8) | |
200 | #define ETHER_MAC_CTL_MACLOOP_OFST (4) | |
201 | #define ETHER_MAC_CTL_MACLOOP_MSK (0x10) | |
202 | #define ETHER_MAC_CTL_CONN_OFST (5) | |
203 | #define ETHER_MAC_CTL_CONN_MSK (0x60) | |
204 | #define ETHER_MAC_CTL_LOOP10_OFST (7) | |
205 | #define ETHER_MAC_CTL_LOOP10_MSK (0x80) | |
206 | #define ETHER_MAC_CTL_LNKCHG_OFST (8) | |
207 | #define ETHER_MAC_CTL_LNKCHG_MSK (0x100) | |
208 | #define ETHER_MAC_CTL_MISSROLL_OFST (10) | |
209 | #define ETHER_MAC_CTL_MISSROLL_MSK (0x400) | |
210 | #define ETHER_MAC_CTL_ENMISSROLL_OFST (13) | |
211 | #define ETHER_MAC_CTL_ENMISSROLL_MSK (0x2000) | |
212 | #define ETHER_MAC_CTL_LINK10_OFST (15) | |
213 | #define ETHER_MAC_CTL_LINK10_MSK (0x8000) | |
214 | ||
215 | #define ETHER_ARC_CTL(base) (ETHER00_TYPE (base + 0x4)) | |
216 | #define ETHER_ARC_CTL_STATIONACC_OFST (0) | |
217 | #define ETHER_ARC_CTL_STATIONACC_MSK (0x1) | |
218 | #define ETHER_ARC_CTL_GROUPACC_OFST (1) | |
219 | #define ETHER_ARC_CTL_GROUPACC_MSK (0x2) | |
220 | #define ETHER_ARC_CTL_BROADACC_OFST (2) | |
221 | #define ETHER_ARC_CTL_BROADACC_MSK (0x4) | |
222 | #define ETHER_ARC_CTL_NEGARC_OFST (3) | |
223 | #define ETHER_ARC_CTL_NEGARC_MSK (0x8) | |
224 | #define ETHER_ARC_CTL_COMPEN_OFST (4) | |
225 | #define ETHER_ARC_CTL_COMPEN_MSK (0x10) | |
226 | ||
227 | #define ETHER_TX_CTL(base) (ETHER00_TYPE (base + 0x8)) | |
228 | #define ETHER_TX_CTL_TXEN_OFST (0) | |
229 | #define ETHER_TX_CTL_TXEN_MSK (0x1) | |
230 | #define ETHER_TX_CTL_TXHALT_OFST (1) | |
231 | #define ETHER_TX_CTL_TXHALT_MSK (0x2) | |
232 | #define ETHER_TX_CTL_NOPAD_OFST (2) | |
233 | #define ETHER_TX_CTL_NOPAD_MSK (0x4) | |
234 | #define ETHER_TX_CTL_NOCRC_OFST (3) | |
235 | #define ETHER_TX_CTL_NOCRC_MSK (0x8) | |
236 | #define ETHER_TX_CTL_FBACK_OFST (4) | |
237 | #define ETHER_TX_CTL_FBACK_MSK (0x10) | |
238 | #define ETHER_TX_CTL_NOEXDEF_OFST (5) | |
239 | #define ETHER_TX_CTL_NOEXDEF_MSK (0x20) | |
240 | #define ETHER_TX_CTL_SDPAUSE_OFST (6) | |
241 | #define ETHER_TX_CTL_SDPAUSE_MSK (0x40) | |
242 | #define ETHER_TX_CTL_MII10_OFST (7) | |
243 | #define ETHER_TX_CTL_MII10_MSK (0x80) | |
244 | #define ETHER_TX_CTL_ENUNDER_OFST (8) | |
245 | #define ETHER_TX_CTL_ENUNDER_MSK (0x100) | |
246 | #define ETHER_TX_CTL_ENEXDEFER_OFST (9) | |
247 | #define ETHER_TX_CTL_ENEXDEFER_MSK (0x200) | |
248 | #define ETHER_TX_CTL_ENLCARR_OFST (10) | |
249 | #define ETHER_TX_CTL_ENLCARR_MSK (0x400) | |
250 | #define ETHER_TX_CTL_ENEXCOLL_OFST (11) | |
251 | #define ETHER_TX_CTL_ENEXCOLL_MSK (0x800) | |
252 | #define ETHER_TX_CTL_ENLATECOLL_OFST (12) | |
253 | #define ETHER_TX_CTL_ENLATECOLL_MSK (0x1000) | |
254 | #define ETHER_TX_CTL_ENTXPAR_OFST (13) | |
255 | #define ETHER_TX_CTL_ENTXPAR_MSK (0x2000) | |
256 | #define ETHER_TX_CTL_ENCOMP_OFST (14) | |
257 | #define ETHER_TX_CTL_ENCOMP_MSK (0x4000) | |
258 | ||
259 | #define ETHER_TX_STAT(base) (ETHER00_TYPE (base + 0xc)) | |
260 | #define ETHER_TX_STAT_TXCOLL_OFST (0) | |
261 | #define ETHER_TX_STAT_TXCOLL_MSK (0xF) | |
262 | #define ETHER_TX_STAT_EXCOLL_OFST (4) | |
263 | #define ETHER_TX_STAT_EXCOLL_MSK (0x10) | |
264 | #define ETHER_TX_STAT_TXDEFER_OFST (5) | |
265 | #define ETHER_TX_STAT_TXDEFER_MSK (0x20) | |
266 | #define ETHER_TX_STAT_PAUSED_OFST (6) | |
267 | #define ETHER_TX_STAT_PAUSED_MSK (0x40) | |
268 | #define ETHER_TX_STAT_INTTX_OFST (7) | |
269 | #define ETHER_TX_STAT_INTTX_MSK (0x80) | |
270 | #define ETHER_TX_STAT_UNDER_OFST (8) | |
271 | #define ETHER_TX_STAT_UNDER_MSK (0x100) | |
272 | #define ETHER_TX_STAT_EXDEFER_OFST (9) | |
273 | #define ETHER_TX_STAT_EXDEFER_MSK (0x200) | |
274 | #define ETHER_TX_STAT_LCARR_OFST (10) | |
275 | #define ETHER_TX_STAT_LCARR_MSK (0x400) | |
276 | #define ETHER_TX_STAT_TX10STAT_OFST (11) | |
277 | #define ETHER_TX_STAT_TX10STAT_MSK (0x800) | |
278 | #define ETHER_TX_STAT_LATECOLL_OFST (12) | |
279 | #define ETHER_TX_STAT_LATECOLL_MSK (0x1000) | |
280 | #define ETHER_TX_STAT_TXPAR_OFST (13) | |
281 | #define ETHER_TX_STAT_TXPAR_MSK (0x2000) | |
282 | #define ETHER_TX_STAT_COMP_OFST (14) | |
283 | #define ETHER_TX_STAT_COMP_MSK (0x4000) | |
284 | #define ETHER_TX_STAT_TXHALTED_OFST (15) | |
285 | #define ETHER_TX_STAT_TXHALTED_MSK (0x8000) | |
286 | #define ETHER_TX_STAT_SQERR_OFST (16) | |
287 | #define ETHER_TX_STAT_SQERR_MSK (0x10000) | |
288 | #define ETHER_TX_STAT_TXMCAST_OFST (17) | |
289 | #define ETHER_TX_STAT_TXMCAST_MSK (0x20000) | |
290 | #define ETHER_TX_STAT_TXBCAST_OFST (18) | |
291 | #define ETHER_TX_STAT_TXBCAST_MSK (0x40000) | |
292 | #define ETHER_TX_STAT_VLAN_OFST (19) | |
293 | #define ETHER_TX_STAT_VLAN_MSK (0x80000) | |
294 | #define ETHER_TX_STAT_MACC_OFST (20) | |
295 | #define ETHER_TX_STAT_MACC_MSK (0x100000) | |
296 | #define ETHER_TX_STAT_TXPAUSE_OFST (21) | |
297 | #define ETHER_TX_STAT_TXPAUSE_MSK (0x200000) | |
298 | ||
299 | #define ETHER_RX_CTL(base) (ETHER00_TYPE (base + 0x10)) | |
300 | #define ETHER_RX_CTL_RXEN_OFST (0) | |
301 | #define ETHER_RX_CTL_RXEN_MSK (0x1) | |
302 | #define ETHER_RX_CTL_RXHALT_OFST (1) | |
303 | #define ETHER_RX_CTL_RXHALT_MSK (0x2) | |
304 | #define ETHER_RX_CTL_LONGEN_OFST (2) | |
305 | #define ETHER_RX_CTL_LONGEN_MSK (0x4) | |
306 | #define ETHER_RX_CTL_SHORTEN_OFST (3) | |
307 | #define ETHER_RX_CTL_SHORTEN_MSK (0x8) | |
308 | #define ETHER_RX_CTL_STRIPCRC_OFST (4) | |
309 | #define ETHER_RX_CTL_STRIPCRC_MSK (0x10) | |
310 | #define ETHER_RX_CTL_PASSCTL_OFST (5) | |
311 | #define ETHER_RX_CTL_PASSCTL_MSK (0x20) | |
312 | #define ETHER_RX_CTL_IGNORECRC_OFST (6) | |
313 | #define ETHER_RX_CTL_IGNORECRC_MSK (0x40) | |
314 | #define ETHER_RX_CTL_ENALIGN_OFST (8) | |
315 | #define ETHER_RX_CTL_ENALIGN_MSK (0x100) | |
316 | #define ETHER_RX_CTL_ENCRCERR_OFST (9) | |
317 | #define ETHER_RX_CTL_ENCRCERR_MSK (0x200) | |
318 | #define ETHER_RX_CTL_ENOVER_OFST (10) | |
319 | #define ETHER_RX_CTL_ENOVER_MSK (0x400) | |
320 | #define ETHER_RX_CTL_ENLONGERR_OFST (11) | |
321 | #define ETHER_RX_CTL_ENLONGERR_MSK (0x800) | |
322 | #define ETHER_RX_CTL_ENRXPAR_OFST (13) | |
323 | #define ETHER_RX_CTL_ENRXPAR_MSK (0x2000) | |
324 | #define ETHER_RX_CTL_ENGOOD_OFST (14) | |
325 | #define ETHER_RX_CTL_ENGOOD_MSK (0x4000) | |
326 | ||
327 | #define ETHER_RX_STAT(base) (ETHER00_TYPE (base + 0x14)) | |
328 | #define ETHER_RX_STAT_LENERR_OFST (4) | |
329 | #define ETHER_RX_STAT_LENERR_MSK (0x10) | |
330 | #define ETHER_RX_STAT_CTLRECD_OFST (5) | |
331 | #define ETHER_RX_STAT_CTLRECD_MSK (0x20) | |
332 | #define ETHER_RX_STAT_INTRX_OFST (6) | |
333 | #define ETHER_RX_STAT_INTRX_MSK (0x40) | |
334 | #define ETHER_RX_STAT_RX10STAT_OFST (7) | |
335 | #define ETHER_RX_STAT_RX10STAT_MSK (0x80) | |
336 | #define ETHER_RX_STAT_ALIGNERR_OFST (8) | |
337 | #define ETHER_RX_STAT_ALIGNERR_MSK (0x100) | |
338 | #define ETHER_RX_STAT_CRCERR_OFST (9) | |
339 | #define ETHER_RX_STAT_CRCERR_MSK (0x200) | |
340 | #define ETHER_RX_STAT_OVERFLOW_OFST (10) | |
341 | #define ETHER_RX_STAT_OVERFLOW_MSK (0x400) | |
342 | #define ETHER_RX_STAT_LONGERR_OFST (11) | |
343 | #define ETHER_RX_STAT_LONGERR_MSK (0x800) | |
344 | #define ETHER_RX_STAT_RXPAR_OFST (13) | |
345 | #define ETHER_RX_STAT_RXPAR_MSK (0x2000) | |
346 | #define ETHER_RX_STAT_GOOD_OFST (14) | |
347 | #define ETHER_RX_STAT_GOOD_MSK (0x4000) | |
348 | #define ETHER_RX_STAT_RXHALTED_OFST (15) | |
349 | #define ETHER_RX_STAT_RXHALTED_MSK (0x8000) | |
350 | #define ETHER_RX_STAT_RXMCAST_OFST (17) | |
351 | #define ETHER_RX_STAT_RXMCAST_MSK (0x10000) | |
352 | #define ETHER_RX_STAT_RXBCAST_OFST (18) | |
353 | #define ETHER_RX_STAT_RXBCAST_MSK (0x20000) | |
354 | #define ETHER_RX_STAT_RXVLAN_OFST (19) | |
355 | #define ETHER_RX_STAT_RXVLAN_MSK (0x40000) | |
356 | #define ETHER_RX_STAT_RXPAUSE_OFST (20) | |
357 | #define ETHER_RX_STAT_RXPAUSE_MSK (0x80000) | |
358 | #define ETHER_RX_STAT_ARCSTATUS_OFST (21) | |
359 | #define ETHER_RX_STAT_ARCSTATUS_MSK (0xF00000) | |
360 | #define ETHER_RX_STAT_ARCENT_OFST (25) | |
361 | #define ETHER_RX_STAT_ARCENT_MSK (0x1F000000) | |
362 | ||
363 | #define ETHER_MD_DATA(base) (ETHER00_TYPE (base + 0x18)) | |
364 | ||
365 | #define ETHER_MD_CA(base) (ETHER00_TYPE (base + 0x1c)) | |
366 | #define ETHER_MD_CA_ADDR_OFST (0) | |
367 | #define ETHER_MD_CA_ADDR_MSK (0x1F) | |
368 | #define ETHER_MD_CA_PHY_OFST (5) | |
369 | #define ETHER_MD_CA_PHY_MSK (0x3E0) | |
370 | #define ETHER_MD_CA_WR_OFST (10) | |
371 | #define ETHER_MD_CA_WR_MSK (0x400) | |
372 | #define ETHER_MD_CA_BUSY_OFST (11) | |
373 | #define ETHER_MD_CA_BUSY_MSK (0x800) | |
374 | #define ETHER_MD_CA_PRESUPP_OFST (12) | |
375 | #define ETHER_MD_CA_PRESUPP_MSK (0x1000) | |
376 | ||
377 | #define ETHER_ARC_ADR(base) (ETHER00_TYPE (base + 0x160)) | |
378 | #define ETHER_ARC_ADR_ARC_LOC_OFST (2) | |
379 | #define ETHER_ARC_ADR_ARC_LOC_MSK (0xFFC) | |
380 | ||
381 | #define ETHER_ARC_DATA(base) (ETHER00_TYPE (base + 0x364)) | |
382 | ||
383 | #define ETHER_ARC_ENA(base) (ETHER00_TYPE (base + 0x28)) | |
384 | #define ETHER_ARC_ENA_MSK (0x1FFFFF) | |
385 | ||
386 | #define ETHER_PROM_CTL(base) (ETHER00_TYPE (base + 0x2c)) | |
387 | #define ETHER_PROM_CTL_PROM_ADDR_OFST (0) | |
388 | #define ETHER_PROM_CTL_PROM_ADDR_MSK (0x3F) | |
389 | #define ETHER_PROM_CTL_OPCODE_OFST (13) | |
390 | #define ETHER_PROM_CTL_OPCODE_MSK (0x6000) | |
391 | #define ETHER_PROM_CTL_OPCODE_READ_MSK (0x4000) | |
392 | #define ETHER_PROM_CTL_OPCODE_WRITE_MSK (0x2000) | |
393 | #define ETHER_PROM_CTL_OPCODE_ERASE_MSK (0x6000) | |
394 | #define ETHER_PROM_CTL_ENABLE_MSK (0x0030) | |
395 | #define ETHER_PROM_CTL_DISABLE_MSK (0x0000) | |
396 | #define ETHER_PROM_CTL_BUSY_OFST (15) | |
397 | #define ETHER_PROM_CTL_BUSY_MSK (0x8000) | |
398 | ||
399 | #define ETHER_PROM_DATA(base) (ETHER00_TYPE (base + 0x30)) | |
400 | ||
401 | #define ETHER_MISS_CNT(base) (ETHER00_TYPE (base + 0x3c)) | |
402 | #define ETHER_MISS_CNT_COUNT_OFST (0) | |
403 | #define ETHER_MISS_CNT_COUNT_MSK (0xFFFF) | |
404 | ||
405 | #define ETHER_CNTDATA(base) (ETHER00_TYPE (base + 0x80)) | |
406 | ||
407 | #define ETHER_CNTACC(base) (ETHER00_TYPE (base + 0x84)) | |
408 | #define ETHER_CNTACC_ADDR_OFST (0) | |
409 | #define ETHER_CNTACC_ADDR_MSK (0xFF) | |
410 | #define ETHER_CNTACC_WRRDN_OFST (8) | |
411 | #define ETHER_CNTACC_WRRDN_MSK (0x100) | |
412 | #define ETHER_CNTACC_CLEAR_OFST (9) | |
413 | #define ETHER_CNTACC_CLEAR_MSK (0x200) | |
414 | ||
415 | #define ETHER_TXRMINTEN(base) (ETHER00_TYPE (base + 0x88)) | |
416 | #define ETHER_TXRMINTEN_MSK (0x3FFFFFFF) | |
417 | ||
418 | #define ETHER_RXRMINTEN(base) (ETHER00_TYPE (base + 0x8C)) | |
419 | #define ETHER_RXRMINTEN_MSK (0xFFFFFF) | |
420 | ||
421 | /* | |
422 | * RMON Registers | |
423 | */ | |
424 | #define RMON_COLLISION0 0x0 | |
425 | #define RMON_COLLISION1 0x1 | |
426 | #define RMON_COLLISION2 0x2 | |
427 | #define RMON_COLLISION3 0x3 | |
428 | #define RMON_COLLISION4 0x4 | |
429 | #define RMON_COLLISION5 0x5 | |
430 | #define RMON_COLLISION6 0x6 | |
431 | #define RMON_COLLISION7 0x7 | |
432 | #define RMON_COLLISION8 0x8 | |
433 | #define RMON_COLLISION9 0x9 | |
434 | #define RMON_COLLISION10 0xa | |
435 | #define RMON_COLLISION11 0xb | |
436 | #define RMON_COLLISION12 0xc | |
437 | #define RMON_COLLISION13 0xd | |
438 | #define RMON_COLLISION14 0xe | |
439 | #define RMON_COLLISION15 0xf | |
440 | #define RMON_COLLISION16 0x10 | |
441 | #define RMON_FRAMES_WITH_DEFERRED_XMISSIONS 0x11 | |
442 | #define RMON_LATE_COLLISIONS 0x12 | |
443 | #define RMON_FRAMES_LOST_DUE_TO_MAC_XMIT 0x13 | |
444 | #define RMON_CARRIER_SENSE_ERRORS 0x14 | |
445 | #define RMON_FRAMES_WITH_EXCESSIVE_DEFERAL 0x15 | |
446 | #define RMON_UNICAST_FRAMES_TRANSMITTED_OK 0x16 | |
447 | #define RMON_MULTICAST_FRAMES_XMITTED_OK 0x17 | |
448 | #define RMON_BROADCAST_FRAMES_XMITTED_OK 0x18 | |
449 | #define RMON_SQE_TEST_ERRORS 0x19 | |
450 | #define RMON_PAUSE_MACCTRL_FRAMES_XMITTED 0x1A | |
451 | #define RMON_MACCTRL_FRAMES_XMITTED 0x1B | |
452 | #define RMON_VLAN_FRAMES_XMITTED 0x1C | |
453 | #define RMON_OCTETS_XMITTED_OK 0x1D | |
454 | #define RMON_OCTETS_XMITTED_OK_HI 0x1E | |
455 | ||
456 | #define RMON_RX_PACKET_SIZES0 0x40 | |
457 | #define RMON_RX_PACKET_SIZES1 0x41 | |
458 | #define RMON_RX_PACKET_SIZES2 0x42 | |
459 | #define RMON_RX_PACKET_SIZES3 0x43 | |
460 | #define RMON_RX_PACKET_SIZES4 0x44 | |
461 | #define RMON_RX_PACKET_SIZES5 0x45 | |
462 | #define RMON_RX_PACKET_SIZES6 0x46 | |
463 | #define RMON_RX_PACKET_SIZES7 0x47 | |
464 | #define RMON_FRAME_CHECK_SEQUENCE_ERRORS 0x48 | |
465 | #define RMON_ALIGNMENT_ERRORS 0x49 | |
466 | #define RMON_FRAGMENTS 0x4A | |
467 | #define RMON_JABBERS 0x4B | |
468 | #define RMON_FRAMES_LOST_TO_INTMACRCVERR 0x4C | |
469 | #define RMON_UNICAST_FRAMES_RCVD_OK 0x4D | |
470 | #define RMON_MULTICAST_FRAMES_RCVD_OK 0x4E | |
471 | #define RMON_BROADCAST_FRAMES_RCVD_OK 0x4F | |
472 | #define RMON_IN_RANGE_LENGTH_ERRORS 0x50 | |
473 | #define RMON_OUT_OF_RANGE_LENGTH_ERRORS 0x51 | |
474 | #define RMON_VLAN_FRAMES_RCVD 0x52 | |
475 | #define RMON_PAUSE_MAC_CTRL_FRAMES_RCVD 0x53 | |
476 | #define RMON_MAC_CTRL_FRAMES_RCVD 0x54 | |
477 | #define RMON_OCTETS_RCVD_OK 0x55 | |
478 | #define RMON_OCTETS_RCVD_OK_HI 0x56 | |
479 | #define RMON_OCTETS_RCVD_OTHER 0x57 | |
480 | #define RMON_OCTETS_RCVD_OTHER_HI 0x58 | |
481 | ||
482 | #endif /* __ETHER00_H */ |