[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / xen / xen-pciback / conf_space_header.c

/*
 * PCI Backend - Handles the virtual fields in the configuration space headers.
 *
 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include "pciback.h"
#include "conf_space.h"

struct pci_cmd_info {
	u16 val;
};

struct pci_bar_info {
	u32 val;
	u32 len_val;
	int which;
};

#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
#define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)

/* Bits guests are allowed to control in permissive mode. */
#define PCI_COMMAND_GUEST (PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL| \
			   PCI_COMMAND_INVALIDATE|PCI_COMMAND_VGA_PALETTE| \
			   PCI_COMMAND_WAIT|PCI_COMMAND_FAST_BACK)

static void *command_init(struct pci_dev *dev, int offset)
{
	struct pci_cmd_info *cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
	int err;

	if (!cmd)
		return ERR_PTR(-ENOMEM);

	err = pci_read_config_word(dev, PCI_COMMAND, &cmd->val);
	if (err) {
		kfree(cmd);
		return ERR_PTR(err);
	}

	return cmd;
}

static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
{
	int ret = pci_read_config_word(dev, offset, value);
	const struct pci_cmd_info *cmd = data;

	*value &= PCI_COMMAND_GUEST;
	*value |= cmd->val & ~PCI_COMMAND_GUEST;

	return ret;
}

static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
{
	struct xen_pcibk_dev_data *dev_data;
	int err;
	u16 val;
	struct pci_cmd_info *cmd = data;

	dev_data = pci_get_drvdata(dev);
	if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
			       pci_name(dev));
		err = pci_enable_device(dev);
		if (err)
			return err;
		if (dev_data)
			dev_data->enable_intx = 1;
	} else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
			       pci_name(dev));
		pci_disable_device(dev);
		if (dev_data)
			dev_data->enable_intx = 0;
	}

	if (!dev->is_busmaster && is_master_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
			       pci_name(dev));
		pci_set_master(dev);
	}

	if (value & PCI_COMMAND_INVALIDATE) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG
			       DRV_NAME ": %s: enable memory-write-invalidate\n",
			       pci_name(dev));
		err = pci_set_mwi(dev);
		if (err) {
			printk(KERN_WARNING
			       DRV_NAME ": %s: cannot enable "
			       "memory-write-invalidate (%d)\n",
			       pci_name(dev), err);
			value &= ~PCI_COMMAND_INVALIDATE;
		}
	}

	cmd->val = value;

	if (!permissive && (!dev_data || !dev_data->permissive))
		return 0;

	/* Only allow the guest to control certain bits. */
	err = pci_read_config_word(dev, offset, &val);
	if (err || val == value)
		return err;

	value &= PCI_COMMAND_GUEST;
	value |= val & ~PCI_COMMAND_GUEST;

	return pci_write_config_word(dev, offset, value);
}

static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
{
	struct pci_bar_info *bar = data;

	if (unlikely(!bar)) {
		printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
		       pci_name(dev));
		return XEN_PCI_ERR_op_failed;
	}

	/* A write to obtain the length must happen as a 32-bit write.
	 * This does not (yet) support writing individual bytes
	 */
	if (value == ~PCI_ROM_ADDRESS_ENABLE)
		bar->which = 1;
	else {
		u32 tmpval;
		pci_read_config_dword(dev, offset, &tmpval);
		if (tmpval != bar->val && value == bar->val) {
			/* Allow restoration of bar value. */
			pci_write_config_dword(dev, offset, bar->val);
		}
		bar->which = 0;
	}

	/* Do we need to support enabling/disabling the rom address here? */

	return 0;
}

/* For the BARs, only allow writes which write ~0 or
 * the correct resource information
 * (Needed for when the driver probes the resource usage)
 */
static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data)
{
	struct pci_bar_info *bar = data;

	if (unlikely(!bar)) {
		printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
		       pci_name(dev));
		return XEN_PCI_ERR_op_failed;
	}

	/* A write to obtain the length must happen as a 32-bit write.
	 * This does not (yet) support writing individual bytes
	 */
	if (value == ~0)
		bar->which = 1;
	else {
		u32 tmpval;
		pci_read_config_dword(dev, offset, &tmpval);
		if (tmpval != bar->val && value == bar->val) {
			/* Allow restoration of bar value. */
			pci_write_config_dword(dev, offset, bar->val);
		}
		bar->which = 0;
	}

	return 0;
}

static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data)
{
	struct pci_bar_info *bar = data;

	if (unlikely(!bar)) {
		printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
		       pci_name(dev));
		return XEN_PCI_ERR_op_failed;
	}

	*value = bar->which ? bar->len_val : bar->val;

	return 0;
}

static inline void read_dev_bar(struct pci_dev *dev,
				struct pci_bar_info *bar_info, int offset,
				u32 len_mask)
{
	int	pos;
	struct resource	*res = dev->resource;

	if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
		pos = PCI_ROM_RESOURCE;
	else {
		pos = (offset - PCI_BASE_ADDRESS_0) / 4;
		if (pos && ((res[pos - 1].flags & (PCI_BASE_ADDRESS_SPACE |
				PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
			   (PCI_BASE_ADDRESS_SPACE_MEMORY |
				PCI_BASE_ADDRESS_MEM_TYPE_64))) {
			bar_info->val = res[pos - 1].start >> 32;
			bar_info->len_val = res[pos - 1].end >> 32;
			return;
		}
	}

	bar_info->val = res[pos].start |
			(res[pos].flags & PCI_REGION_FLAG_MASK);
	bar_info->len_val = resource_size(&res[pos]);
}

static void *bar_init(struct pci_dev *dev, int offset)
{
	struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);

	if (!bar)
		return ERR_PTR(-ENOMEM);

	read_dev_bar(dev, bar, offset, ~0);
	bar->which = 0;

	return bar;
}

static void *rom_init(struct pci_dev *dev, int offset)
{
	struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);

	if (!bar)
		return ERR_PTR(-ENOMEM);

	read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE);
	bar->which = 0;

	return bar;
}

static void bar_reset(struct pci_dev *dev, int offset, void *data)
{
	struct pci_bar_info *bar = data;

	bar->which = 0;
}

static void bar_release(struct pci_dev *dev, int offset, void *data)
{
	kfree(data);
}

static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
			       u16 *value, void *data)
{
	*value = dev->vendor;

	return 0;
}

static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
			       u16 *value, void *data)
{
	*value = dev->device;

	return 0;
}

static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
			  void *data)
{
	*value = (u8) dev->irq;

	return 0;
}

static int bist_write(struct pci_dev *dev, int offset, u8 value, void *data)
{
	u8 cur_value;
	int err;

	err = pci_read_config_byte(dev, offset, &cur_value);
	if (err)
		goto out;

	if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
	    || value == PCI_BIST_START)
		err = pci_write_config_byte(dev, offset, value);

out:
	return err;
}

static const struct config_field header_common[] = {
	{
	 .offset    = PCI_VENDOR_ID,
	 .size      = 2,
	 .u.w.read  = xen_pcibk_read_vendor,
	},
	{
	 .offset    = PCI_DEVICE_ID,
	 .size      = 2,
	 .u.w.read  = xen_pcibk_read_device,
	},
	{
	 .offset    = PCI_COMMAND,
	 .size      = 2,
	 .init      = command_init,
	 .release   = bar_release,
	 .u.w.read  = command_read,
	 .u.w.write = command_write,
	},
	{
	 .offset    = PCI_INTERRUPT_LINE,
	 .size      = 1,
	 .u.b.read  = interrupt_read,
	},
	{
	 .offset    = PCI_INTERRUPT_PIN,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	},
	{
	 /* Any side effects of letting driver domain control cache line? */
	 .offset    = PCI_CACHE_LINE_SIZE,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	 .u.b.write = xen_pcibk_write_config_byte,
	},
	{
	 .offset    = PCI_LATENCY_TIMER,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	},
	{
	 .offset    = PCI_BIST,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	 .u.b.write = bist_write,
	},
	{}
};

#define CFG_FIELD_BAR(reg_offset)			\
	{						\
	.offset     = reg_offset,			\
	.size       = 4,				\
	.init       = bar_init,				\
	.reset      = bar_reset,			\
	.release    = bar_release,			\
	.u.dw.read  = bar_read,				\
	.u.dw.write = bar_write,			\
	}

#define CFG_FIELD_ROM(reg_offset)			\
	{						\
	.offset     = reg_offset,			\
	.size       = 4,				\
	.init       = rom_init,				\
	.reset      = bar_reset,			\
	.release    = bar_release,			\
	.u.dw.read  = bar_read,				\
	.u.dw.write = rom_write,			\
	}

static const struct config_field header_0[] = {
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
	CFG_FIELD_ROM(PCI_ROM_ADDRESS),
	{}
};

static const struct config_field header_1[] = {
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
	{}
};

int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
{
	int err;

	err = xen_pcibk_config_add_fields(dev, header_common);
	if (err)
		goto out;

	switch (dev->hdr_type) {
	case PCI_HEADER_TYPE_NORMAL:
		err = xen_pcibk_config_add_fields(dev, header_0);
		break;

	case PCI_HEADER_TYPE_BRIDGE:
		err = xen_pcibk_config_add_fields(dev, header_1);
		break;

	default:
		err = -EINVAL;
		printk(KERN_ERR DRV_NAME ": %s: Unsupported header type %d!\n",
		       pci_name(dev), dev->hdr_type);
		break;
	}

out:
	return err;
}
Commit	Line	Data
30edc14b KRW	1	/*
	2	* PCI Backend - Handles the virtual fields in the configuration space headers.
	3	*
	4	* Author: Ryan Wilson <hap9@epoch.ncsc.mil>
	5	*/
	6
	7	#include <linux/kernel.h>
	8	#include <linux/pci.h>
	9	#include "pciback.h"
	10	#include "conf_space.h"
	11
1c335229 JB	12	struct pci_cmd_info {
	13	u16 val;
	14	};
	15
30edc14b KRW	16	struct pci_bar_info {
	17	u32 val;
	18	u32 len_val;
	19	int which;
	20	};
	21
	22	#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY\|PCI_COMMAND_IO))
	23	#define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
	24
1c335229 JB	25	/* Bits guests are allowed to control in permissive mode. */
	26	#define PCI_COMMAND_GUEST (PCI_COMMAND_MASTER\|PCI_COMMAND_SPECIAL\| \
	27	PCI_COMMAND_INVALIDATE\|PCI_COMMAND_VGA_PALETTE\| \
	28	PCI_COMMAND_WAIT\|PCI_COMMAND_FAST_BACK)
	29
	30	static void command_init(struct pci_dev dev, int offset)
fd5b221b	31	{
1c335229 JB	32	struct pci_cmd_info cmd = kmalloc(sizeof(cmd), GFP_KERNEL);
	33	int err;
	34
	35	if (!cmd)
	36	return ERR_PTR(-ENOMEM);
	37
	38	err = pci_read_config_word(dev, PCI_COMMAND, &cmd->val);
	39	if (err) {
	40	kfree(cmd);
	41	return ERR_PTR(err);
fd5b221b ZY	42	}
fd5b221b ZY	43
1c335229 JB	44	return cmd;
	45	}
	46
	47	static int command_read(struct pci_dev dev, int offset, u16 value, void *data)
	48	{
	49	int ret = pci_read_config_word(dev, offset, value);
	50	const struct pci_cmd_info *cmd = data;
	51
	52	*value &= PCI_COMMAND_GUEST;
	53	*value \|= cmd->val & ~PCI_COMMAND_GUEST;
	54
fd5b221b ZY	55	return ret;
	56	}
	57
30edc14b KRW	58	static int command_write(struct pci_dev dev, int offset, u16 value, void data)
30edc14b KRW	59	{
a92336a1	60	struct xen_pcibk_dev_data *dev_data;
30edc14b	61	int err;
1c335229 JB	62	u16 val;
1c335229 JB	63	struct pci_cmd_info *cmd = data;
30edc14b	64
0513fe9e	65	dev_data = pci_get_drvdata(dev);
30edc14b KRW	66	if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
30edc14b KRW	67	if (unlikely(verbose_request))
a92336a1	68	printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
30edc14b KRW	69	pci_name(dev));
	70	err = pci_enable_device(dev);
	71	if (err)
	72	return err;
0513fe9e KRW	73	if (dev_data)
0513fe9e KRW	74	dev_data->enable_intx = 1;
30edc14b KRW	75	} else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
30edc14b KRW	76	if (unlikely(verbose_request))
a92336a1	77	printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
30edc14b KRW	78	pci_name(dev));
30edc14b KRW	79	pci_disable_device(dev);
0513fe9e KRW	80	if (dev_data)
0513fe9e KRW	81	dev_data->enable_intx = 0;
30edc14b KRW	82	}
	83
	84	if (!dev->is_busmaster && is_master_cmd(value)) {
	85	if (unlikely(verbose_request))
a92336a1	86	printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
30edc14b KRW	87	pci_name(dev));
	88	pci_set_master(dev);
	89	}
	90
	91	if (value & PCI_COMMAND_INVALIDATE) {
	92	if (unlikely(verbose_request))
	93	printk(KERN_DEBUG
a92336a1	94	DRV_NAME ": %s: enable memory-write-invalidate\n",
30edc14b KRW	95	pci_name(dev));
	96	err = pci_set_mwi(dev);
	97	if (err) {
	98	printk(KERN_WARNING
a92336a1	99	DRV_NAME ": %s: cannot enable "
30edc14b KRW	100	"memory-write-invalidate (%d)\n",
	101	pci_name(dev), err);
	102	value &= ~PCI_COMMAND_INVALIDATE;
	103	}
	104	}
	105
1c335229 JB	106	cmd->val = value;
	107
	108	if (!permissive && (!dev_data \|\| !dev_data->permissive))
	109	return 0;
	110
	111	/* Only allow the guest to control certain bits. */
	112	err = pci_read_config_word(dev, offset, &val);
	113	if (err \|\| val == value)
	114	return err;
	115
	116	value &= PCI_COMMAND_GUEST;
	117	value \|= val & ~PCI_COMMAND_GUEST;
	118
30edc14b KRW	119	return pci_write_config_word(dev, offset, value);
	120	}
	121
	122	static int rom_write(struct pci_dev dev, int offset, u32 value, void data)
	123	{
	124	struct pci_bar_info *bar = data;
	125
	126	if (unlikely(!bar)) {
a92336a1	127	printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
30edc14b KRW	128	pci_name(dev));
	129	return XEN_PCI_ERR_op_failed;
	130	}
	131
	132	/* A write to obtain the length must happen as a 32-bit write.
	133	* This does not (yet) support writing individual bytes
	134	*/
	135	if (value == ~PCI_ROM_ADDRESS_ENABLE)
	136	bar->which = 1;
	137	else {
	138	u32 tmpval;
	139	pci_read_config_dword(dev, offset, &tmpval);
	140	if (tmpval != bar->val && value == bar->val) {
	141	/* Allow restoration of bar value. */
	142	pci_write_config_dword(dev, offset, bar->val);
	143	}
	144	bar->which = 0;
	145	}
	146
	147	/* Do we need to support enabling/disabling the rom address here? */
	148
	149	return 0;
	150	}
	151
	152	/* For the BARs, only allow writes which write ~0 or
	153	* the correct resource information
	154	* (Needed for when the driver probes the resource usage)
	155	*/
	156	static int bar_write(struct pci_dev dev, int offset, u32 value, void data)
	157	{
	158	struct pci_bar_info *bar = data;
	159
	160	if (unlikely(!bar)) {
a92336a1	161	printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
30edc14b KRW	162	pci_name(dev));
	163	return XEN_PCI_ERR_op_failed;
	164	}
	165
	166	/* A write to obtain the length must happen as a 32-bit write.
	167	* This does not (yet) support writing individual bytes
	168	*/
	169	if (value == ~0)
	170	bar->which = 1;
	171	else {
	172	u32 tmpval;
	173	pci_read_config_dword(dev, offset, &tmpval);
	174	if (tmpval != bar->val && value == bar->val) {
	175	/* Allow restoration of bar value. */
	176	pci_write_config_dword(dev, offset, bar->val);
	177	}
	178	bar->which = 0;
	179	}
	180
	181	return 0;
	182	}
	183
	184	static int bar_read(struct pci_dev dev, int offset, u32 value, void *data)
	185	{
	186	struct pci_bar_info *bar = data;
	187
	188	if (unlikely(!bar)) {
a92336a1	189	printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
30edc14b KRW	190	pci_name(dev));
	191	return XEN_PCI_ERR_op_failed;
	192	}
	193
	194	*value = bar->which ? bar->len_val : bar->val;
	195
	196	return 0;
	197	}
	198
	199	static inline void read_dev_bar(struct pci_dev *dev,
	200	struct pci_bar_info *bar_info, int offset,
	201	u32 len_mask)
	202	{
fd5b221b ZY	203	int pos;
	204	struct resource *res = dev->resource;
	205
	206	if (offset == PCI_ROM_ADDRESS \|\| offset == PCI_ROM_ADDRESS1)
	207	pos = PCI_ROM_RESOURCE;
	208	else {
	209	pos = (offset - PCI_BASE_ADDRESS_0) / 4;
	210	if (pos && ((res[pos - 1].flags & (PCI_BASE_ADDRESS_SPACE \|
	211	PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
	212	(PCI_BASE_ADDRESS_SPACE_MEMORY \|
	213	PCI_BASE_ADDRESS_MEM_TYPE_64))) {
	214	bar_info->val = res[pos - 1].start >> 32;
	215	bar_info->len_val = res[pos - 1].end >> 32;
	216	return;
	217	}
	218	}
	219
	220	bar_info->val = res[pos].start \|
	221	(res[pos].flags & PCI_REGION_FLAG_MASK);
5fa99911	222	bar_info->len_val = resource_size(&res[pos]);
30edc14b KRW	223	}
	224
	225	static void bar_init(struct pci_dev dev, int offset)
	226	{
	227	struct pci_bar_info bar = kmalloc(sizeof(bar), GFP_KERNEL);
	228
	229	if (!bar)
	230	return ERR_PTR(-ENOMEM);
	231
	232	read_dev_bar(dev, bar, offset, ~0);
	233	bar->which = 0;
	234
	235	return bar;
	236	}
	237
	238	static void rom_init(struct pci_dev dev, int offset)
	239	{
	240	struct pci_bar_info bar = kmalloc(sizeof(bar), GFP_KERNEL);
	241
	242	if (!bar)
	243	return ERR_PTR(-ENOMEM);
	244
	245	read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE);
	246	bar->which = 0;
	247
	248	return bar;
	249	}
	250
	251	static void bar_reset(struct pci_dev dev, int offset, void data)
	252	{
	253	struct pci_bar_info *bar = data;
	254
	255	bar->which = 0;
	256	}
	257
	258	static void bar_release(struct pci_dev dev, int offset, void data)
	259	{
	260	kfree(data);
	261	}
	262
a92336a1	263	static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
fd5b221b ZY	264	u16 value, void data)
	265	{
	266	*value = dev->vendor;
	267
	268	return 0;
	269	}
	270
a92336a1	271	static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
fd5b221b ZY	272	u16 value, void data)
	273	{
	274	*value = dev->device;
	275
	276	return 0;
	277	}
	278
30edc14b KRW	279	static int interrupt_read(struct pci_dev dev, int offset, u8 value,
	280	void *data)
	281	{
	282	*value = (u8) dev->irq;
	283
	284	return 0;
	285	}
	286
	287	static int bist_write(struct pci_dev dev, int offset, u8 value, void data)
	288	{
	289	u8 cur_value;
	290	int err;
	291
	292	err = pci_read_config_byte(dev, offset, &cur_value);
	293	if (err)
	294	goto out;
	295
	296	if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
	297	\|\| value == PCI_BIST_START)
	298	err = pci_write_config_byte(dev, offset, value);
	299
	300	out:
	301	return err;
	302	}
	303
	304	static const struct config_field header_common[] = {
fd5b221b ZY	305	{
	306	.offset = PCI_VENDOR_ID,
	307	.size = 2,
a92336a1	308	.u.w.read = xen_pcibk_read_vendor,
fd5b221b ZY	309	},
	310	{
	311	.offset = PCI_DEVICE_ID,
	312	.size = 2,
a92336a1	313	.u.w.read = xen_pcibk_read_device,
fd5b221b	314	},
30edc14b KRW	315	{
	316	.offset = PCI_COMMAND,
	317	.size = 2,
1c335229 JB	318	.init = command_init,
1c335229 JB	319	.release = bar_release,
fd5b221b	320	.u.w.read = command_read,
30edc14b KRW	321	.u.w.write = command_write,
	322	},
	323	{
	324	.offset = PCI_INTERRUPT_LINE,
	325	.size = 1,
	326	.u.b.read = interrupt_read,
	327	},
	328	{
	329	.offset = PCI_INTERRUPT_PIN,
	330	.size = 1,
a92336a1	331	.u.b.read = xen_pcibk_read_config_byte,
30edc14b KRW	332	},
	333	{
	334	/* Any side effects of letting driver domain control cache line? */
	335	.offset = PCI_CACHE_LINE_SIZE,
	336	.size = 1,
a92336a1 KRW	337	.u.b.read = xen_pcibk_read_config_byte,
a92336a1 KRW	338	.u.b.write = xen_pcibk_write_config_byte,
30edc14b KRW	339	},
	340	{
	341	.offset = PCI_LATENCY_TIMER,
	342	.size = 1,
a92336a1	343	.u.b.read = xen_pcibk_read_config_byte,
30edc14b KRW	344	},
	345	{
	346	.offset = PCI_BIST,
	347	.size = 1,
a92336a1	348	.u.b.read = xen_pcibk_read_config_byte,
30edc14b KRW	349	.u.b.write = bist_write,
	350	},
	351	{}
	352	};
	353
8bfd4e02 KRW	354	#define CFG_FIELD_BAR(reg_offset) \
	355	{ \
	356	.offset = reg_offset, \
	357	.size = 4, \
	358	.init = bar_init, \
	359	.reset = bar_reset, \
	360	.release = bar_release, \
	361	.u.dw.read = bar_read, \
	362	.u.dw.write = bar_write, \
	363	}
	364
	365	#define CFG_FIELD_ROM(reg_offset) \
	366	{ \
	367	.offset = reg_offset, \
	368	.size = 4, \
	369	.init = rom_init, \
	370	.reset = bar_reset, \
	371	.release = bar_release, \
	372	.u.dw.read = bar_read, \
	373	.u.dw.write = rom_write, \
	374	}
30edc14b KRW	375
	376	static const struct config_field header_0[] = {
	377	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	378	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	379	CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
	380	CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
	381	CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
	382	CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
	383	CFG_FIELD_ROM(PCI_ROM_ADDRESS),
	384	{}
	385	};
	386
	387	static const struct config_field header_1[] = {
	388	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	389	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	390	CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
	391	{}
	392	};
	393
a92336a1	394	int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
30edc14b KRW	395	{
	396	int err;
	397
a92336a1	398	err = xen_pcibk_config_add_fields(dev, header_common);
30edc14b KRW	399	if (err)
	400	goto out;
	401
	402	switch (dev->hdr_type) {
	403	case PCI_HEADER_TYPE_NORMAL:
a92336a1	404	err = xen_pcibk_config_add_fields(dev, header_0);
30edc14b KRW	405	break;
	406
	407	case PCI_HEADER_TYPE_BRIDGE:
a92336a1	408	err = xen_pcibk_config_add_fields(dev, header_1);
30edc14b KRW	409	break;
	410
	411	default:
	412	err = -EINVAL;
a92336a1	413	printk(KERN_ERR DRV_NAME ": %s: Unsupported header type %d!\n",
30edc14b KRW	414	pci_name(dev), dev->hdr_type);
	415	break;
	416	}
	417
	418	out:
	419	return err;
	420	}