[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / watchdog / ath79_wdt.c

/*
 * Atheros AR71XX/AR724X/AR913X built-in hardware watchdog timer.
 *
 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 *
 * This driver was based on: drivers/watchdog/ixp4xx_wdt.c
 *	Author: Deepak Saxena <dsaxena@plexity.net>
 *	Copyright 2004 (c) MontaVista, Software, Inc.
 *
 * which again was based on sa1100 driver,
 *	Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 *
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/miscdevice.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_platform.h>

#define DRIVER_NAME	"ath79-wdt"

#define WDT_TIMEOUT	15	/* seconds */

#define WDOG_REG_CTRL		0x00
#define WDOG_REG_TIMER		0x04

#define WDOG_CTRL_LAST_RESET	BIT(31)
#define WDOG_CTRL_ACTION_MASK	3
#define WDOG_CTRL_ACTION_NONE	0	/* no action */
#define WDOG_CTRL_ACTION_GPI	1	/* general purpose interrupt */
#define WDOG_CTRL_ACTION_NMI	2	/* NMI */
#define WDOG_CTRL_ACTION_FCR	3	/* full chip reset */

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
			   "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static int timeout = WDT_TIMEOUT;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds "
			  "(default=" __MODULE_STRING(WDT_TIMEOUT) "s)");

static unsigned long wdt_flags;

#define WDT_FLAGS_BUSY		0
#define WDT_FLAGS_EXPECT_CLOSE	1

static struct clk *wdt_clk;
static unsigned long wdt_freq;
static int boot_status;
static int max_timeout;
static void __iomem *wdt_base;

static inline void ath79_wdt_wr(unsigned reg, u32 val)
{
	iowrite32(val, wdt_base + reg);
}

static inline u32 ath79_wdt_rr(unsigned reg)
{
	return ioread32(wdt_base + reg);
}

static inline void ath79_wdt_keepalive(void)
{
	ath79_wdt_wr(WDOG_REG_TIMER, wdt_freq * timeout);
	/* flush write */
	ath79_wdt_rr(WDOG_REG_TIMER);
}

static inline void ath79_wdt_enable(void)
{
	ath79_wdt_keepalive();

	/*
	 * Updating the TIMER register requires a few microseconds
	 * on the AR934x SoCs at least. Use a small delay to ensure
	 * that the TIMER register is updated within the hardware
	 * before enabling the watchdog.
	 */
	udelay(2);

	ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_FCR);
	/* flush write */
	ath79_wdt_rr(WDOG_REG_CTRL);
}

static inline void ath79_wdt_disable(void)
{
	ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_NONE);
	/* flush write */
	ath79_wdt_rr(WDOG_REG_CTRL);
}

static int ath79_wdt_set_timeout(int val)
{
	if (val < 1 || val > max_timeout)
		return -EINVAL;

	timeout = val;
	ath79_wdt_keepalive();

	return 0;
}

static int ath79_wdt_open(struct inode *inode, struct file *file)
{
	if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags))
		return -EBUSY;

	clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
	ath79_wdt_enable();

	return nonseekable_open(inode, file);
}

static int ath79_wdt_release(struct inode *inode, struct file *file)
{
	if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags))
		ath79_wdt_disable();
	else {
		pr_crit("device closed unexpectedly, watchdog timer will not stop!\n");
		ath79_wdt_keepalive();
	}

	clear_bit(WDT_FLAGS_BUSY, &wdt_flags);
	clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);

	return 0;
}

static ssize_t ath79_wdt_write(struct file *file, const char *data,
				size_t len, loff_t *ppos)
{
	if (len) {
		if (!nowayout) {
			size_t i;

			clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);

			for (i = 0; i != len; i++) {
				char c;

				if (get_user(c, data + i))
					return -EFAULT;

				if (c == 'V')
					set_bit(WDT_FLAGS_EXPECT_CLOSE,
						&wdt_flags);
			}
		}

		ath79_wdt_keepalive();
	}

	return len;
}

static const struct watchdog_info ath79_wdt_info = {
	.options		= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
				  WDIOF_MAGICCLOSE | WDIOF_CARDRESET,
	.firmware_version	= 0,
	.identity		= "ATH79 watchdog",
};

static long ath79_wdt_ioctl(struct file *file, unsigned int cmd,
			    unsigned long arg)
{
	void __user *argp = (void __user *)arg;
	int __user *p = argp;
	int err;
	int t;

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		err = copy_to_user(argp, &ath79_wdt_info,
				   sizeof(ath79_wdt_info)) ? -EFAULT : 0;
		break;

	case WDIOC_GETSTATUS:
		err = put_user(0, p);
		break;

	case WDIOC_GETBOOTSTATUS:
		err = put_user(boot_status, p);
		break;

	case WDIOC_KEEPALIVE:
		ath79_wdt_keepalive();
		err = 0;
		break;

	case WDIOC_SETTIMEOUT:
		err = get_user(t, p);
		if (err)
			break;

		err = ath79_wdt_set_timeout(t);
		if (err)
			break;

		/* fallthrough */
	case WDIOC_GETTIMEOUT:
		err = put_user(timeout, p);
		break;

	default:
		err = -ENOTTY;
		break;
	}

	return err;
}

static const struct file_operations ath79_wdt_fops = {
	.owner		= THIS_MODULE,
	.llseek		= no_llseek,
	.write		= ath79_wdt_write,
	.unlocked_ioctl	= ath79_wdt_ioctl,
	.open		= ath79_wdt_open,
	.release	= ath79_wdt_release,
};

static struct miscdevice ath79_wdt_miscdev = {
	.minor = WATCHDOG_MINOR,
	.name = "watchdog",
	.fops = &ath79_wdt_fops,
};

static int ath79_wdt_probe(struct platform_device *pdev)
{
	struct resource *res;
	u32 ctrl;
	int err;

	if (wdt_base)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	wdt_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(wdt_base))
		return PTR_ERR(wdt_base);

	wdt_clk = devm_clk_get(&pdev->dev, "wdt");
	if (IS_ERR(wdt_clk))
		return PTR_ERR(wdt_clk);

	err = clk_enable(wdt_clk);
	if (err)
		return err;

	wdt_freq = clk_get_rate(wdt_clk);
	if (!wdt_freq) {
		err = -EINVAL;
		goto err_clk_disable;
	}

	max_timeout = (0xfffffffful / wdt_freq);
	if (timeout < 1 || timeout > max_timeout) {
		timeout = max_timeout;
		dev_info(&pdev->dev,
			"timeout value must be 0 < timeout < %d, using %d\n",
			max_timeout, timeout);
	}

	ctrl = ath79_wdt_rr(WDOG_REG_CTRL);
	boot_status = (ctrl & WDOG_CTRL_LAST_RESET) ? WDIOF_CARDRESET : 0;

	err = misc_register(&ath79_wdt_miscdev);
	if (err) {
		dev_err(&pdev->dev,
			"unable to register misc device, err=%d\n", err);
		goto err_clk_disable;
	}

	return 0;

err_clk_disable:
	clk_disable(wdt_clk);
	return err;
}

static int ath79_wdt_remove(struct platform_device *pdev)
{
	misc_deregister(&ath79_wdt_miscdev);
	clk_disable(wdt_clk);
	return 0;
}

static void ath97_wdt_shutdown(struct platform_device *pdev)
{
	ath79_wdt_disable();
}

#ifdef CONFIG_OF
static const struct of_device_id ath79_wdt_match[] = {
	{ .compatible = "qca,ar7130-wdt" },
	{},
};
MODULE_DEVICE_TABLE(of, ath79_wdt_match);
#endif

static struct platform_driver ath79_wdt_driver = {
	.probe		= ath79_wdt_probe,
	.remove		= ath79_wdt_remove,
	.shutdown	= ath97_wdt_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(ath79_wdt_match),
	},
};

module_platform_driver(ath79_wdt_driver);

MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X hardware watchdog driver");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Commit	Line	Data
f8394f61 GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X built-in hardware watchdog timer.
	3	*
	4	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
	5	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
	6	*
	7	* This driver was based on: drivers/watchdog/ixp4xx_wdt.c
	8	* Author: Deepak Saxena <dsaxena@plexity.net>
	9	* Copyright 2004 (c) MontaVista, Software, Inc.
	10	*
	11	* which again was based on sa1100 driver,
	12	* Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
	13	*
	14	* This program is free software; you can redistribute it and/or modify it
	15	* under the terms of the GNU General Public License version 2 as published
	16	* by the Free Software Foundation.
	17	*
	18	*/
	19
27c766aa JP	20	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	21
f8394f61	22	#include <linux/bitops.h>
be8d53f0	23	#include <linux/delay.h>
f8394f61 GJ	24	#include <linux/errno.h>
	25	#include <linux/fs.h>
	26	#include <linux/init.h>
09f5100a	27	#include <linux/io.h>
f8394f61 GJ	28	#include <linux/kernel.h>
	29	#include <linux/miscdevice.h>
	30	#include <linux/module.h>
	31	#include <linux/moduleparam.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/types.h>
	34	#include <linux/watchdog.h>
	35	#include <linux/clk.h>
	36	#include <linux/err.h>
15920d12 GJ	37	#include <linux/of.h>
15920d12 GJ	38	#include <linux/of_platform.h>
f8394f61	39
f8394f61 GJ	40	#define DRIVER_NAME "ath79-wdt"
	41
	42	#define WDT_TIMEOUT 15 /* seconds */
	43
09f5100a GJ	44	#define WDOG_REG_CTRL 0x00
	45	#define WDOG_REG_TIMER 0x04
	46
f8394f61 GJ	47	#define WDOG_CTRL_LAST_RESET BIT(31)
	48	#define WDOG_CTRL_ACTION_MASK 3
	49	#define WDOG_CTRL_ACTION_NONE 0 /* no action */
	50	#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
	51	#define WDOG_CTRL_ACTION_NMI 2 /* NMI */
	52	#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
	53
86a1e189 WVS	54	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	55	module_param(nowayout, bool, 0);
f8394f61 GJ	56	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	57	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	58
	59	static int timeout = WDT_TIMEOUT;
	60	module_param(timeout, int, 0);
	61	MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds "
	62	"(default=" __MODULE_STRING(WDT_TIMEOUT) "s)");
	63
	64	static unsigned long wdt_flags;
	65
	66	#define WDT_FLAGS_BUSY 0
	67	#define WDT_FLAGS_EXPECT_CLOSE 1
	68
	69	static struct clk *wdt_clk;
	70	static unsigned long wdt_freq;
	71	static int boot_status;
	72	static int max_timeout;
09f5100a GJ	73	static void __iomem *wdt_base;
	74
	75	static inline void ath79_wdt_wr(unsigned reg, u32 val)
	76	{
	77	iowrite32(val, wdt_base + reg);
	78	}
	79
	80	static inline u32 ath79_wdt_rr(unsigned reg)
	81	{
	82	return ioread32(wdt_base + reg);
	83	}
f8394f61 GJ	84
	85	static inline void ath79_wdt_keepalive(void)
	86	{
09f5100a	87	ath79_wdt_wr(WDOG_REG_TIMER, wdt_freq * timeout);
86955e2b	88	/* flush write */
09f5100a	89	ath79_wdt_rr(WDOG_REG_TIMER);
f8394f61 GJ	90	}
	91
	92	static inline void ath79_wdt_enable(void)
	93	{
	94	ath79_wdt_keepalive();
be8d53f0 GJ	95
	96	/*
	97	* Updating the TIMER register requires a few microseconds
	98	* on the AR934x SoCs at least. Use a small delay to ensure
	99	* that the TIMER register is updated within the hardware
	100	* before enabling the watchdog.
	101	*/
	102	udelay(2);
	103
09f5100a	104	ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_FCR);
86955e2b	105	/* flush write */
09f5100a	106	ath79_wdt_rr(WDOG_REG_CTRL);
f8394f61 GJ	107	}
	108
	109	static inline void ath79_wdt_disable(void)
	110	{
09f5100a	111	ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_NONE);
86955e2b	112	/* flush write */
09f5100a	113	ath79_wdt_rr(WDOG_REG_CTRL);
f8394f61 GJ	114	}
	115
	116	static int ath79_wdt_set_timeout(int val)
	117	{
	118	if (val < 1 \|\| val > max_timeout)
	119	return -EINVAL;
	120
	121	timeout = val;
	122	ath79_wdt_keepalive();
	123
	124	return 0;
	125	}
	126
	127	static int ath79_wdt_open(struct inode inode, struct file file)
	128	{
	129	if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags))
	130	return -EBUSY;
	131
	132	clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
	133	ath79_wdt_enable();
	134
	135	return nonseekable_open(inode, file);
	136	}
	137
	138	static int ath79_wdt_release(struct inode inode, struct file file)
	139	{
	140	if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags))
	141	ath79_wdt_disable();
	142	else {
27c766aa	143	pr_crit("device closed unexpectedly, watchdog timer will not stop!\n");
f8394f61 GJ	144	ath79_wdt_keepalive();
	145	}
	146
	147	clear_bit(WDT_FLAGS_BUSY, &wdt_flags);
	148	clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
	149
	150	return 0;
	151	}
	152
	153	static ssize_t ath79_wdt_write(struct file file, const char data,
	154	size_t len, loff_t *ppos)
	155	{
	156	if (len) {
	157	if (!nowayout) {
	158	size_t i;
	159
	160	clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
	161
	162	for (i = 0; i != len; i++) {
	163	char c;
	164
	165	if (get_user(c, data + i))
	166	return -EFAULT;
	167
	168	if (c == 'V')
	169	set_bit(WDT_FLAGS_EXPECT_CLOSE,
	170	&wdt_flags);
	171	}
	172	}
	173
	174	ath79_wdt_keepalive();
	175	}
	176
	177	return len;
	178	}
	179
	180	static const struct watchdog_info ath79_wdt_info = {
	181	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \|
	182	WDIOF_MAGICCLOSE \| WDIOF_CARDRESET,
	183	.firmware_version = 0,
	184	.identity = "ATH79 watchdog",
	185	};
	186
	187	static long ath79_wdt_ioctl(struct file *file, unsigned int cmd,
	188	unsigned long arg)
	189	{
	190	void __user argp = (void __user )arg;
	191	int __user *p = argp;
	192	int err;
	193	int t;
	194
	195	switch (cmd) {
	196	case WDIOC_GETSUPPORT:
	197	err = copy_to_user(argp, &ath79_wdt_info,
	198	sizeof(ath79_wdt_info)) ? -EFAULT : 0;
	199	break;
	200
	201	case WDIOC_GETSTATUS:
	202	err = put_user(0, p);
	203	break;
	204
	205	case WDIOC_GETBOOTSTATUS:
	206	err = put_user(boot_status, p);
	207	break;
208
209	case WDIOC_KEEPALIVE:
210	ath79_wdt_keepalive();
211	err = 0;
212	break;
213
214	case WDIOC_SETTIMEOUT:
215	err = get_user(t, p);
216	if (err)
217	break;
218
219	err = ath79_wdt_set_timeout(t);
220	if (err)
221	break;
222
223	/* fallthrough */
224	case WDIOC_GETTIMEOUT:
225	err = put_user(timeout, p);
226	break;
227
228	default:
229	err = -ENOTTY;
230	break;
231	}
232
233	return err;
234	}
235
236	static const struct file_operations ath79_wdt_fops = {
237	.owner = THIS_MODULE,
238	.llseek = no_llseek,
239	.write = ath79_wdt_write,
240	.unlocked_ioctl = ath79_wdt_ioctl,
241	.open = ath79_wdt_open,
242	.release = ath79_wdt_release,
243	};
244
245	static struct miscdevice ath79_wdt_miscdev = {
246	.minor = WATCHDOG_MINOR,
247	.name = "watchdog",
248	.fops = &ath79_wdt_fops,
249	};
250
2d991a16	251	static int ath79_wdt_probe(struct platform_device *pdev)
f8394f61	252	{
09f5100a	253	struct resource *res;
f8394f61 GJ	254	u32 ctrl;
	255	int err;
	256
09f5100a GJ	257	if (wdt_base)
	258	return -EBUSY;
	259
	260	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6330c707 SK	261	wdt_base = devm_ioremap_resource(&pdev->dev, res);
	262	if (IS_ERR(wdt_base))
	263	return PTR_ERR(wdt_base);
09f5100a	264
5071a884	265	wdt_clk = devm_clk_get(&pdev->dev, "wdt");
f8394f61 GJ	266	if (IS_ERR(wdt_clk))
	267	return PTR_ERR(wdt_clk);
	268
	269	err = clk_enable(wdt_clk);
	270	if (err)
5071a884	271	return err;
f8394f61 GJ	272
	273	wdt_freq = clk_get_rate(wdt_clk);
	274	if (!wdt_freq) {
	275	err = -EINVAL;
	276	goto err_clk_disable;
	277	}
	278
	279	max_timeout = (0xfffffffful / wdt_freq);
	280	if (timeout < 1 \|\| timeout > max_timeout) {
	281	timeout = max_timeout;
	282	dev_info(&pdev->dev,
	283	"timeout value must be 0 < timeout < %d, using %d\n",
	284	max_timeout, timeout);
	285	}
	286
09f5100a	287	ctrl = ath79_wdt_rr(WDOG_REG_CTRL);
f8394f61 GJ	288	boot_status = (ctrl & WDOG_CTRL_LAST_RESET) ? WDIOF_CARDRESET : 0;
	289
	290	err = misc_register(&ath79_wdt_miscdev);
	291	if (err) {
	292	dev_err(&pdev->dev,
	293	"unable to register misc device, err=%d\n", err);
	294	goto err_clk_disable;
	295	}
	296
	297	return 0;
	298
	299	err_clk_disable:
	300	clk_disable(wdt_clk);
f8394f61 GJ	301	return err;
	302	}
	303
4b12b896	304	static int ath79_wdt_remove(struct platform_device *pdev)
f8394f61 GJ	305	{
	306	misc_deregister(&ath79_wdt_miscdev);
	307	clk_disable(wdt_clk);
f8394f61 GJ	308	return 0;
	309	}
	310
	311	static void ath97_wdt_shutdown(struct platform_device *pdev)
	312	{
	313	ath79_wdt_disable();
	314	}
	315
15920d12 GJ	316	#ifdef CONFIG_OF
	317	static const struct of_device_id ath79_wdt_match[] = {
	318	{ .compatible = "qca,ar7130-wdt" },
	319	{},
	320	};
	321	MODULE_DEVICE_TABLE(of, ath79_wdt_match);
	322	#endif
	323
f8394f61	324	static struct platform_driver ath79_wdt_driver = {
8157becf	325	.probe = ath79_wdt_probe,
82268714	326	.remove = ath79_wdt_remove,
f8394f61 GJ	327	.shutdown = ath97_wdt_shutdown,
	328	.driver = {
	329	.name = DRIVER_NAME,
	330	.owner = THIS_MODULE,
15920d12	331	.of_match_table = of_match_ptr(ath79_wdt_match),
f8394f61 GJ	332	},
	333	};
	334
8157becf	335	module_platform_driver(ath79_wdt_driver);
f8394f61 GJ	336
	337	MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X hardware watchdog driver");
	338	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
	339	MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org");
	340	MODULE_LICENSE("GPL v2");
	341	MODULE_ALIAS("platform:" DRIVER_NAME);
	342	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);