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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / sm501fb.c
CommitLineData
5fc404e4
BD		 1/* linux/drivers/video/sm501fb.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Vincent Sanders <vince@simtec.co.uk>
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Framebuffer driver for the Silicon Motion SM501
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/mm.h>
19#include <linux/tty.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/fb.h>
23#include <linux/init.h>
24#include <linux/vmalloc.h>
25#include <linux/dma-mapping.h>
26#include <linux/interrupt.h>
27#include <linux/workqueue.h>
28#include <linux/wait.h>
29#include <linux/platform_device.h>
30#include <linux/clk.h>
f22e521f 31#include <linux/console.h>
2d72b11c 32#include <linux/io.h>
5fc404e4 33
5fc404e4
BD		 34#include <asm/uaccess.h>
35#include <asm/div64.h>
36
37#ifdef CONFIG_PM
38#include <linux/pm.h>
39#endif
40
41#include <linux/sm501.h>
42#include <linux/sm501-regs.h>
43
e6a04980
HS		 44#include "edid.h"
45
46static char *fb_mode = "640x480-16@60";
47static unsigned long default_bpp = 16;
48
48c68c4f 49static struct fb_videomode sm501_default_mode = {
e6a04980
HS		 50 .refresh = 60,
51 .xres = 640,
52 .yres = 480,
53 .pixclock = 20833,
54 .left_margin = 142,
55 .right_margin = 13,
56 .upper_margin = 21,
57 .lower_margin = 1,
58 .hsync_len = 69,
59 .vsync_len = 3,
60 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
61 .vmode = FB_VMODE_NONINTERLACED
62};
63
5fc404e4
BD		 64#define NR_PALETTE 256
65
66enum sm501_controller {
67 HEAD_CRT = 0,
68 HEAD_PANEL = 1,
69};
70
d0525419
BD		 71/* SM501 memory address.
72 *
73 * This structure is used to track memory usage within the SM501 framebuffer
74 * allocation. The sm_addr field is stored as an offset as it is often used
75 * against both the physical and mapped addresses.
76 */
5fc404e4
BD		 77struct sm501_mem {
78 unsigned long size;
d0525419 79 unsigned long sm_addr; /* offset from base of sm501 fb. */
5fc404e4
BD		 80 void __iomem *k_addr;
81};
82
83/* private data that is shared between all frambuffers* */
84struct sm501fb_info {
85 struct device *dev;
86 struct fb_info *fb[2]; /* fb info for both heads */
87 struct resource *fbmem_res; /* framebuffer resource */
88 struct resource *regs_res; /* registers resource */
9265576d 89 struct resource *regs2d_res; /* 2d registers resource */
5fc404e4
BD		 90 struct sm501_platdata_fb *pdata; /* our platform data */
91
c1f303bb
BD		 92 unsigned long pm_crt_ctrl; /* pm: crt ctrl save */
93
5fc404e4
BD		 94 int irq;
95 int swap_endian; /* set to swap rgb=>bgr */
96 void __iomem *regs; /* remapped registers */
9265576d 97 void __iomem *regs2d; /* 2d remapped registers */
5fc404e4
BD		 98 void __iomem *fbmem; /* remapped framebuffer */
99 size_t fbmem_len; /* length of remapped region */
e6a04980 100 u8 *edid_data;
5fc404e4
BD		 101};
102
103/* per-framebuffer private data */
104struct sm501fb_par {
105 u32 pseudo_palette[16];
106
107 enum sm501_controller head;
108 struct sm501_mem cursor;
109 struct sm501_mem screen;
110 struct fb_ops ops;
111
112 void *store_fb;
113 void *store_cursor;
114 void __iomem *cursor_regs;
115 struct sm501fb_info *info;
116};
117
118/* Helper functions */
119
120static inline int h_total(struct fb_var_screeninfo *var)
121{
122 return var->xres + var->left_margin +
123 var->right_margin + var->hsync_len;
124}
125
126static inline int v_total(struct fb_var_screeninfo *var)
127{
128 return var->yres + var->upper_margin +
129 var->lower_margin + var->vsync_len;
130}
131
132/* sm501fb_sync_regs()
133 *
134 * This call is mainly for PCI bus systems where we need to
135 * ensure that any writes to the bus are completed before the
136 * next phase, or after completing a function.
137*/
138
139static inline void sm501fb_sync_regs(struct sm501fb_info *info)
140{
bf5f0019 141 smc501_readl(info->regs);
5fc404e4
BD		 142}
143
144/* sm501_alloc_mem
145 *
146 * This is an attempt to lay out memory for the two framebuffers and
147 * everything else
148 *
9265576d
VS		 149 * |fbmem_res->start fbmem_res->end|
150 * | |
151 * |fb[0].fix.smem_start | |fb[1].fix.smem_start | 2K |
5fc404e4
BD		 152 * |-> fb[0].fix.smem_len <-| spare |-> fb[1].fix.smem_len <-|-> cursors <-|
153 *
154 * The "spare" space is for the 2d engine data
155 * the fixed is space for the cursors (2x1Kbyte)
156 *
157 * we need to allocate memory for the 2D acceleration engine
158 * command list and the data for the engine to deal with.
159 *
160 * - all allocations must be 128bit aligned
161 * - cursors are 64x64x2 bits (1Kbyte)
162 *
163 */
164
165#define SM501_MEMF_CURSOR (1)
166#define SM501_MEMF_PANEL (2)
167#define SM501_MEMF_CRT (4)
168#define SM501_MEMF_ACCEL (8)
169
9540f75b 170static int sm501_alloc_mem(struct sm501fb_info *inf, struct sm501_mem *mem,
537a1bf0 171 unsigned int why, size_t size, u32 smem_len)
5fc404e4 172{
d0525419 173 struct sm501fb_par *par;
9b599fb2 174 struct fb_info *fbi;
d0525419
BD		 175 unsigned int ptr;
176 unsigned int end;
5fc404e4
BD		 177
178 switch (why) {
179 case SM501_MEMF_CURSOR:
180 ptr = inf->fbmem_len - size;
d0525419 181 inf->fbmem_len = ptr; /* adjust available memory. */
5fc404e4
BD		 182 break;
183
184 case SM501_MEMF_PANEL:
c00b1b7d 185 if (size > inf->fbmem_len)
186 return -ENOMEM;
187
5fc404e4 188 ptr = inf->fbmem_len - size;
d0525419
BD		 189 fbi = inf->fb[HEAD_CRT];
190
191 /* round down, some programs such as directfb do not draw
192 * 0,0 correctly unless the start is aligned to a page start.
193 */
194
195 if (ptr > 0)
196 ptr &= ~(PAGE_SIZE - 1);
9b599fb2 197
537a1bf0 198 if (fbi && ptr < smem_len)
5fc404e4
BD		 199 return -ENOMEM;
200
201 break;
202
203 case SM501_MEMF_CRT:
204 ptr = 0;
d0525419
BD		 205
206 /* check to see if we have panel memory allocated
207 * which would put an limit on available memory. */
208
209 fbi = inf->fb[HEAD_PANEL];
210 if (fbi) {
211 par = fbi->par;
212 end = par->screen.k_addr ? par->screen.sm_addr : inf->fbmem_len;
213 } else
214 end = inf->fbmem_len;
215
216 if ((ptr + size) > end)
217 return -ENOMEM;
218
5fc404e4
BD		 219 break;
220
221 case SM501_MEMF_ACCEL:
d0525419 222 fbi = inf->fb[HEAD_CRT];
537a1bf0 223 ptr = fbi ? smem_len : 0;
9b599fb2 224
d0525419
BD		 225 fbi = inf->fb[HEAD_PANEL];
226 if (fbi) {
227 par = fbi->par;
228 end = par->screen.sm_addr;
229 } else
9b599fb2 230 end = inf->fbmem_len;
5fc404e4 231
9b599fb2 232 if ((ptr + size) > end)
5fc404e4 233 return -ENOMEM;
9b599fb2 234
5fc404e4
BD		 235 break;
236
237 default:
238 return -EINVAL;
239 }
240
241 mem->size = size;
242 mem->sm_addr = ptr;
243 mem->k_addr = inf->fbmem + ptr;
244
245 dev_dbg(inf->dev, "%s: result %08lx, %p - %u, %zd\n",
246 __func__, mem->sm_addr, mem->k_addr, why, size);
247
248 return 0;
249}
250
251/* sm501fb_ps_to_hz
252 *
253 * Converts a period in picoseconds to Hz.
254 *
255 * Note, we try to keep this in Hz to minimise rounding with
256 * the limited PLL settings on the SM501.
257*/
258
259static unsigned long sm501fb_ps_to_hz(unsigned long psvalue)
260{
261 unsigned long long numerator=1000000000000ULL;
262
263 /* 10^12 / picosecond period gives frequency in Hz */
264 do_div(numerator, psvalue);
265 return (unsigned long)numerator;
266}
267
25985edc 268/* sm501fb_hz_to_ps is identical to the opposite transform */
5fc404e4
BD		 269
270#define sm501fb_hz_to_ps(x) sm501fb_ps_to_hz(x)
271
272/* sm501fb_setup_gamma
273 *
274 * Programs a linear 1.0 gamma ramp in case the gamma
275 * correction is enabled without programming anything else.
276*/
277
278static void sm501fb_setup_gamma(struct sm501fb_info *fbi,
279 unsigned long palette)
280{
281 unsigned long value = 0;
282 int offset;
283
284 /* set gamma values */
285 for (offset = 0; offset < 256 * 4; offset += 4) {
bf5f0019 286 smc501_writel(value, fbi->regs + palette + offset);
5fc404e4
BD		 287 value += 0x010101; /* Advance RGB by 1,1,1.*/
288 }
289}
290
291/* sm501fb_check_var
292 *
293 * check common variables for both panel and crt
294*/
295
296static int sm501fb_check_var(struct fb_var_screeninfo *var,
297 struct fb_info *info)
298{
299 struct sm501fb_par *par = info->par;
300 struct sm501fb_info *sm = par->info;
301 unsigned long tmp;
302
303 /* check we can fit these values into the registers */
304
7e533705 305 if (var->hsync_len > 255 || var->vsync_len > 63)
5fc404e4
BD		 306 return -EINVAL;
307
7e533705
VS		 308 /* hdisplay end and hsync start */
309 if ((var->xres + var->right_margin) > 4096)
5fc404e4
BD		 310 return -EINVAL;
311
7e533705 312 /* vdisplay end and vsync start */
5fc404e4
BD		 313 if ((var->yres + var->lower_margin) > 2048)
314 return -EINVAL;
315
316 /* hard limits of device */
317
318 if (h_total(var) > 4096 || v_total(var) > 2048)
319 return -EINVAL;
320
321 /* check our line length is going to be 128 bit aligned */
322
323 tmp = (var->xres * var->bits_per_pixel) / 8;
324 if ((tmp & 15) != 0)
325 return -EINVAL;
326
327 /* check the virtual size */
328
329 if (var->xres_virtual > 4096 || var->yres_virtual > 2048)
330 return -EINVAL;
331
332 /* can cope with 8,16 or 32bpp */
333
334 if (var->bits_per_pixel <= 8)
335 var->bits_per_pixel = 8;
336 else if (var->bits_per_pixel <= 16)
337 var->bits_per_pixel = 16;
338 else if (var->bits_per_pixel == 24)
339 var->bits_per_pixel = 32;
340
341 /* set r/g/b positions and validate bpp */
342 switch(var->bits_per_pixel) {
343 case 8:
344 var->red.length = var->bits_per_pixel;
345 var->red.offset = 0;
346 var->green.length = var->bits_per_pixel;
347 var->green.offset = 0;
348 var->blue.length = var->bits_per_pixel;
349 var->blue.offset = 0;
350 var->transp.length = 0;
19d06eff 351 var->transp.offset = 0;
5fc404e4
BD		 352
353 break;
354
355 case 16:
356 if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
5fc404e4
BD		 357 var->blue.offset = 11;
358 var->green.offset = 5;
359 var->red.offset = 0;
fedbb362
VS		 360 } else {
361 var->red.offset = 11;
362 var->green.offset = 5;
363 var->blue.offset = 0;
5fc404e4 364 }
19d06eff 365 var->transp.offset = 0;
5fc404e4
BD		 366
367 var->red.length = 5;
368 var->green.length = 6;
369 var->blue.length = 5;
370 var->transp.length = 0;
371 break;
372
373 case 32:
374 if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
375 var->transp.offset = 0;
376 var->red.offset = 8;
377 var->green.offset = 16;
378 var->blue.offset = 24;
379 } else {
380 var->transp.offset = 24;
381 var->red.offset = 16;
382 var->green.offset = 8;
383 var->blue.offset = 0;
384 }
385
386 var->red.length = 8;
387 var->green.length = 8;
388 var->blue.length = 8;
389 var->transp.length = 0;
390 break;
391
392 default:
393 return -EINVAL;
394 }
395
396 return 0;
397}
398
399/*
400 * sm501fb_check_var_crt():
401 *
402 * check the parameters for the CRT head, and either bring them
403 * back into range, or return -EINVAL.
404*/
405
406static int sm501fb_check_var_crt(struct fb_var_screeninfo *var,
407 struct fb_info *info)
408{
409 return sm501fb_check_var(var, info);
410}
411
412/* sm501fb_check_var_pnl():
413 *
414 * check the parameters for the CRT head, and either bring them
415 * back into range, or return -EINVAL.
416*/
417
418static int sm501fb_check_var_pnl(struct fb_var_screeninfo *var,
419 struct fb_info *info)
420{
421 return sm501fb_check_var(var, info);
422}
423
424/* sm501fb_set_par_common
425 *
426 * set common registers for framebuffers
427*/
428
429static int sm501fb_set_par_common(struct fb_info *info,
430 struct fb_var_screeninfo *var)
431{
432 struct sm501fb_par *par = info->par;
433 struct sm501fb_info *fbi = par->info;
434 unsigned long pixclock; /* pixelclock in Hz */
3ad2f3fb 435 unsigned long sm501pixclock; /* pixelclock the 501 can achieve in Hz */
5fc404e4
BD		 436 unsigned int mem_type;
437 unsigned int clock_type;
438 unsigned int head_addr;
537a1bf0 439 unsigned int smem_len;
5fc404e4
BD		 440
441 dev_dbg(fbi->dev, "%s: %dx%d, bpp = %d, virtual %dx%d\n",
442 __func__, var->xres, var->yres, var->bits_per_pixel,
443 var->xres_virtual, var->yres_virtual);
444
445 switch (par->head) {
446 case HEAD_CRT:
447 mem_type = SM501_MEMF_CRT;
448 clock_type = SM501_CLOCK_V2XCLK;
449 head_addr = SM501_DC_CRT_FB_ADDR;
450 break;
451
452 case HEAD_PANEL:
453 mem_type = SM501_MEMF_PANEL;
454 clock_type = SM501_CLOCK_P2XCLK;
455 head_addr = SM501_DC_PANEL_FB_ADDR;
456 break;
457
458 default:
459 mem_type = 0; /* stop compiler warnings */
460 head_addr = 0;
461 clock_type = 0;
462 }
463
464 switch (var->bits_per_pixel) {
465 case 8:
466 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
467 break;
468
469 case 16:
5619d823 470 info->fix.visual = FB_VISUAL_TRUECOLOR;
5fc404e4
BD		 471 break;
472
473 case 32:
474 info->fix.visual = FB_VISUAL_TRUECOLOR;
475 break;
476 }
477
478 /* allocate fb memory within 501 */
479 info->fix.line_length = (var->xres_virtual * var->bits_per_pixel)/8;
537a1bf0 480 smem_len = info->fix.line_length * var->yres_virtual;
5fc404e4
BD		 481
482 dev_dbg(fbi->dev, "%s: line length = %u\n", __func__,
483 info->fix.line_length);
484
537a1bf0 485 if (sm501_alloc_mem(fbi, &par->screen, mem_type, smem_len, smem_len)) {
5fc404e4
BD		 486 dev_err(fbi->dev, "no memory available\n");
487 return -ENOMEM;
488 }
489
537a1bf0 490 mutex_lock(&info->mm_lock);
5fc404e4 491 info->fix.smem_start = fbi->fbmem_res->start + par->screen.sm_addr;
537a1bf0
KH		 492 info->fix.smem_len = smem_len;
493 mutex_unlock(&info->mm_lock);
5fc404e4
BD		 494
495 info->screen_base = fbi->fbmem + par->screen.sm_addr;
496 info->screen_size = info->fix.smem_len;
497
498 /* set start of framebuffer to the screen */
499
bf5f0019
HS		 500 smc501_writel(par->screen.sm_addr | SM501_ADDR_FLIP,
501 fbi->regs + head_addr);
5fc404e4
BD		 502
503 /* program CRT clock */
504
505 pixclock = sm501fb_ps_to_hz(var->pixclock);
506
507 sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
508 pixclock);
509
510 /* update fb layer with actual clock used */
511 var->pixclock = sm501fb_hz_to_ps(sm501pixclock);
512
513 dev_dbg(fbi->dev, "%s: pixclock(ps) = %u, pixclock(Hz) = %lu, "
514 "sm501pixclock = %lu, error = %ld%%\n",
515 __func__, var->pixclock, pixclock, sm501pixclock,
516 ((pixclock - sm501pixclock)*100)/pixclock);
517
518 return 0;
519}
520
521/* sm501fb_set_par_geometry
522 *
523 * set the geometry registers for specified framebuffer.
524*/
525
526static void sm501fb_set_par_geometry(struct fb_info *info,
527 struct fb_var_screeninfo *var)
528{
529 struct sm501fb_par *par = info->par;
530 struct sm501fb_info *fbi = par->info;
531 void __iomem *base = fbi->regs;
532 unsigned long reg;
533
534 if (par->head == HEAD_CRT)
535 base += SM501_DC_CRT_H_TOT;
536 else
537 base += SM501_DC_PANEL_H_TOT;
538
539 /* set framebuffer width and display width */
540
541 reg = info->fix.line_length;
542 reg |= ((var->xres * var->bits_per_pixel)/8) << 16;
543
bf5f0019 544 smc501_writel(reg, fbi->regs + (par->head == HEAD_CRT ?
5fc404e4
BD		 545 SM501_DC_CRT_FB_OFFSET : SM501_DC_PANEL_FB_OFFSET));
546
547 /* program horizontal total */
548
549 reg = (h_total(var) - 1) << 16;
550 reg |= (var->xres - 1);
551
bf5f0019 552 smc501_writel(reg, base + SM501_OFF_DC_H_TOT);
5fc404e4
BD		 553
554 /* program horizontal sync */
555
556 reg = var->hsync_len << 16;
557 reg |= var->xres + var->right_margin - 1;
558
bf5f0019 559 smc501_writel(reg, base + SM501_OFF_DC_H_SYNC);
5fc404e4
BD		 560
561 /* program vertical total */
562
563 reg = (v_total(var) - 1) << 16;
564 reg |= (var->yres - 1);
565
bf5f0019 566 smc501_writel(reg, base + SM501_OFF_DC_V_TOT);
5fc404e4
BD		 567
568 /* program vertical sync */
569 reg = var->vsync_len << 16;
570 reg |= var->yres + var->lower_margin - 1;
571
bf5f0019 572 smc501_writel(reg, base + SM501_OFF_DC_V_SYNC);
5fc404e4
BD		 573}
574
575/* sm501fb_pan_crt
576 *
577 * pan the CRT display output within an virtual framebuffer
578*/
579
580static int sm501fb_pan_crt(struct fb_var_screeninfo *var,
581 struct fb_info *info)
582{
583 struct sm501fb_par *par = info->par;
584 struct sm501fb_info *fbi = par->info;
0aa76b0c 585 unsigned int bytes_pixel = info->var.bits_per_pixel / 8;
5fc404e4
BD		 586 unsigned long reg;
587 unsigned long xoffs;
588
589 xoffs = var->xoffset * bytes_pixel;
590
bf5f0019 591 reg = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 592
593 reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK;
594 reg |= ((xoffs & 15) / bytes_pixel) << 4;
bf5f0019 595 smc501_writel(reg, fbi->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 596
597 reg = (par->screen.sm_addr + xoffs +
598 var->yoffset * info->fix.line_length);
bf5f0019 599 smc501_writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR);
5fc404e4
BD		 600
601 sm501fb_sync_regs(fbi);
602 return 0;
603}
604
605/* sm501fb_pan_pnl
606 *
607 * pan the panel display output within an virtual framebuffer
608*/
609
610static int sm501fb_pan_pnl(struct fb_var_screeninfo *var,
611 struct fb_info *info)
612{
613 struct sm501fb_par *par = info->par;
614 struct sm501fb_info *fbi = par->info;
615 unsigned long reg;
616
0aa76b0c 617 reg = var->xoffset | (info->var.xres_virtual << 16);
bf5f0019 618 smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH);
5fc404e4 619
0aa76b0c 620 reg = var->yoffset | (info->var.yres_virtual << 16);
bf5f0019 621 smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT);
5fc404e4
BD		 622
623 sm501fb_sync_regs(fbi);
624 return 0;
625}
626
627/* sm501fb_set_par_crt
628 *
629 * Set the CRT video mode from the fb_info structure
630*/
631
632static int sm501fb_set_par_crt(struct fb_info *info)
633{
634 struct sm501fb_par *par = info->par;
635 struct sm501fb_info *fbi = par->info;
636 struct fb_var_screeninfo *var = &info->var;
637 unsigned long control; /* control register */
638 int ret;
639
640 /* activate new configuration */
641
642 dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
643
644 /* enable CRT DAC - note 0 is on!*/
645 sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
646
bf5f0019 647 control = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 648
649 control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK |
650 SM501_DC_CRT_CONTROL_GAMMA |
651 SM501_DC_CRT_CONTROL_BLANK |
652 SM501_DC_CRT_CONTROL_SEL |
653 SM501_DC_CRT_CONTROL_CP |
654 SM501_DC_CRT_CONTROL_TVP);
655
656 /* set the sync polarities before we check data source */
657
658 if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
659 control |= SM501_DC_CRT_CONTROL_HSP;
660
661 if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
662 control |= SM501_DC_CRT_CONTROL_VSP;
663
664 if ((control & SM501_DC_CRT_CONTROL_SEL) == 0) {
665 /* the head is displaying panel data... */
666
537a1bf0
KH		 667 sm501_alloc_mem(fbi, &par->screen, SM501_MEMF_CRT, 0,
668 info->fix.smem_len);
5fc404e4
BD		 669 goto out_update;
670 }
671
672 ret = sm501fb_set_par_common(info, var);
673 if (ret) {
674 dev_err(fbi->dev, "failed to set common parameters\n");
675 return ret;
676 }
677
678 sm501fb_pan_crt(var, info);
679 sm501fb_set_par_geometry(info, var);
680
681 control |= SM501_FIFO_3; /* fill if >3 free slots */
682
683 switch(var->bits_per_pixel) {
684 case 8:
685 control |= SM501_DC_CRT_CONTROL_8BPP;
686 break;
687
688 case 16:
689 control |= SM501_DC_CRT_CONTROL_16BPP;
5619d823 690 sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
5fc404e4
BD		 691 break;
692
693 case 32:
694 control |= SM501_DC_CRT_CONTROL_32BPP;
695 sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
696 break;
697
698 default:
699 BUG();
700 }
701
702 control |= SM501_DC_CRT_CONTROL_SEL; /* CRT displays CRT data */
703 control |= SM501_DC_CRT_CONTROL_TE; /* enable CRT timing */
704 control |= SM501_DC_CRT_CONTROL_ENABLE; /* enable CRT plane */
705
706 out_update:
707 dev_dbg(fbi->dev, "new control is %08lx\n", control);
708
bf5f0019 709 smc501_writel(control, fbi->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 710 sm501fb_sync_regs(fbi);
711
712 return 0;
713}
714
715static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
716{
717 unsigned long control;
718 void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL;
dfcffa46 719 struct sm501_platdata_fbsub *pd = fbi->pdata->fb_pnl;
5fc404e4 720
bf5f0019 721 control = smc501_readl(ctrl_reg);
5fc404e4
BD		 722
723 if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) {
724 /* enable panel power */
725
726 control |= SM501_DC_PANEL_CONTROL_VDD; /* FPVDDEN */
bf5f0019 727 smc501_writel(control, ctrl_reg);
5fc404e4
BD		 728 sm501fb_sync_regs(fbi);
729 mdelay(10);
730
731 control |= SM501_DC_PANEL_CONTROL_DATA; /* DATA */
bf5f0019 732 smc501_writel(control, ctrl_reg);
5fc404e4
BD		 733 sm501fb_sync_regs(fbi);
734 mdelay(10);
735
206c5d69
BD		 736 /* VBIASEN */
737
cdc83ae2 738 if (!(pd->flags & SM501FB_FLAG_PANEL_NO_VBIASEN)) {
206c5d69
BD		 739 if (pd->flags & SM501FB_FLAG_PANEL_INV_VBIASEN)
740 control &= ~SM501_DC_PANEL_CONTROL_BIAS;
741 else
742 control |= SM501_DC_PANEL_CONTROL_BIAS;
743
bf5f0019 744 smc501_writel(control, ctrl_reg);
dfcffa46
MD		 745 sm501fb_sync_regs(fbi);
746 mdelay(10);
747 }
5fc404e4 748
cdc83ae2 749 if (!(pd->flags & SM501FB_FLAG_PANEL_NO_FPEN)) {
206c5d69
BD		 750 if (pd->flags & SM501FB_FLAG_PANEL_INV_FPEN)
751 control &= ~SM501_DC_PANEL_CONTROL_FPEN;
752 else
753 control |= SM501_DC_PANEL_CONTROL_FPEN;
754
bf5f0019 755 smc501_writel(control, ctrl_reg);
dfcffa46
MD		 756 sm501fb_sync_regs(fbi);
757 mdelay(10);
758 }
5fc404e4
BD		 759 } else if (!to && (control & SM501_DC_PANEL_CONTROL_VDD) != 0) {
760 /* disable panel power */
cdc83ae2 761 if (!(pd->flags & SM501FB_FLAG_PANEL_NO_FPEN)) {
206c5d69
BD		 762 if (pd->flags & SM501FB_FLAG_PANEL_INV_FPEN)
763 control |= SM501_DC_PANEL_CONTROL_FPEN;
764 else
765 control &= ~SM501_DC_PANEL_CONTROL_FPEN;
766
bf5f0019 767 smc501_writel(control, ctrl_reg);
dfcffa46
MD		 768 sm501fb_sync_regs(fbi);
769 mdelay(10);
770 }
5fc404e4 771
cdc83ae2 772 if (!(pd->flags & SM501FB_FLAG_PANEL_NO_VBIASEN)) {
206c5d69
BD		 773 if (pd->flags & SM501FB_FLAG_PANEL_INV_VBIASEN)
774 control |= SM501_DC_PANEL_CONTROL_BIAS;
775 else
776 control &= ~SM501_DC_PANEL_CONTROL_BIAS;
777
bf5f0019 778 smc501_writel(control, ctrl_reg);
dfcffa46
MD		 779 sm501fb_sync_regs(fbi);
780 mdelay(10);
781 }
5fc404e4
BD		 782
783 control &= ~SM501_DC_PANEL_CONTROL_DATA;
bf5f0019 784 smc501_writel(control, ctrl_reg);
5fc404e4
BD		 785 sm501fb_sync_regs(fbi);
786 mdelay(10);
787
788 control &= ~SM501_DC_PANEL_CONTROL_VDD;
bf5f0019 789 smc501_writel(control, ctrl_reg);
5fc404e4
BD		 790 sm501fb_sync_regs(fbi);
791 mdelay(10);
792 }
793
794 sm501fb_sync_regs(fbi);
795}
796
797/* sm501fb_set_par_pnl
798 *
799 * Set the panel video mode from the fb_info structure
800*/
801
802static int sm501fb_set_par_pnl(struct fb_info *info)
803{
804 struct sm501fb_par *par = info->par;
805 struct sm501fb_info *fbi = par->info;
806 struct fb_var_screeninfo *var = &info->var;
807 unsigned long control;
808 unsigned long reg;
809 int ret;
810
811 dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
812
813 /* activate this new configuration */
814
815 ret = sm501fb_set_par_common(info, var);
816 if (ret)
817 return ret;
818
819 sm501fb_pan_pnl(var, info);
820 sm501fb_set_par_geometry(info, var);
821
822 /* update control register */
823
bf5f0019 824 control = smc501_readl(fbi->regs + SM501_DC_PANEL_CONTROL);
5fc404e4
BD		 825 control &= (SM501_DC_PANEL_CONTROL_GAMMA |
826 SM501_DC_PANEL_CONTROL_VDD |
827 SM501_DC_PANEL_CONTROL_DATA |
828 SM501_DC_PANEL_CONTROL_BIAS |
829 SM501_DC_PANEL_CONTROL_FPEN |
830 SM501_DC_PANEL_CONTROL_CP |
831 SM501_DC_PANEL_CONTROL_CK |
832 SM501_DC_PANEL_CONTROL_HP |
833 SM501_DC_PANEL_CONTROL_VP |
834 SM501_DC_PANEL_CONTROL_HPD |
835 SM501_DC_PANEL_CONTROL_VPD);
836
837 control |= SM501_FIFO_3; /* fill if >3 free slots */
838
839 switch(var->bits_per_pixel) {
840 case 8:
841 control |= SM501_DC_PANEL_CONTROL_8BPP;
842 break;
843
844 case 16:
845 control |= SM501_DC_PANEL_CONTROL_16BPP;
5619d823 846 sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
5fc404e4
BD		 847 break;
848
849 case 32:
850 control |= SM501_DC_PANEL_CONTROL_32BPP;
851 sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
852 break;
853
854 default:
855 BUG();
856 }
857
bf5f0019 858 smc501_writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL);
5fc404e4
BD		 859
860 /* panel plane top left and bottom right location */
861
bf5f0019 862 smc501_writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC);
5fc404e4
BD		 863
864 reg = var->xres - 1;
865 reg |= (var->yres - 1) << 16;
866
bf5f0019 867 smc501_writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC);
5fc404e4
BD		 868
869 /* program panel control register */
870
871 control |= SM501_DC_PANEL_CONTROL_TE; /* enable PANEL timing */
872 control |= SM501_DC_PANEL_CONTROL_EN; /* enable PANEL gfx plane */
873
874 if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
875 control |= SM501_DC_PANEL_CONTROL_HSP;
876
877 if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
878 control |= SM501_DC_PANEL_CONTROL_VSP;
879
bf5f0019 880 smc501_writel(control, fbi->regs + SM501_DC_PANEL_CONTROL);
5fc404e4
BD		 881 sm501fb_sync_regs(fbi);
882
eb78f9b3
BD		 883 /* ensure the panel interface is not tristated at this point */
884
885 sm501_modify_reg(fbi->dev->parent, SM501_SYSTEM_CONTROL,
886 0, SM501_SYSCTRL_PANEL_TRISTATE);
887
5fc404e4
BD		 888 /* power the panel up */
889 sm501fb_panel_power(fbi, 1);
890 return 0;
891}
892
893
894/* chan_to_field
895 *
896 * convert a colour value into a field position
897 *
898 * from pxafb.c
899*/
900
901static inline unsigned int chan_to_field(unsigned int chan,
902 struct fb_bitfield *bf)
903{
904 chan &= 0xffff;
905 chan >>= 16 - bf->length;
906 return chan << bf->offset;
907}
908
909/* sm501fb_setcolreg
910 *
911 * set the colour mapping for modes that support palettised data
912*/
913
914static int sm501fb_setcolreg(unsigned regno,
915 unsigned red, unsigned green, unsigned blue,
916 unsigned transp, struct fb_info *info)
917{
918 struct sm501fb_par *par = info->par;
919 struct sm501fb_info *fbi = par->info;
920 void __iomem *base = fbi->regs;
921 unsigned int val;
922
923 if (par->head == HEAD_CRT)
924 base += SM501_DC_CRT_PALETTE;
925 else
926 base += SM501_DC_PANEL_PALETTE;
927
928 switch (info->fix.visual) {
929 case FB_VISUAL_TRUECOLOR:
930 /* true-colour, use pseuo-palette */
931
932 if (regno < 16) {
933 u32 *pal = par->pseudo_palette;
934
935 val = chan_to_field(red, &info->var.red);
936 val |= chan_to_field(green, &info->var.green);
937 val |= chan_to_field(blue, &info->var.blue);
938
939 pal[regno] = val;
940 }
941 break;
942
943 case FB_VISUAL_PSEUDOCOLOR:
944 if (regno < 256) {
945 val = (red >> 8) << 16;
946 val |= (green >> 8) << 8;
947 val |= blue >> 8;
948
bf5f0019 949 smc501_writel(val, base + (regno * 4));
5fc404e4
BD		 950 }
951
952 break;
953
954 default:
955 return 1; /* unknown type */
956 }
957
958 return 0;
959}
960
961/* sm501fb_blank_pnl
962 *
963 * Blank or un-blank the panel interface
964*/
965
966static int sm501fb_blank_pnl(int blank_mode, struct fb_info *info)
967{
968 struct sm501fb_par *par = info->par;
969 struct sm501fb_info *fbi = par->info;
970
971 dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
972
973 switch (blank_mode) {
974 case FB_BLANK_POWERDOWN:
975 sm501fb_panel_power(fbi, 0);
976 break;
977
978 case FB_BLANK_UNBLANK:
979 sm501fb_panel_power(fbi, 1);
980 break;
981
982 case FB_BLANK_NORMAL:
983 case FB_BLANK_VSYNC_SUSPEND:
984 case FB_BLANK_HSYNC_SUSPEND:
985 default:
986 return 1;
987 }
988
989 return 0;
990}
991
992/* sm501fb_blank_crt
993 *
994 * Blank or un-blank the crt interface
995*/
996
997static int sm501fb_blank_crt(int blank_mode, struct fb_info *info)
998{
999 struct sm501fb_par *par = info->par;
1000 struct sm501fb_info *fbi = par->info;
1001 unsigned long ctrl;
1002
1003 dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
1004
bf5f0019 1005 ctrl = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 1006
1007 switch (blank_mode) {
1008 case FB_BLANK_POWERDOWN:
1009 ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
1010 sm501_misc_control(fbi->dev->parent, SM501_MISC_DAC_POWER, 0);
1011
1012 case FB_BLANK_NORMAL:
1013 ctrl |= SM501_DC_CRT_CONTROL_BLANK;
1014 break;
1015
1016 case FB_BLANK_UNBLANK:
1017 ctrl &= ~SM501_DC_CRT_CONTROL_BLANK;
1018 ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
1019 sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
1020 break;
1021
1022 case FB_BLANK_VSYNC_SUSPEND:
1023 case FB_BLANK_HSYNC_SUSPEND:
1024 default:
1025 return 1;
1026
1027 }
1028
bf5f0019 1029 smc501_writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 1030 sm501fb_sync_regs(fbi);
1031
1032 return 0;
1033}
1034
1035/* sm501fb_cursor
1036 *
1037 * set or change the hardware cursor parameters
1038*/
1039
9540f75b 1040static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
5fc404e4
BD		 1041{
1042 struct sm501fb_par *par = info->par;
1043 struct sm501fb_info *fbi = par->info;
1044 void __iomem *base = fbi->regs;
1045 unsigned long hwc_addr;
1046 unsigned long fg, bg;
1047
1048 dev_dbg(fbi->dev, "%s(%p,%p)\n", __func__, info, cursor);
1049
1050 if (par->head == HEAD_CRT)
1051 base += SM501_DC_CRT_HWC_BASE;
1052 else
1053 base += SM501_DC_PANEL_HWC_BASE;
1054
1055 /* check not being asked to exceed capabilities */
1056
1057 if (cursor->image.width > 64)
1058 return -EINVAL;
1059
1060 if (cursor->image.height > 64)
1061 return -EINVAL;
1062
1063 if (cursor->image.depth > 1)
1064 return -EINVAL;
1065
bf5f0019 1066 hwc_addr = smc501_readl(base + SM501_OFF_HWC_ADDR);
5fc404e4
BD		 1067
1068 if (cursor->enable)
bf5f0019
HS		 1069 smc501_writel(hwc_addr | SM501_HWC_EN,
1070 base + SM501_OFF_HWC_ADDR);
5fc404e4 1071 else
bf5f0019
HS		 1072 smc501_writel(hwc_addr & ~SM501_HWC_EN,
1073 base + SM501_OFF_HWC_ADDR);
5fc404e4
BD		 1074
1075 /* set data */
1076 if (cursor->set & FB_CUR_SETPOS) {
1077 unsigned int x = cursor->image.dx;
1078 unsigned int y = cursor->image.dy;
1079
1080 if (x >= 2048 || y >= 2048 )
1081 return -EINVAL;
1082
1083 dev_dbg(fbi->dev, "set position %d,%d\n", x, y);
1084
1085 //y += cursor->image.height;
1086
bf5f0019 1087 smc501_writel(x | (y << 16), base + SM501_OFF_HWC_LOC);
5fc404e4
BD		 1088 }
1089
1090 if (cursor->set & FB_CUR_SETCMAP) {
1091 unsigned int bg_col = cursor->image.bg_color;
1092 unsigned int fg_col = cursor->image.fg_color;
1093
1094 dev_dbg(fbi->dev, "%s: update cmap (%08x,%08x)\n",
1095 __func__, bg_col, fg_col);
1096
1097 bg = ((info->cmap.red[bg_col] & 0xF8) << 8) |
1098 ((info->cmap.green[bg_col] & 0xFC) << 3) |
1099 ((info->cmap.blue[bg_col] & 0xF8) >> 3);
1100
1101 fg = ((info->cmap.red[fg_col] & 0xF8) << 8) |
1102 ((info->cmap.green[fg_col] & 0xFC) << 3) |
1103 ((info->cmap.blue[fg_col] & 0xF8) >> 3);
1104
be3478dd 1105 dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg);
5fc404e4 1106
bf5f0019
HS		 1107 smc501_writel(bg, base + SM501_OFF_HWC_COLOR_1_2);
1108 smc501_writel(fg, base + SM501_OFF_HWC_COLOR_3);
5fc404e4
BD		 1109 }
1110
1111 if (cursor->set & FB_CUR_SETSIZE ||
1112 cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
1113 /* SM501 cursor is a two bpp 64x64 bitmap this routine
1114 * clears it to transparent then combines the cursor
1115 * shape plane with the colour plane to set the
1116 * cursor */
1117 int x, y;
1118 const unsigned char *pcol = cursor->image.data;
1119 const unsigned char *pmsk = cursor->mask;
1120 void __iomem *dst = par->cursor.k_addr;
1121 unsigned char dcol = 0;
1122 unsigned char dmsk = 0;
1123 unsigned int op;
1124
1125 dev_dbg(fbi->dev, "%s: setting shape (%d,%d)\n",
1126 __func__, cursor->image.width, cursor->image.height);
1127
1128 for (op = 0; op < (64*64*2)/8; op+=4)
bf5f0019 1129 smc501_writel(0x0, dst + op);
5fc404e4
BD		 1130
1131 for (y = 0; y < cursor->image.height; y++) {
1132 for (x = 0; x < cursor->image.width; x++) {
1133 if ((x % 8) == 0) {
1134 dcol = *pcol++;
1135 dmsk = *pmsk++;
1136 } else {
1137 dcol >>= 1;
1138 dmsk >>= 1;
1139 }
1140
1141 if (dmsk & 1) {
1142 op = (dcol & 1) ? 1 : 3;
1143 op <<= ((x % 4) * 2);
1144
1145 op |= readb(dst + (x / 4));
1146 writeb(op, dst + (x / 4));
1147 }
1148 }
1149 dst += (64*2)/8;
1150 }
1151 }
1152
1153 sm501fb_sync_regs(fbi); /* ensure cursor data flushed */
1154 return 0;
1155}
1156
1157/* sm501fb_crtsrc_show
1158 *
1159 * device attribute code to show where the crt output is sourced from
1160*/
1161
1162static ssize_t sm501fb_crtsrc_show(struct device *dev,
1163 struct device_attribute *attr, char *buf)
1164{
1165 struct sm501fb_info *info = dev_get_drvdata(dev);
1166 unsigned long ctrl;
1167
bf5f0019 1168 ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 1169 ctrl &= SM501_DC_CRT_CONTROL_SEL;
1170
1171 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl ? "crt" : "panel");
1172}
1173
1174/* sm501fb_crtsrc_show
1175 *
1176 * device attribute code to set where the crt output is sourced from
1177*/
1178
1179static ssize_t sm501fb_crtsrc_store(struct device *dev,
1180 struct device_attribute *attr,
1181 const char *buf, size_t len)
1182{
1183 struct sm501fb_info *info = dev_get_drvdata(dev);
1184 enum sm501_controller head;
1185 unsigned long ctrl;
1186
1187 if (len < 1)
1188 return -EINVAL;
1189
1f2b69f9 1190 if (strnicmp(buf, "crt", 3) == 0)
5fc404e4 1191 head = HEAD_CRT;
1f2b69f9 1192 else if (strnicmp(buf, "panel", 5) == 0)
5fc404e4
BD		 1193 head = HEAD_PANEL;
1194 else
1195 return -EINVAL;
1196
1197 dev_info(dev, "setting crt source to head %d\n", head);
1198
bf5f0019 1199 ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 1200
1201 if (head == HEAD_CRT) {
1202 ctrl |= SM501_DC_CRT_CONTROL_SEL;
1203 ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
1204 ctrl |= SM501_DC_CRT_CONTROL_TE;
1205 } else {
1206 ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
1207 ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
1208 ctrl &= ~SM501_DC_CRT_CONTROL_TE;
1209 }
1210
bf5f0019 1211 smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 1212 sm501fb_sync_regs(info);
1213
1f2b69f9 1214 return len;
5fc404e4
BD		 1215}
1216
1217/* Prepare the device_attr for registration with sysfs later */
1218static DEVICE_ATTR(crt_src, 0666, sm501fb_crtsrc_show, sm501fb_crtsrc_store);
1219
1220/* sm501fb_show_regs
1221 *
1222 * show the primary sm501 registers
1223*/
1224static int sm501fb_show_regs(struct sm501fb_info *info, char *ptr,
1225 unsigned int start, unsigned int len)
1226{
1227 void __iomem *mem = info->regs;
1228 char *buf = ptr;
1229 unsigned int reg;
1230
1231 for (reg = start; reg < (len + start); reg += 4)
bf5f0019
HS		 1232 ptr += sprintf(ptr, "%08x = %08x\n", reg,
1233 smc501_readl(mem + reg));
5fc404e4
BD		 1234
1235 return ptr - buf;
1236}
1237
1238/* sm501fb_debug_show_crt
1239 *
1240 * show the crt control and cursor registers
1241*/
1242
1243static ssize_t sm501fb_debug_show_crt(struct device *dev,
1244 struct device_attribute *attr, char *buf)
1245{
1246 struct sm501fb_info *info = dev_get_drvdata(dev);
1247 char *ptr = buf;
1248
1249 ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_CONTROL, 0x40);
1250 ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_HWC_BASE, 0x10);
1251
1252 return ptr - buf;
1253}
1254
1255static DEVICE_ATTR(fbregs_crt, 0444, sm501fb_debug_show_crt, NULL);
1256
1257/* sm501fb_debug_show_pnl
1258 *
1259 * show the panel control and cursor registers
1260*/
1261
1262static ssize_t sm501fb_debug_show_pnl(struct device *dev,
1263 struct device_attribute *attr, char *buf)
1264{
1265 struct sm501fb_info *info = dev_get_drvdata(dev);
1266 char *ptr = buf;
1267
1268 ptr += sm501fb_show_regs(info, ptr, 0x0, 0x40);
1269 ptr += sm501fb_show_regs(info, ptr, SM501_DC_PANEL_HWC_BASE, 0x10);
1270
1271 return ptr - buf;
1272}
1273
1274static DEVICE_ATTR(fbregs_pnl, 0444, sm501fb_debug_show_pnl, NULL);
1275
9265576d
VS		 1276/* acceleration operations */
1277static int sm501fb_sync(struct fb_info *info)
1278{
1279 int count = 1000000;
1280 struct sm501fb_par *par = info->par;
1281 struct sm501fb_info *fbi = par->info;
1282
1283 /* wait for the 2d engine to be ready */
1284 while ((count > 0) &&
bf5f0019 1285 (smc501_readl(fbi->regs + SM501_SYSTEM_CONTROL) &
9265576d
VS		 1286 SM501_SYSCTRL_2D_ENGINE_STATUS) != 0)
1287 count--;
1288
1289 if (count <= 0) {
1290 dev_err(info->dev, "Timeout waiting for 2d engine sync\n");
1291 return 1;
1292 }
1293 return 0;
1294}
1295
1296static void sm501fb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1297{
1298 struct sm501fb_par *par = info->par;
1299 struct sm501fb_info *fbi = par->info;
1300 int width = area->width;
1301 int height = area->height;
1302 int sx = area->sx;
1303 int sy = area->sy;
1304 int dx = area->dx;
1305 int dy = area->dy;
1306 unsigned long rtl = 0;
1307
1308 /* source clip */
1309 if ((sx >= info->var.xres_virtual) ||
1310 (sy >= info->var.yres_virtual))
1311 /* source Area not within virtual screen, skipping */
1312 return;
1313 if ((sx + width) >= info->var.xres_virtual)
1314 width = info->var.xres_virtual - sx - 1;
1315 if ((sy + height) >= info->var.yres_virtual)
1316 height = info->var.yres_virtual - sy - 1;
1317
1318 /* dest clip */
1319 if ((dx >= info->var.xres_virtual) ||
1320 (dy >= info->var.yres_virtual))
1321 /* Destination Area not within virtual screen, skipping */
1322 return;
1323 if ((dx + width) >= info->var.xres_virtual)
1324 width = info->var.xres_virtual - dx - 1;
1325 if ((dy + height) >= info->var.yres_virtual)
1326 height = info->var.yres_virtual - dy - 1;
1327
1328 if ((sx < dx) || (sy < dy)) {
1329 rtl = 1 << 27;
1330 sx += width - 1;
1331 dx += width - 1;
1332 sy += height - 1;
1333 dy += height - 1;
1334 }
1335
1336 if (sm501fb_sync(info))
1337 return;
1338
1339 /* set the base addresses */
bf5f0019
HS		 1340 smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE);
1341 smc501_writel(par->screen.sm_addr,
1342 fbi->regs2d + SM501_2D_DESTINATION_BASE);
9265576d
VS		 1343
1344 /* set the window width */
bf5f0019 1345 smc501_writel((info->var.xres << 16) | info->var.xres,
9265576d
VS		 1346 fbi->regs2d + SM501_2D_WINDOW_WIDTH);
1347
1348 /* set window stride */
bf5f0019 1349 smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual,
9265576d
VS		 1350 fbi->regs2d + SM501_2D_PITCH);
1351
1352 /* set data format */
1353 switch (info->var.bits_per_pixel) {
1354 case 8:
bf5f0019 1355 smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH);
9265576d
VS		 1356 break;
1357 case 16:
bf5f0019 1358 smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH);
9265576d
VS		 1359 break;
1360 case 32:
bf5f0019 1361 smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH);
9265576d
VS		 1362 break;
1363 }
1364
1365 /* 2d compare mask */
bf5f0019 1366 smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK);
9265576d
VS		 1367
1368 /* 2d mask */
bf5f0019 1369 smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK);
9265576d
VS		 1370
1371 /* source and destination x y */
bf5f0019
HS		 1372 smc501_writel((sx << 16) | sy, fbi->regs2d + SM501_2D_SOURCE);
1373 smc501_writel((dx << 16) | dy, fbi->regs2d + SM501_2D_DESTINATION);
9265576d
VS		 1374
1375 /* w/h */
bf5f0019 1376 smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION);
9265576d
VS		 1377
1378 /* do area move */
bf5f0019 1379 smc501_writel(0x800000cc | rtl, fbi->regs2d + SM501_2D_CONTROL);
9265576d
VS		 1380}
1381
1382static void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1383{
1384 struct sm501fb_par *par = info->par;
1385 struct sm501fb_info *fbi = par->info;
1386 int width = rect->width, height = rect->height;
1387
1388 if ((rect->dx >= info->var.xres_virtual) ||
1389 (rect->dy >= info->var.yres_virtual))
1390 /* Rectangle not within virtual screen, skipping */
1391 return;
1392 if ((rect->dx + width) >= info->var.xres_virtual)
1393 width = info->var.xres_virtual - rect->dx - 1;
1394 if ((rect->dy + height) >= info->var.yres_virtual)
1395 height = info->var.yres_virtual - rect->dy - 1;
1396
1397 if (sm501fb_sync(info))
1398 return;
1399
1400 /* set the base addresses */
bf5f0019
HS		 1401 smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE);
1402 smc501_writel(par->screen.sm_addr,
1403 fbi->regs2d + SM501_2D_DESTINATION_BASE);
9265576d
VS		 1404
1405 /* set the window width */
bf5f0019 1406 smc501_writel((info->var.xres << 16) | info->var.xres,
9265576d
VS		 1407 fbi->regs2d + SM501_2D_WINDOW_WIDTH);
1408
1409 /* set window stride */
bf5f0019 1410 smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual,
9265576d
VS		 1411 fbi->regs2d + SM501_2D_PITCH);
1412
1413 /* set data format */
1414 switch (info->var.bits_per_pixel) {
1415 case 8:
bf5f0019 1416 smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH);
9265576d
VS		 1417 break;
1418 case 16:
bf5f0019 1419 smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH);
9265576d
VS		 1420 break;
1421 case 32:
bf5f0019 1422 smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH);
9265576d
VS		 1423 break;
1424 }
1425
1426 /* 2d compare mask */
bf5f0019 1427 smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK);
9265576d
VS		 1428
1429 /* 2d mask */
bf5f0019 1430 smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK);
9265576d
VS		 1431
1432 /* colour */
bf5f0019 1433 smc501_writel(rect->color, fbi->regs2d + SM501_2D_FOREGROUND);
9265576d
VS		 1434
1435 /* x y */
bf5f0019
HS		 1436 smc501_writel((rect->dx << 16) | rect->dy,
1437 fbi->regs2d + SM501_2D_DESTINATION);
9265576d
VS		 1438
1439 /* w/h */
bf5f0019 1440 smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION);
9265576d
VS		 1441
1442 /* do rectangle fill */
bf5f0019 1443 smc501_writel(0x800100cc, fbi->regs2d + SM501_2D_CONTROL);
9265576d
VS		 1444}
1445
5fc404e4
BD		 1446
1447static struct fb_ops sm501fb_ops_crt = {
1448 .owner = THIS_MODULE,
1449 .fb_check_var = sm501fb_check_var_crt,
1450 .fb_set_par = sm501fb_set_par_crt,
1451 .fb_blank = sm501fb_blank_crt,
1452 .fb_setcolreg = sm501fb_setcolreg,
1453 .fb_pan_display = sm501fb_pan_crt,
1454 .fb_cursor = sm501fb_cursor,
9265576d
VS		 1455 .fb_fillrect = sm501fb_fillrect,
1456 .fb_copyarea = sm501fb_copyarea,
5fc404e4 1457 .fb_imageblit = cfb_imageblit,
9265576d 1458 .fb_sync = sm501fb_sync,
5fc404e4
BD		 1459};
1460
1461static struct fb_ops sm501fb_ops_pnl = {
1462 .owner = THIS_MODULE,
1463 .fb_check_var = sm501fb_check_var_pnl,
1464 .fb_set_par = sm501fb_set_par_pnl,
1465 .fb_pan_display = sm501fb_pan_pnl,
1466 .fb_blank = sm501fb_blank_pnl,
1467 .fb_setcolreg = sm501fb_setcolreg,
1468 .fb_cursor = sm501fb_cursor,
9265576d
VS		 1469 .fb_fillrect = sm501fb_fillrect,
1470 .fb_copyarea = sm501fb_copyarea,
5fc404e4 1471 .fb_imageblit = cfb_imageblit,
9265576d 1472 .fb_sync = sm501fb_sync,
5fc404e4
BD		 1473};
1474
5fc404e4
BD		 1475/* sm501_init_cursor
1476 *
1477 * initialise hw cursor parameters
1478*/
1479
9540f75b 1480static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base)
5fc404e4 1481{
9b599fb2
BD		 1482 struct sm501fb_par *par;
1483 struct sm501fb_info *info;
5fc404e4
BD		 1484 int ret;
1485
9b599fb2
BD		 1486 if (fbi == NULL)
1487 return 0;
1488
1489 par = fbi->par;
1490 info = par->info;
1491
5fc404e4
BD		 1492 par->cursor_regs = info->regs + reg_base;
1493
537a1bf0
KH		 1494 ret = sm501_alloc_mem(info, &par->cursor, SM501_MEMF_CURSOR, 1024,
1495 fbi->fix.smem_len);
5fc404e4
BD		 1496 if (ret < 0)
1497 return ret;
1498
1499 /* initialise the colour registers */
1500
bf5f0019
HS		 1501 smc501_writel(par->cursor.sm_addr,
1502 par->cursor_regs + SM501_OFF_HWC_ADDR);
5fc404e4 1503
bf5f0019
HS		 1504 smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC);
1505 smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2);
1506 smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3);
5fc404e4
BD		 1507 sm501fb_sync_regs(info);
1508
1509 return 0;
1510}
1511
1512/* sm501fb_info_start
1513 *
1514 * fills the par structure claiming resources and remapping etc.
1515*/
1516
1517static int sm501fb_start(struct sm501fb_info *info,
1518 struct platform_device *pdev)
1519{
1520 struct resource *res;
9b599fb2 1521 struct device *dev = &pdev->dev;
b1230ee5 1522 int k;
5fc404e4
BD		 1523 int ret;
1524
5fc404e4
BD		 1525 info->irq = ret = platform_get_irq(pdev, 0);
1526 if (ret < 0) {
1527 /* we currently do not use the IRQ */
1528 dev_warn(dev, "no irq for device\n");
1529 }
1530
9265576d
VS		 1531 /* allocate, reserve and remap resources for display
1532 * controller registers */
5fc404e4
BD		 1533 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1534 if (res == NULL) {
1535 dev_err(dev, "no resource definition for registers\n");
1536 ret = -ENOENT;
1537 goto err_release;
1538 }
1539
1540 info->regs_res = request_mem_region(res->start,
d60f6c2b 1541 resource_size(res),
5fc404e4
BD		 1542 pdev->name);
1543
1544 if (info->regs_res == NULL) {
1545 dev_err(dev, "cannot claim registers\n");
1546 ret = -ENXIO;
1547 goto err_release;
1548 }
1549
d60f6c2b 1550 info->regs = ioremap(res->start, resource_size(res));
5fc404e4
BD		 1551 if (info->regs == NULL) {
1552 dev_err(dev, "cannot remap registers\n");
1553 ret = -ENXIO;
1554 goto err_regs_res;
1555 }
1556
9265576d
VS		 1557 /* allocate, reserve and remap resources for 2d
1558 * controller registers */
1559 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1560 if (res == NULL) {
1561 dev_err(dev, "no resource definition for 2d registers\n");
1562 ret = -ENOENT;
1563 goto err_regs_map;
1564 }
1565
1566 info->regs2d_res = request_mem_region(res->start,
1567 resource_size(res),
1568 pdev->name);
1569
1570 if (info->regs2d_res == NULL) {
1571 dev_err(dev, "cannot claim registers\n");
1572 ret = -ENXIO;
1573 goto err_regs_map;
1574 }
1575
1576 info->regs2d = ioremap(res->start, resource_size(res));
1577 if (info->regs2d == NULL) {
1578 dev_err(dev, "cannot remap registers\n");
1579 ret = -ENXIO;
1580 goto err_regs2d_res;
1581 }
1582
5fc404e4
BD		 1583 /* allocate, reserve resources for framebuffer */
1584 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1585 if (res == NULL) {
1586 dev_err(dev, "no memory resource defined\n");
1587 ret = -ENXIO;
9265576d 1588 goto err_regs2d_map;
5fc404e4
BD		 1589 }
1590
1591 info->fbmem_res = request_mem_region(res->start,
d60f6c2b 1592 resource_size(res),
5fc404e4
BD		 1593 pdev->name);
1594 if (info->fbmem_res == NULL) {
1595 dev_err(dev, "cannot claim framebuffer\n");
1596 ret = -ENXIO;
9265576d 1597 goto err_regs2d_map;
5fc404e4
BD		 1598 }
1599
d60f6c2b 1600 info->fbmem = ioremap(res->start, resource_size(res));
5fc404e4
BD		 1601 if (info->fbmem == NULL) {
1602 dev_err(dev, "cannot remap framebuffer\n");
1603 goto err_mem_res;
1604 }
1605
d60f6c2b 1606 info->fbmem_len = resource_size(res);
5fc404e4 1607
b1230ee5
MD		 1608 /* clear framebuffer memory - avoids garbage data on unused fb */
1609 memset(info->fbmem, 0, info->fbmem_len);
1610
1611 /* clear palette ram - undefined at power on */
1612 for (k = 0; k < (256 * 3); k++)
bf5f0019 1613 smc501_writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4));
b1230ee5 1614
5fc404e4
BD		 1615 /* enable display controller */
1616 sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1);
1617
9265576d
VS		 1618 /* enable 2d controller */
1619 sm501_unit_power(dev->parent, SM501_GATE_2D_ENGINE, 1);
5fc404e4 1620
9265576d 1621 /* setup cursors */
5fc404e4
BD		 1622 sm501_init_cursor(info->fb[HEAD_CRT], SM501_DC_CRT_HWC_ADDR);
1623 sm501_init_cursor(info->fb[HEAD_PANEL], SM501_DC_PANEL_HWC_ADDR);
1624
1625 return 0; /* everything is setup */
1626
1627 err_mem_res:
d2f6b7f7
JL		 1628 release_mem_region(info->fbmem_res->start,
1629 resource_size(info->fbmem_res));
5fc404e4 1630
9265576d
VS		 1631 err_regs2d_map:
1632 iounmap(info->regs2d);
1633
1634 err_regs2d_res:
d2f6b7f7
JL		 1635 release_mem_region(info->regs2d_res->start,
1636 resource_size(info->regs2d_res));
9265576d 1637
5fc404e4
BD		 1638 err_regs_map:
1639 iounmap(info->regs);
1640
1641 err_regs_res:
d2f6b7f7
JL		 1642 release_mem_region(info->regs_res->start,
1643 resource_size(info->regs_res));
5fc404e4
BD		 1644
1645 err_release:
1646 return ret;
1647}
1648
1649static void sm501fb_stop(struct sm501fb_info *info)
1650{
1651 /* disable display controller */
1652 sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
1653
1654 iounmap(info->fbmem);
d2f6b7f7
JL		 1655 release_mem_region(info->fbmem_res->start,
1656 resource_size(info->fbmem_res));
5fc404e4 1657
9265576d 1658 iounmap(info->regs2d);
d2f6b7f7
JL		 1659 release_mem_region(info->regs2d_res->start,
1660 resource_size(info->regs2d_res));
9265576d 1661
5fc404e4 1662 iounmap(info->regs);
d2f6b7f7
JL		 1663 release_mem_region(info->regs_res->start,
1664 resource_size(info->regs_res));
5fc404e4
BD		 1665}
1666
48c68c4f 1667static int sm501fb_init_fb(struct fb_info *fb, enum sm501_controller head,
5fc404e4
BD		 1668 const char *fbname)
1669{
1670 struct sm501_platdata_fbsub *pd;
1671 struct sm501fb_par *par = fb->par;
1672 struct sm501fb_info *info = par->info;
1673 unsigned long ctrl;
1674 unsigned int enable;
1675 int ret;
1676
1677 switch (head) {
1678 case HEAD_CRT:
1679 pd = info->pdata->fb_crt;
bf5f0019 1680 ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 1681 enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0;
1682
1683 /* ensure we set the correct source register */
1684 if (info->pdata->fb_route != SM501_FB_CRT_PANEL) {
1685 ctrl |= SM501_DC_CRT_CONTROL_SEL;
bf5f0019 1686 smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 1687 }
1688
1689 break;
1690
1691 case HEAD_PANEL:
1692 pd = info->pdata->fb_pnl;
bf5f0019 1693 ctrl = smc501_readl(info->regs + SM501_DC_PANEL_CONTROL);
5fc404e4
BD		 1694 enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0;
1695 break;
1696
1697 default:
1698 pd = NULL; /* stop compiler warnings */
1699 ctrl = 0;
1700 enable = 0;
1701 BUG();
1702 }
1703
1704 dev_info(info->dev, "fb %s %sabled at start\n",
1705 fbname, enable ? "en" : "dis");
1706
1707 /* check to see if our routing allows this */
1708
1709 if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) {
1710 ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
bf5f0019 1711 smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
5fc404e4
BD		 1712 enable = 0;
1713 }
1714
1715 strlcpy(fb->fix.id, fbname, sizeof(fb->fix.id));
1716
1717 memcpy(&par->ops,
1718 (head == HEAD_CRT) ? &sm501fb_ops_crt : &sm501fb_ops_pnl,
1719 sizeof(struct fb_ops));
1720
25985edc 1721 /* update ops dependent on what we've been passed */
5fc404e4
BD		 1722
1723 if ((pd->flags & SM501FB_FLAG_USE_HWCURSOR) == 0)
1724 par->ops.fb_cursor = NULL;
1725
1726 fb->fbops = &par->ops;
9265576d
VS		 1727 fb->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST |
1728 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
5fc404e4
BD		 1729 FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
1730
4295f9bf
HS		 1731#if defined(CONFIG_OF)
1732#ifdef __BIG_ENDIAN
1733 if (of_get_property(info->dev->parent->of_node, "little-endian", NULL))
1734 fb->flags |= FBINFO_FOREIGN_ENDIAN;
1735#else
1736 if (of_get_property(info->dev->parent->of_node, "big-endian", NULL))
1737 fb->flags |= FBINFO_FOREIGN_ENDIAN;
1738#endif
1739#endif
5fc404e4
BD		 1740 /* fixed data */
1741
1742 fb->fix.type = FB_TYPE_PACKED_PIXELS;
1743 fb->fix.type_aux = 0;
1744 fb->fix.xpanstep = 1;
1745 fb->fix.ypanstep = 1;
1746 fb->fix.ywrapstep = 0;
1747 fb->fix.accel = FB_ACCEL_NONE;
1748
1749 /* screenmode */
1750
1751 fb->var.nonstd = 0;
1752 fb->var.activate = FB_ACTIVATE_NOW;
1753 fb->var.accel_flags = 0;
1754 fb->var.vmode = FB_VMODE_NONINTERLACED;
1755 fb->var.bits_per_pixel = 16;
1756
e6a04980
HS		 1757 if (info->edid_data) {
1758 /* Now build modedb from EDID */
1759 fb_edid_to_monspecs(info->edid_data, &fb->monspecs);
1760 fb_videomode_to_modelist(fb->monspecs.modedb,
1761 fb->monspecs.modedb_len,
1762 &fb->modelist);
1763 }
1764
5fc404e4
BD		 1765 if (enable && (pd->flags & SM501FB_FLAG_USE_INIT_MODE) && 0) {
1766 /* TODO read the mode from the current display */
5fc404e4
BD		 1767 } else {
1768 if (pd->def_mode) {
1769 dev_info(info->dev, "using supplied mode\n");
1770 fb_videomode_to_var(&fb->var, pd->def_mode);
1771
1772 fb->var.bits_per_pixel = pd->def_bpp ? pd->def_bpp : 8;
1773 fb->var.xres_virtual = fb->var.xres;
1774 fb->var.yres_virtual = fb->var.yres;
1775 } else {
4295f9bf 1776 if (info->edid_data) {
e6a04980
HS		 1777 ret = fb_find_mode(&fb->var, fb, fb_mode,
1778 fb->monspecs.modedb,
1779 fb->monspecs.modedb_len,
1780 &sm501_default_mode, default_bpp);
4295f9bf
HS		 1781 /* edid_data is no longer needed, free it */
1782 kfree(info->edid_data);
1783 } else {
e6a04980 1784 ret = fb_find_mode(&fb->var, fb,
5fc404e4 1785 NULL, NULL, 0, NULL, 8);
4295f9bf 1786 }
5fc404e4 1787
e6a04980
HS		 1788 switch (ret) {
1789 case 1:
1790 dev_info(info->dev, "using mode specified in "
1791 "@mode\n");
1792 break;
1793 case 2:
1794 dev_info(info->dev, "using mode specified in "
1795 "@mode with ignored refresh rate\n");
1796 break;
1797 case 3:
1798 dev_info(info->dev, "using mode default "
1799 "mode\n");
1800 break;
1801 case 4:
1802 dev_info(info->dev, "using mode from list\n");
1803 break;
1804 default:
1805 dev_info(info->dev, "ret = %d\n", ret);
1806 dev_info(info->dev, "failed to find mode\n");
5fc404e4
BD		 1807 return -EINVAL;
1808 }
1809 }
1810 }
1811
1812 /* initialise and set the palette */
0a5d924e
AS		 1813 if (fb_alloc_cmap(&fb->cmap, NR_PALETTE, 0)) {
1814 dev_err(info->dev, "failed to allocate cmap memory\n");
1815 return -ENOMEM;
1816 }
5fc404e4
BD		 1817 fb_set_cmap(&fb->cmap, fb);
1818
1819 ret = (fb->fbops->fb_check_var)(&fb->var, fb);
1820 if (ret)
1821 dev_err(info->dev, "check_var() failed on initial setup?\n");
1822
5fc404e4
BD		 1823 return 0;
1824}
1825
1826/* default platform data if none is supplied (ie, PCI device) */
1827
1828static struct sm501_platdata_fbsub sm501fb_pdata_crt = {
1829 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1830 SM501FB_FLAG_USE_HWCURSOR |
1831 SM501FB_FLAG_USE_HWACCEL |
1832 SM501FB_FLAG_DISABLE_AT_EXIT),
1833
1834};
1835
1836static struct sm501_platdata_fbsub sm501fb_pdata_pnl = {
1837 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1838 SM501FB_FLAG_USE_HWCURSOR |
1839 SM501FB_FLAG_USE_HWACCEL |
1840 SM501FB_FLAG_DISABLE_AT_EXIT),
1841};
1842
1843static struct sm501_platdata_fb sm501fb_def_pdata = {
1844 .fb_route = SM501_FB_OWN,
1845 .fb_crt = &sm501fb_pdata_crt,
1846 .fb_pnl = &sm501fb_pdata_pnl,
1847};
1848
1849static char driver_name_crt[] = "sm501fb-crt";
1850static char driver_name_pnl[] = "sm501fb-panel";
1851
48c68c4f
GKH		 1852static int sm501fb_probe_one(struct sm501fb_info *info,
1853 enum sm501_controller head)
5fc404e4 1854{
9b599fb2
BD		 1855 unsigned char *name = (head == HEAD_CRT) ? "crt" : "panel";
1856 struct sm501_platdata_fbsub *pd;
1857 struct sm501fb_par *par;
1858 struct fb_info *fbi;
5fc404e4 1859
9b599fb2 1860 pd = (head == HEAD_CRT) ? info->pdata->fb_crt : info->pdata->fb_pnl;
5fc404e4 1861
9b599fb2
BD		 1862 /* Do not initialise if we've not been given any platform data */
1863 if (pd == NULL) {
1864 dev_info(info->dev, "no data for fb %s (disabled)\n", name);
1865 return 0;
1866 }
1867
1868 fbi = framebuffer_alloc(sizeof(struct sm501fb_par), info->dev);
1869 if (fbi == NULL) {
1870 dev_err(info->dev, "cannot allocate %s framebuffer\n", name);
5fc404e4
BD		 1871 return -ENOMEM;
1872 }
1873
9b599fb2
BD		 1874 par = fbi->par;
1875 par->info = info;
1876 par->head = head;
1877 fbi->pseudo_palette = &par->pseudo_palette;
1878
1879 info->fb[head] = fbi;
1880
1881 return 0;
1882}
1883
1884/* Free up anything allocated by sm501fb_init_fb */
1885
1886static void sm501_free_init_fb(struct sm501fb_info *info,
1887 enum sm501_controller head)
1888{
1889 struct fb_info *fbi = info->fb[head];
1890
1891 fb_dealloc_cmap(&fbi->cmap);
1892}
1893
48c68c4f
GKH		 1894static int sm501fb_start_one(struct sm501fb_info *info,
1895 enum sm501_controller head, const char *drvname)
9b599fb2
BD		 1896{
1897 struct fb_info *fbi = info->fb[head];
1898 int ret;
1899
1900 if (!fbi)
1901 return 0;
1902
6c96895e
LT		 1903 mutex_init(&info->fb[head]->mm_lock);
1904
9b599fb2
BD		 1905 ret = sm501fb_init_fb(info->fb[head], head, drvname);
1906 if (ret) {
1907 dev_err(info->dev, "cannot initialise fb %s\n", drvname);
1908 return ret;
1909 }
1910
1911 ret = register_framebuffer(info->fb[head]);
1912 if (ret) {
1913 dev_err(info->dev, "failed to register fb %s\n", drvname);
1914 sm501_free_init_fb(info, head);
1915 return ret;
5fc404e4
BD		 1916 }
1917
9b599fb2
BD		 1918 dev_info(info->dev, "fb%d: %s frame buffer\n", fbi->node, fbi->fix.id);
1919
1920 return 0;
1921}
1922
48c68c4f 1923static int sm501fb_probe(struct platform_device *pdev)
9b599fb2
BD		 1924{
1925 struct sm501fb_info *info;
1926 struct device *dev = &pdev->dev;
1927 int ret;
1928
1929 /* allocate our framebuffers */
1930
1931 info = kzalloc(sizeof(struct sm501fb_info), GFP_KERNEL);
1932 if (!info) {
1933 dev_err(dev, "failed to allocate state\n");
1934 return -ENOMEM;
5fc404e4
BD		 1935 }
1936
9b599fb2
BD		 1937 info->dev = dev = &pdev->dev;
1938 platform_set_drvdata(pdev, info);
1939
5fc404e4
BD		 1940 if (dev->parent->platform_data) {
1941 struct sm501_platdata *pd = dev->parent->platform_data;
1942 info->pdata = pd->fb;
1943 }
1944
1945 if (info->pdata == NULL) {
4295f9bf
HS		 1946 int found = 0;
1947#if defined(CONFIG_OF)
1948 struct device_node *np = pdev->dev.parent->of_node;
1949 const u8 *prop;
1950 const char *cp;
1951 int len;
1952
5fc404e4 1953 info->pdata = &sm501fb_def_pdata;
4295f9bf
HS		 1954 if (np) {
1955 /* Get EDID */
1956 cp = of_get_property(np, "mode", &len);
1957 if (cp)
1958 strcpy(fb_mode, cp);
1959 prop = of_get_property(np, "edid", &len);
1960 if (prop && len == EDID_LENGTH) {
1961 info->edid_data = kmemdup(prop, EDID_LENGTH,
1962 GFP_KERNEL);
1963 if (info->edid_data)
1964 found = 1;
1965 }
1966 }
1967#endif
1968 if (!found) {
1969 dev_info(dev, "using default configuration data\n");
1970 info->pdata = &sm501fb_def_pdata;
1971 }
5fc404e4
BD		 1972 }
1973
9b599fb2 1974 /* probe for the presence of each panel */
5fc404e4 1975
9b599fb2
BD		 1976 ret = sm501fb_probe_one(info, HEAD_CRT);
1977 if (ret < 0) {
1978 dev_err(dev, "failed to probe CRT\n");
1979 goto err_alloc;
5fc404e4
BD		 1980 }
1981
9b599fb2
BD		 1982 ret = sm501fb_probe_one(info, HEAD_PANEL);
1983 if (ret < 0) {
1984 dev_err(dev, "failed to probe PANEL\n");
1985 goto err_probed_crt;
1986 }
5fc404e4 1987
9b599fb2
BD		 1988 if (info->fb[HEAD_PANEL] == NULL &&
1989 info->fb[HEAD_CRT] == NULL) {
1990 dev_err(dev, "no framebuffers found\n");
1991 goto err_alloc;
5fc404e4
BD		 1992 }
1993
9b599fb2 1994 /* get the resources for both of the framebuffers */
5fc404e4 1995
9b599fb2 1996 ret = sm501fb_start(info, pdev);
5fc404e4 1997 if (ret) {
9b599fb2
BD		 1998 dev_err(dev, "cannot initialise SM501\n");
1999 goto err_probed_panel;
5fc404e4
BD		 2000 }
2001
9b599fb2
BD		 2002 ret = sm501fb_start_one(info, HEAD_CRT, driver_name_crt);
2003 if (ret) {
2004 dev_err(dev, "failed to start CRT\n");
2005 goto err_started;
5fc404e4
BD		 2006 }
2007
9b599fb2
BD		 2008 ret = sm501fb_start_one(info, HEAD_PANEL, driver_name_pnl);
2009 if (ret) {
2010 dev_err(dev, "failed to start Panel\n");
2011 goto err_started_crt;
5fc404e4
BD		 2012 }
2013
5fc404e4
BD		 2014 /* create device files */
2015
2016 ret = device_create_file(dev, &dev_attr_crt_src);
2017 if (ret)
9b599fb2 2018 goto err_started_panel;
5fc404e4
BD		 2019
2020 ret = device_create_file(dev, &dev_attr_fbregs_pnl);
2021 if (ret)
9b599fb2 2022 goto err_attached_crtsrc_file;
5fc404e4
BD		 2023
2024 ret = device_create_file(dev, &dev_attr_fbregs_crt);
2025 if (ret)
9b599fb2 2026 goto err_attached_pnlregs_file;
5fc404e4
BD		 2027
2028 /* we registered, return ok */
2029 return 0;
2030
9b599fb2 2031err_attached_pnlregs_file:
5fc404e4
BD		 2032 device_remove_file(dev, &dev_attr_fbregs_pnl);
2033
9b599fb2 2034err_attached_crtsrc_file:
5fc404e4
BD		 2035 device_remove_file(dev, &dev_attr_crt_src);
2036
9b599fb2
BD		 2037err_started_panel:
2038 unregister_framebuffer(info->fb[HEAD_PANEL]);
2039 sm501_free_init_fb(info, HEAD_PANEL);
5fc404e4 2040
9b599fb2
BD		 2041err_started_crt:
2042 unregister_framebuffer(info->fb[HEAD_CRT]);
2043 sm501_free_init_fb(info, HEAD_CRT);
5fc404e4 2044
9b599fb2 2045err_started:
5fc404e4
BD		 2046 sm501fb_stop(info);
2047
9b599fb2
BD		 2048err_probed_panel:
2049 framebuffer_release(info->fb[HEAD_PANEL]);
5fc404e4 2050
9b599fb2
BD		 2051err_probed_crt:
2052 framebuffer_release(info->fb[HEAD_CRT]);
5fc404e4 2053
9b599fb2
BD		 2054err_alloc:
2055 kfree(info);
5fc404e4
BD		 2056
2057 return ret;
2058}
2059
2060
2061/*
2062 * Cleanup
2063 */
2064static int sm501fb_remove(struct platform_device *pdev)
2065{
2066 struct sm501fb_info *info = platform_get_drvdata(pdev);
2067 struct fb_info *fbinfo_crt = info->fb[0];
2068 struct fb_info *fbinfo_pnl = info->fb[1];
2069
2070 device_remove_file(&pdev->dev, &dev_attr_fbregs_crt);
2071 device_remove_file(&pdev->dev, &dev_attr_fbregs_pnl);
2072 device_remove_file(&pdev->dev, &dev_attr_crt_src);
2073
9b599fb2
BD		 2074 sm501_free_init_fb(info, HEAD_CRT);
2075 sm501_free_init_fb(info, HEAD_PANEL);
2076
5fc404e4
BD		 2077 unregister_framebuffer(fbinfo_crt);
2078 unregister_framebuffer(fbinfo_pnl);
2079
2080 sm501fb_stop(info);
9b599fb2 2081 kfree(info);
5fc404e4
BD		 2082
2083 framebuffer_release(fbinfo_pnl);
2084 framebuffer_release(fbinfo_crt);
2085
2086 return 0;
2087}
2088
2089#ifdef CONFIG_PM
2090
2091static int sm501fb_suspend_fb(struct sm501fb_info *info,
2092 enum sm501_controller head)
2093{
2094 struct fb_info *fbi = info->fb[head];
2095 struct sm501fb_par *par = fbi->par;
2096
2097 if (par->screen.size == 0)
2098 return 0;
2099
40488db2
BD		 2100 /* blank the relevant interface to ensure unit power minimised */
2101 (par->ops.fb_blank)(FB_BLANK_POWERDOWN, fbi);
2102
2103 /* tell console/fb driver we are suspending */
2104
ac751efa 2105 console_lock();
40488db2 2106 fb_set_suspend(fbi, 1);
ac751efa 2107 console_unlock();
40488db2 2108
5fc404e4
BD		 2109 /* backup copies in case chip is powered down over suspend */
2110
2111 par->store_fb = vmalloc(par->screen.size);
2112 if (par->store_fb == NULL) {
2113 dev_err(info->dev, "no memory to store screen\n");
2114 return -ENOMEM;
2115 }
2116
2117 par->store_cursor = vmalloc(par->cursor.size);
2118 if (par->store_cursor == NULL) {
2119 dev_err(info->dev, "no memory to store cursor\n");
2120 goto err_nocursor;
2121 }
2122
c1f303bb
BD		 2123 dev_dbg(info->dev, "suspending screen to %p\n", par->store_fb);
2124 dev_dbg(info->dev, "suspending cursor to %p\n", par->store_cursor);
2125
5fc404e4
BD		 2126 memcpy_fromio(par->store_fb, par->screen.k_addr, par->screen.size);
2127 memcpy_fromio(par->store_cursor, par->cursor.k_addr, par->cursor.size);
f22e521f 2128
5fc404e4
BD		 2129 return 0;
2130
2131 err_nocursor:
2132 vfree(par->store_fb);
c1f303bb 2133 par->store_fb = NULL;
5fc404e4
BD		 2134
2135 return -ENOMEM;
5fc404e4
BD		 2136}
2137
2138static void sm501fb_resume_fb(struct sm501fb_info *info,
2139 enum sm501_controller head)
2140{
2141 struct fb_info *fbi = info->fb[head];
2142 struct sm501fb_par *par = fbi->par;
2143
2144 if (par->screen.size == 0)
2145 return;
2146
2147 /* re-activate the configuration */
2148
2149 (par->ops.fb_set_par)(fbi);
2150
2151 /* restore the data */
2152
c1f303bb
BD		 2153 dev_dbg(info->dev, "restoring screen from %p\n", par->store_fb);
2154 dev_dbg(info->dev, "restoring cursor from %p\n", par->store_cursor);
2155
2156 if (par->store_fb)
2157 memcpy_toio(par->screen.k_addr, par->store_fb,
2158 par->screen.size);
2159
2160 if (par->store_cursor)
2161 memcpy_toio(par->cursor.k_addr, par->store_cursor,
2162 par->cursor.size);
5fc404e4 2163
ac751efa 2164 console_lock();
f22e521f 2165 fb_set_suspend(fbi, 0);
ac751efa 2166 console_unlock();
f22e521f 2167
5fc404e4
BD		 2168 vfree(par->store_fb);
2169 vfree(par->store_cursor);
2170}
2171
2172
2173/* suspend and resume support */
2174
2175static int sm501fb_suspend(struct platform_device *pdev, pm_message_t state)
2176{
2177 struct sm501fb_info *info = platform_get_drvdata(pdev);
2178
c1f303bb 2179 /* store crt control to resume with */
bf5f0019 2180 info->pm_crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
c1f303bb 2181
5fc404e4
BD		 2182 sm501fb_suspend_fb(info, HEAD_CRT);
2183 sm501fb_suspend_fb(info, HEAD_PANEL);
2184
2185 /* turn off the clocks, in case the device is not powered down */
2186 sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
2187
2188 return 0;
2189}
2190
c1f303bb
BD		 2191#define SM501_CRT_CTRL_SAVE (SM501_DC_CRT_CONTROL_TVP | \
2192 SM501_DC_CRT_CONTROL_SEL)
2193
2194
5fc404e4
BD		 2195static int sm501fb_resume(struct platform_device *pdev)
2196{
2197 struct sm501fb_info *info = platform_get_drvdata(pdev);
c1f303bb 2198 unsigned long crt_ctrl;
5fc404e4
BD		 2199
2200 sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 1);
2201
c1f303bb
BD		 2202 /* restore the items we want to be saved for crt control */
2203
bf5f0019 2204 crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
c1f303bb
BD		 2205 crt_ctrl &= ~SM501_CRT_CTRL_SAVE;
2206 crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE;
bf5f0019 2207 smc501_writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL);
c1f303bb 2208
5fc404e4
BD		 2209 sm501fb_resume_fb(info, HEAD_CRT);
2210 sm501fb_resume_fb(info, HEAD_PANEL);
2211
2212 return 0;
2213}
2214
2215#else
2216#define sm501fb_suspend NULL
2217#define sm501fb_resume NULL
2218#endif
2219
2220static struct platform_driver sm501fb_driver = {
2221 .probe = sm501fb_probe,
2222 .remove = sm501fb_remove,
2223 .suspend = sm501fb_suspend,
2224 .resume = sm501fb_resume,
2225 .driver = {
2226 .name = "sm501-fb",
2227 .owner = THIS_MODULE,
2228 },
2229};
2230
4277f2c4 2231module_platform_driver(sm501fb_driver);
5fc404e4 2232
e6a04980
HS		 2233module_param_named(mode, fb_mode, charp, 0);
2234MODULE_PARM_DESC(mode,
2235 "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2236module_param_named(bpp, default_bpp, ulong, 0);
2237MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified mode");
5fc404e4
BD		 2238MODULE_AUTHOR("Ben Dooks, Vincent Sanders");
2239MODULE_DESCRIPTION("SM501 Framebuffer driver");
2240MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)