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Merge branch 'master' of ../mine
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
cfb4f5d1 15#include <linux/clk.h>
0246c471 16#include <linux/pm_runtime.h>
cfb4f5d1
MD		 17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
8564557a 19#include <linux/interrupt.h>
1c6a307a 20#include <linux/vmalloc.h>
40331b21 21#include <linux/ioctl.h>
5a0e3ad6 22#include <linux/slab.h>
dd210503 23#include <linux/console.h>
225c9a8d 24#include <video/sh_mobile_lcdc.h>
8564557a 25#include <asm/atomic.h>
cfb4f5d1 26
6de9edd5
GL		 27#include "sh_mobile_lcdcfb.h"
28
a6f15ade
PE		 29#define SIDE_B_OFFSET 0x1000
30#define MIRROR_OFFSET 0x2000
cfb4f5d1 31
cfb4f5d1
MD		 32/* shared registers */
33#define _LDDCKR 0x410
34#define _LDDCKSTPR 0x414
35#define _LDINTR 0x468
36#define _LDSR 0x46c
37#define _LDCNT1R 0x470
38#define _LDCNT2R 0x474
9dd38819 39#define _LDRCNTR 0x478
cfb4f5d1
MD		 40#define _LDDDSR 0x47c
41#define _LDDWD0R 0x800
42#define _LDDRDR 0x840
43#define _LDDWAR 0x900
44#define _LDDRAR 0x904
45
0246c471
MD		 46/* shared registers and their order for context save/restore */
47static int lcdc_shared_regs[] = {
48 _LDDCKR,
49 _LDDCKSTPR,
50 _LDINTR,
51 _LDDDSR,
52 _LDCNT1R,
53 _LDCNT2R,
54};
55#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
56
c44f9f76
GL		 57#define DEFAULT_XRES 1280
58#define DEFAULT_YRES 1024
cfb4f5d1 59
0246c471 60static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 61 [LDDCKPAT1R] = 0x400,
62 [LDDCKPAT2R] = 0x404,
63 [LDMT1R] = 0x418,
64 [LDMT2R] = 0x41c,
65 [LDMT3R] = 0x420,
66 [LDDFR] = 0x424,
67 [LDSM1R] = 0x428,
8564557a 68 [LDSM2R] = 0x42c,
cfb4f5d1
MD		 69 [LDSA1R] = 0x430,
70 [LDMLSR] = 0x438,
71 [LDHCNR] = 0x448,
72 [LDHSYNR] = 0x44c,
73 [LDVLNR] = 0x450,
74 [LDVSYNR] = 0x454,
75 [LDPMR] = 0x460,
6011bdea 76 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 77};
78
0246c471 79static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 80 [LDDCKPAT1R] = 0x408,
81 [LDDCKPAT2R] = 0x40c,
82 [LDMT1R] = 0x600,
83 [LDMT2R] = 0x604,
84 [LDMT3R] = 0x608,
85 [LDDFR] = 0x60c,
86 [LDSM1R] = 0x610,
8564557a 87 [LDSM2R] = 0x614,
cfb4f5d1
MD		 88 [LDSA1R] = 0x618,
89 [LDMLSR] = 0x620,
90 [LDHCNR] = 0x624,
91 [LDHSYNR] = 0x628,
92 [LDVLNR] = 0x62c,
93 [LDVSYNR] = 0x630,
94 [LDPMR] = 0x63c,
95};
96
97#define START_LCDC 0x00000001
98#define LCDC_RESET 0x00000100
99#define DISPLAY_BEU 0x00000008
100#define LCDC_ENABLE 0x00000001
8564557a 101#define LDINTR_FE 0x00000400
9dd38819
PE		 102#define LDINTR_VSE 0x00000200
103#define LDINTR_VEE 0x00000100
8564557a 104#define LDINTR_FS 0x00000004
9dd38819
PE		 105#define LDINTR_VSS 0x00000002
106#define LDINTR_VES 0x00000001
a6f15ade
PE		 107#define LDRCNTR_SRS 0x00020000
108#define LDRCNTR_SRC 0x00010000
109#define LDRCNTR_MRS 0x00000002
110#define LDRCNTR_MRC 0x00000001
40331b21 111#define LDSR_MRS 0x00000100
cfb4f5d1 112
c44f9f76
GL		 113static const struct fb_videomode default_720p = {
114 .name = "HDMI 720p",
115 .xres = 1280,
116 .yres = 720,
117
118 .left_margin = 200,
119 .right_margin = 88,
120 .hsync_len = 48,
121
122 .upper_margin = 20,
123 .lower_margin = 5,
124 .vsync_len = 5,
125
126 .pixclock = 13468,
127 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
0246c471
MD		 128};
129
130struct sh_mobile_lcdc_priv {
131 void __iomem *base;
132 int irq;
133 atomic_t hw_usecnt;
134 struct device *dev;
135 struct clk *dot_clk;
136 unsigned long lddckr;
137 struct sh_mobile_lcdc_chan ch[2];
6011bdea 138 struct notifier_block notifier;
0246c471
MD		 139 unsigned long saved_shared_regs[NR_SHARED_REGS];
140 int started;
141};
142
a6f15ade
PE		 143static bool banked(int reg_nr)
144{
145 switch (reg_nr) {
146 case LDMT1R:
147 case LDMT2R:
148 case LDMT3R:
149 case LDDFR:
150 case LDSM1R:
151 case LDSA1R:
152 case LDMLSR:
153 case LDHCNR:
154 case LDHSYNR:
155 case LDVLNR:
156 case LDVSYNR:
157 return true;
158 }
159 return false;
160}
161
cfb4f5d1
MD		 162static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
163 int reg_nr, unsigned long data)
164{
165 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 166 if (banked(reg_nr))
167 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
168 SIDE_B_OFFSET);
169}
170
171static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
172 int reg_nr, unsigned long data)
173{
174 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
175 MIRROR_OFFSET);
cfb4f5d1
MD		 176}
177
178static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
179 int reg_nr)
180{
181 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
182}
183
184static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
185 unsigned long reg_offs, unsigned long data)
186{
187 iowrite32(data, priv->base + reg_offs);
188}
189
190static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
191 unsigned long reg_offs)
192{
193 return ioread32(priv->base + reg_offs);
194}
195
196static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
197 unsigned long reg_offs,
198 unsigned long mask, unsigned long until)
199{
200 while ((lcdc_read(priv, reg_offs) & mask) != until)
201 cpu_relax();
202}
203
204static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
205{
206 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
207}
208
209static void lcdc_sys_write_index(void *handle, unsigned long data)
210{
211 struct sh_mobile_lcdc_chan *ch = handle;
212
213 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
214 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
215 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 216 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 217}
218
219static void lcdc_sys_write_data(void *handle, unsigned long data)
220{
221 struct sh_mobile_lcdc_chan *ch = handle;
222
223 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
224 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
225 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 226 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 227}
228
229static unsigned long lcdc_sys_read_data(void *handle)
230{
231 struct sh_mobile_lcdc_chan *ch = handle;
232
233 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
234 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
235 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
236 udelay(1);
909f10de 237 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1 238
ec56b66f 239 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
cfb4f5d1
MD		 240}
241
242struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
243 lcdc_sys_write_index,
244 lcdc_sys_write_data,
245 lcdc_sys_read_data,
246};
247
8564557a
MD		 248static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
249{
0246c471
MD		 250 if (atomic_inc_and_test(&priv->hw_usecnt)) {
251 pm_runtime_get_sync(priv->dev);
8564557a
MD		 252 if (priv->dot_clk)
253 clk_enable(priv->dot_clk);
254 }
255}
256
257static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
258{
0246c471 259 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
8564557a
MD		 260 if (priv->dot_clk)
261 clk_disable(priv->dot_clk);
0246c471 262 pm_runtime_put(priv->dev);
8564557a
MD		 263 }
264}
8564557a 265
1c6a307a
PM		 266static int sh_mobile_lcdc_sginit(struct fb_info *info,
267 struct list_head *pagelist)
268{
269 struct sh_mobile_lcdc_chan *ch = info->par;
270 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
271 struct page *page;
272 int nr_pages = 0;
273
274 sg_init_table(ch->sglist, nr_pages_max);
275
276 list_for_each_entry(page, pagelist, lru)
277 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
278
279 return nr_pages;
280}
281
8564557a
MD		 282static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
283 struct list_head *pagelist)
284{
285 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 286 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD		 287
288 /* enable clocks before accessing hardware */
289 sh_mobile_lcdc_clk_on(ch->lcdc);
290
5c1a56b5
PM		 291 /*
292 * It's possible to get here without anything on the pagelist via
293 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
294 * invocation. In the former case, the acceleration routines are
295 * stepped in to when using the framebuffer console causing the
296 * workqueue to be scheduled without any dirty pages on the list.
297 *
298 * Despite this, a panel update is still needed given that the
299 * acceleration routines have their own methods for writing in
300 * that still need to be updated.
301 *
302 * The fsync() and empty pagelist case could be optimized for,
303 * but we don't bother, as any application exhibiting such
304 * behaviour is fundamentally broken anyways.
305 */
306 if (!list_empty(pagelist)) {
307 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
308
309 /* trigger panel update */
310 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 311 if (bcfg->start_transfer)
312 bcfg->start_transfer(bcfg->board_data, ch,
313 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5
PM		 314 lcdc_write_chan(ch, LDSM2R, 1);
315 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 316 } else {
317 if (bcfg->start_transfer)
318 bcfg->start_transfer(bcfg->board_data, ch,
319 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5 320 lcdc_write_chan(ch, LDSM2R, 1);
ef61aae4 321 }
8564557a
MD		 322}
323
324static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
325{
326 struct fb_deferred_io *fbdefio = info->fbdefio;
327
328 if (fbdefio)
329 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
330}
331
332static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
333{
334 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 335 struct sh_mobile_lcdc_chan *ch;
8564557a 336 unsigned long tmp;
9dd38819 337 unsigned long ldintr;
2feb075a
MD		 338 int is_sub;
339 int k;
8564557a
MD		 340
341 /* acknowledge interrupt */
9dd38819
PE		 342 ldintr = tmp = lcdc_read(priv, _LDINTR);
343 /*
344 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
345 * write 0 to bits 0-6 to ack all triggered IRQs.
346 */
347 tmp &= 0xffffff00 & ~LDINTR_VEE;
8564557a
MD		 348 lcdc_write(priv, _LDINTR, tmp);
349
2feb075a
MD		 350 /* figure out if this interrupt is for main or sub lcd */
351 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
352
9dd38819 353 /* wake up channel and disable clocks */
2feb075a
MD		 354 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
355 ch = &priv->ch[k];
356
357 if (!ch->enabled)
358 continue;
359
9dd38819
PE		 360 /* Frame Start */
361 if (ldintr & LDINTR_FS) {
362 if (is_sub == lcdc_chan_is_sublcd(ch)) {
363 ch->frame_end = 1;
364 wake_up(&ch->frame_end_wait);
2feb075a 365
9dd38819
PE		 366 sh_mobile_lcdc_clk_off(priv);
367 }
368 }
369
370 /* VSYNC End */
40331b21
PE		 371 if (ldintr & LDINTR_VES)
372 complete(&ch->vsync_completion);
2feb075a
MD		 373 }
374
8564557a
MD		 375 return IRQ_HANDLED;
376}
377
cfb4f5d1
MD		 378static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
379 int start)
380{
381 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
382 int k;
383
384 /* start or stop the lcdc */
385 if (start)
386 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
387 else
388 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
389
390 /* wait until power is applied/stopped on all channels */
391 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
392 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
393 while (1) {
394 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
395 if (start && tmp == 3)
396 break;
397 if (!start && tmp == 0)
398 break;
399 cpu_relax();
400 }
401
402 if (!start)
403 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
404}
405
6011bdea
GL		 406static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
407{
1c120deb
GL		 408 struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
409 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 410 u32 tmp;
411
412 tmp = ch->ldmt1r_value;
413 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
414 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
415 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
416 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
417 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
418 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
419 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
420 lcdc_write_chan(ch, LDMT1R, tmp);
421
422 /* setup SYS bus */
423 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
424 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
425
426 /* horizontal configuration */
1c120deb
GL		 427 h_total = display_var->xres + display_var->hsync_len +
428 display_var->left_margin + display_var->right_margin;
6011bdea 429 tmp = h_total / 8; /* HTCN */
1c120deb 430 tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 431 lcdc_write_chan(ch, LDHCNR, tmp);
432
1c120deb 433 hsync_pos = display_var->xres + display_var->right_margin;
6011bdea 434 tmp = hsync_pos / 8; /* HSYNP */
1c120deb 435 tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 436 lcdc_write_chan(ch, LDHSYNR, tmp);
437
438 /* vertical configuration */
1c120deb
GL		 439 tmp = display_var->yres + display_var->vsync_len +
440 display_var->upper_margin + display_var->lower_margin; /* VTLN */
441 tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
6011bdea
GL		 442 lcdc_write_chan(ch, LDVLNR, tmp);
443
1c120deb
GL		 444 tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
445 tmp |= display_var->vsync_len << 16; /* VSYNW */
6011bdea
GL		 446 lcdc_write_chan(ch, LDVSYNR, tmp);
447
448 /* Adjust horizontal synchronisation for HDMI */
1c120deb
GL		 449 display_h_total = display_var->xres + display_var->hsync_len +
450 display_var->left_margin + display_var->right_margin;
451 tmp = ((display_var->xres & 7) << 24) |
452 ((display_h_total & 7) << 16) |
453 ((display_var->hsync_len & 7) << 8) |
6011bdea
GL		 454 hsync_pos;
455 lcdc_write_chan(ch, LDHAJR, tmp);
456}
457
cfb4f5d1
MD		 458static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
459{
460 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD		 461 struct sh_mobile_lcdc_board_cfg *board_cfg;
462 unsigned long tmp;
463 int k, m;
464 int ret = 0;
465
8564557a
MD		 466 /* enable clocks before accessing the hardware */
467 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
468 if (priv->ch[k].enabled)
469 sh_mobile_lcdc_clk_on(priv);
470
cfb4f5d1
MD		 471 /* reset */
472 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
473 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
474
475 /* enable LCDC channels */
476 tmp = lcdc_read(priv, _LDCNT2R);
477 tmp |= priv->ch[0].enabled;
478 tmp |= priv->ch[1].enabled;
479 lcdc_write(priv, _LDCNT2R, tmp);
480
481 /* read data from external memory, avoid using the BEU for now */
482 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
483
484 /* stop the lcdc first */
485 sh_mobile_lcdc_start_stop(priv, 0);
486
487 /* configure clocks */
488 tmp = priv->lddckr;
489 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
490 ch = &priv->ch[k];
491
492 if (!priv->ch[k].enabled)
493 continue;
494
495 m = ch->cfg.clock_divider;
496 if (!m)
497 continue;
498
499 if (m == 1)
500 m = 1 << 6;
501 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
502
dd210503 503 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider denominator */
1c120deb 504 lcdc_write_chan(ch, LDDCKPAT1R, 0);
cfb4f5d1
MD		 505 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
506 }
507
508 lcdc_write(priv, _LDDCKR, tmp);
509
510 /* start dotclock again */
511 lcdc_write(priv, _LDDCKSTPR, 0);
512 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
513
8564557a 514 /* interrupts are disabled to begin with */
cfb4f5d1
MD		 515 lcdc_write(priv, _LDINTR, 0);
516
517 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
518 ch = &priv->ch[k];
cfb4f5d1
MD		 519
520 if (!ch->enabled)
521 continue;
522
6011bdea 523 sh_mobile_lcdc_geometry(ch);
cfb4f5d1
MD		 524
525 /* power supply */
526 lcdc_write_chan(ch, LDPMR, 0);
527
cfb4f5d1
MD		 528 board_cfg = &ch->cfg.board_cfg;
529 if (board_cfg->setup_sys)
530 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
531 &sh_mobile_lcdc_sys_bus_ops);
532 if (ret)
533 return ret;
534 }
535
cfb4f5d1
MD		 536 /* word and long word swap */
537 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
538
539 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
540 ch = &priv->ch[k];
541
542 if (!priv->ch[k].enabled)
543 continue;
544
545 /* set bpp format in PKF[4:0] */
546 tmp = lcdc_read_chan(ch, LDDFR);
1c120deb 547 tmp &= ~0x0001001f;
e33afddc 548 tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
cfb4f5d1
MD		 549 lcdc_write_chan(ch, LDDFR, tmp);
550
551 /* point out our frame buffer */
e33afddc 552 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
cfb4f5d1
MD		 553
554 /* set line size */
e33afddc 555 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
cfb4f5d1 556
8564557a
MD		 557 /* setup deferred io if SYS bus */
558 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
559 if (ch->ldmt1r_value & (1 << 12) && tmp) {
560 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
561 ch->defio.delay = msecs_to_jiffies(tmp);
e33afddc
PM		 562 ch->info->fbdefio = &ch->defio;
563 fb_deferred_io_init(ch->info);
8564557a
MD		 564
565 /* one-shot mode */
566 lcdc_write_chan(ch, LDSM1R, 1);
567
568 /* enable "Frame End Interrupt Enable" bit */
569 lcdc_write(priv, _LDINTR, LDINTR_FE);
570
571 } else {
572 /* continuous read mode */
573 lcdc_write_chan(ch, LDSM1R, 0);
574 }
cfb4f5d1
MD		 575 }
576
577 /* display output */
578 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
579
580 /* start the lcdc */
581 sh_mobile_lcdc_start_stop(priv, 1);
8e9bb19e 582 priv->started = 1;
cfb4f5d1
MD		 583
584 /* tell the board code to enable the panel */
585 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
586 ch = &priv->ch[k];
21bc1f02
MD		 587 if (!ch->enabled)
588 continue;
589
cfb4f5d1 590 board_cfg = &ch->cfg.board_cfg;
6de9edd5 591 if (try_module_get(board_cfg->owner) && board_cfg->display_on) {
c2439398 592 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL		 593 module_put(board_cfg->owner);
594 }
cfb4f5d1
MD		 595 }
596
597 return 0;
598}
599
600static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
601{
602 struct sh_mobile_lcdc_chan *ch;
603 struct sh_mobile_lcdc_board_cfg *board_cfg;
604 int k;
605
2feb075a 606 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 607 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
608 ch = &priv->ch[k];
21bc1f02
MD		 609 if (!ch->enabled)
610 continue;
8564557a 611
2feb075a
MD		 612 /* deferred io mode:
613 * flush frame, and wait for frame end interrupt
614 * clean up deferred io and enable clock
615 */
5ef6b505 616 if (ch->info && ch->info->fbdefio) {
2feb075a 617 ch->frame_end = 0;
e33afddc 618 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 619 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 620 fb_deferred_io_cleanup(ch->info);
621 ch->info->fbdefio = NULL;
2feb075a 622 sh_mobile_lcdc_clk_on(priv);
8564557a 623 }
2feb075a
MD		 624
625 board_cfg = &ch->cfg.board_cfg;
6de9edd5 626 if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
2feb075a 627 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 628 module_put(board_cfg->owner);
629 }
cfb4f5d1
MD		 630 }
631
632 /* stop the lcdc */
8e9bb19e
MD		 633 if (priv->started) {
634 sh_mobile_lcdc_start_stop(priv, 0);
635 priv->started = 0;
636 }
b51339ff 637
8564557a
MD		 638 /* stop clocks */
639 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
640 if (priv->ch[k].enabled)
641 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 642}
643
644static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
645{
646 int ifm, miftyp;
647
648 switch (ch->cfg.interface_type) {
649 case RGB8: ifm = 0; miftyp = 0; break;
650 case RGB9: ifm = 0; miftyp = 4; break;
651 case RGB12A: ifm = 0; miftyp = 5; break;
652 case RGB12B: ifm = 0; miftyp = 6; break;
653 case RGB16: ifm = 0; miftyp = 7; break;
654 case RGB18: ifm = 0; miftyp = 10; break;
655 case RGB24: ifm = 0; miftyp = 11; break;
656 case SYS8A: ifm = 1; miftyp = 0; break;
657 case SYS8B: ifm = 1; miftyp = 1; break;
658 case SYS8C: ifm = 1; miftyp = 2; break;
659 case SYS8D: ifm = 1; miftyp = 3; break;
660 case SYS9: ifm = 1; miftyp = 4; break;
661 case SYS12: ifm = 1; miftyp = 5; break;
662 case SYS16A: ifm = 1; miftyp = 7; break;
663 case SYS16B: ifm = 1; miftyp = 8; break;
664 case SYS16C: ifm = 1; miftyp = 9; break;
665 case SYS18: ifm = 1; miftyp = 10; break;
666 case SYS24: ifm = 1; miftyp = 11; break;
667 default: goto bad;
668 }
669
670 /* SUBLCD only supports SYS interface */
671 if (lcdc_chan_is_sublcd(ch)) {
672 if (ifm == 0)
673 goto bad;
674 else
675 ifm = 0;
676 }
677
678 ch->ldmt1r_value = (ifm << 12) | miftyp;
679 return 0;
680 bad:
681 return -EINVAL;
682}
683
b51339ff
MD		 684static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
685 int clock_source,
cfb4f5d1
MD		 686 struct sh_mobile_lcdc_priv *priv)
687{
688 char *str;
689 int icksel;
690
691 switch (clock_source) {
692 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
693 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
694 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
695 default:
696 return -EINVAL;
697 }
698
699 priv->lddckr = icksel << 16;
700
701 if (str) {
b51339ff
MD		 702 priv->dot_clk = clk_get(&pdev->dev, str);
703 if (IS_ERR(priv->dot_clk)) {
704 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
b51339ff 705 return PTR_ERR(priv->dot_clk);
cfb4f5d1 706 }
cfb4f5d1 707 }
0246c471
MD		 708
709 /* Runtime PM support involves two step for this driver:
710 * 1) Enable Runtime PM
711 * 2) Force Runtime PM Resume since hardware is accessed from probe()
712 */
8bed9055 713 priv->dev = &pdev->dev;
0246c471
MD		 714 pm_runtime_enable(priv->dev);
715 pm_runtime_resume(priv->dev);
cfb4f5d1
MD		 716 return 0;
717}
718
719static int sh_mobile_lcdc_setcolreg(u_int regno,
720 u_int red, u_int green, u_int blue,
721 u_int transp, struct fb_info *info)
722{
723 u32 *palette = info->pseudo_palette;
724
725 if (regno >= PALETTE_NR)
726 return -EINVAL;
727
728 /* only FB_VISUAL_TRUECOLOR supported */
729
730 red >>= 16 - info->var.red.length;
731 green >>= 16 - info->var.green.length;
732 blue >>= 16 - info->var.blue.length;
733 transp >>= 16 - info->var.transp.length;
734
735 palette[regno] = (red << info->var.red.offset) |
736 (green << info->var.green.offset) |
737 (blue << info->var.blue.offset) |
738 (transp << info->var.transp.offset);
739
740 return 0;
741}
742
743static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
744 .id = "SH Mobile LCDC",
745 .type = FB_TYPE_PACKED_PIXELS,
746 .visual = FB_VISUAL_TRUECOLOR,
747 .accel = FB_ACCEL_NONE,
9dd38819
PE		 748 .xpanstep = 0,
749 .ypanstep = 1,
750 .ywrapstep = 0,
cfb4f5d1
MD		 751};
752
8564557a
MD		 753static void sh_mobile_lcdc_fillrect(struct fb_info *info,
754 const struct fb_fillrect *rect)
755{
756 sys_fillrect(info, rect);
757 sh_mobile_lcdc_deferred_io_touch(info);
758}
759
760static void sh_mobile_lcdc_copyarea(struct fb_info *info,
761 const struct fb_copyarea *area)
762{
763 sys_copyarea(info, area);
764 sh_mobile_lcdc_deferred_io_touch(info);
765}
766
767static void sh_mobile_lcdc_imageblit(struct fb_info *info,
768 const struct fb_image *image)
769{
770 sys_imageblit(info, image);
771 sh_mobile_lcdc_deferred_io_touch(info);
772}
773
9dd38819
PE		 774static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
775 struct fb_info *info)
776{
777 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 778 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
779 unsigned long ldrcntr;
780 unsigned long new_pan_offset;
781
782 new_pan_offset = (var->yoffset * info->fix.line_length) +
783 (var->xoffset * (info->var.bits_per_pixel / 8));
9dd38819 784
92e1f9a7 785 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 786 return 0; /* No change, do nothing */
787
92e1f9a7 788 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 789
92e1f9a7
PE		 790 /* Set the source address for the next refresh */
791 lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset);
792 if (lcdc_chan_is_sublcd(ch))
793 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
794 else
795 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
796
797 ch->pan_offset = new_pan_offset;
798
799 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 800
801 return 0;
802}
803
40331b21
PE		 804static int sh_mobile_wait_for_vsync(struct fb_info *info)
805{
806 struct sh_mobile_lcdc_chan *ch = info->par;
807 unsigned long ldintr;
808 int ret;
809
810 /* Enable VSync End interrupt */
811 ldintr = lcdc_read(ch->lcdc, _LDINTR);
812 ldintr |= LDINTR_VEE;
813 lcdc_write(ch->lcdc, _LDINTR, ldintr);
814
815 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
816 msecs_to_jiffies(100));
817 if (!ret)
818 return -ETIMEDOUT;
819
820 return 0;
821}
822
823static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
824 unsigned long arg)
825{
826 int retval;
827
828 switch (cmd) {
829 case FBIO_WAITFORVSYNC:
830 retval = sh_mobile_wait_for_vsync(info);
831 break;
832
833 default:
834 retval = -ENOIOCTLCMD;
835 break;
836 }
837 return retval;
838}
839
dd210503
GL		 840static void sh_mobile_fb_reconfig(struct fb_info *info)
841{
842 struct sh_mobile_lcdc_chan *ch = info->par;
843 struct fb_videomode mode1, mode2;
844 struct fb_event event;
845 int evnt = FB_EVENT_MODE_CHANGE_ALL;
846
847 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
848 /* More framebuffer users are active */
849 return;
850
851 fb_var_to_videomode(&mode1, &ch->display_var);
852 fb_var_to_videomode(&mode2, &info->var);
853
854 if (fb_mode_is_equal(&mode1, &mode2))
855 return;
856
857 /* Display has been re-plugged, framebuffer is free now, reconfigure */
858 if (fb_set_var(info, &ch->display_var) < 0)
859 /* Couldn't reconfigure, hopefully, can continue as before */
860 return;
861
862 info->fix.line_length = mode2.xres * (ch->cfg.bpp / 8);
863
864 /*
865 * fb_set_var() calls the notifier change internally, only if
866 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
867 * user event, we have to call the chain ourselves.
868 */
869 event.info = info;
870 event.data = &mode2;
871 fb_notifier_call_chain(evnt, &event);
872}
873
874/*
875 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
876 * user == 1, or with console sem held, if user == 0.
877 */
878static int sh_mobile_release(struct fb_info *info, int user)
879{
880 struct sh_mobile_lcdc_chan *ch = info->par;
881
882 mutex_lock(&ch->open_lock);
883 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
884
885 ch->use_count--;
886
887 /* Nothing to reconfigure, when called from fbcon */
888 if (user) {
889 acquire_console_sem();
890 sh_mobile_fb_reconfig(info);
891 release_console_sem();
892 }
893
894 mutex_unlock(&ch->open_lock);
895
896 return 0;
897}
898
899static int sh_mobile_open(struct fb_info *info, int user)
900{
901 struct sh_mobile_lcdc_chan *ch = info->par;
902
903 mutex_lock(&ch->open_lock);
904 ch->use_count++;
905
906 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
907 mutex_unlock(&ch->open_lock);
908
909 return 0;
910}
911
912static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
913{
914 struct sh_mobile_lcdc_chan *ch = info->par;
915
916 if (var->xres < 160 || var->xres > 1920 ||
917 var->yres < 120 || var->yres > 1080 ||
918 var->left_margin < 32 || var->left_margin > 320 ||
919 var->right_margin < 12 || var->right_margin > 240 ||
920 var->upper_margin < 12 || var->upper_margin > 120 ||
921 var->lower_margin < 1 || var->lower_margin > 64 ||
6031f347 922 var->hsync_len < 32 || var->hsync_len > 240 ||
dd210503
GL		 923 var->vsync_len < 2 || var->vsync_len > 64 ||
924 var->pixclock < 6000 || var->pixclock > 40000 ||
925 var->xres * var->yres * (ch->cfg.bpp / 8) * 2 > info->fix.smem_len) {
926 dev_warn(info->dev, "Invalid info: %u %u %u %u %u %u %u %u %u!\n",
927 var->xres, var->yres,
928 var->left_margin, var->right_margin,
929 var->upper_margin, var->lower_margin,
930 var->hsync_len, var->vsync_len,
931 var->pixclock);
932 return -EINVAL;
933 }
934 return 0;
935}
40331b21 936
cfb4f5d1 937static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 938 .owner = THIS_MODULE,
cfb4f5d1 939 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 940 .fb_read = fb_sys_read,
941 .fb_write = fb_sys_write,
8564557a
MD		 942 .fb_fillrect = sh_mobile_lcdc_fillrect,
943 .fb_copyarea = sh_mobile_lcdc_copyarea,
944 .fb_imageblit = sh_mobile_lcdc_imageblit,
9dd38819 945 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 946 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL		 947 .fb_open = sh_mobile_open,
948 .fb_release = sh_mobile_release,
949 .fb_check_var = sh_mobile_check_var,
cfb4f5d1
MD		 950};
951
952static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
953{
954 switch (bpp) {
955 case 16: /* PKF[4:0] = 00011 - RGB 565 */
956 var->red.offset = 11;
957 var->red.length = 5;
958 var->green.offset = 5;
959 var->green.length = 6;
960 var->blue.offset = 0;
961 var->blue.length = 5;
962 var->transp.offset = 0;
963 var->transp.length = 0;
964 break;
965
966 case 32: /* PKF[4:0] = 00000 - RGB 888
967 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
968 * this may be because LDDDSR has word swap enabled..
969 */
970 var->red.offset = 0;
971 var->red.length = 8;
972 var->green.offset = 24;
973 var->green.length = 8;
974 var->blue.offset = 16;
975 var->blue.length = 8;
976 var->transp.offset = 0;
977 var->transp.length = 0;
978 break;
979 default:
980 return -EINVAL;
981 }
982 var->bits_per_pixel = bpp;
983 var->red.msb_right = 0;
984 var->green.msb_right = 0;
985 var->blue.msb_right = 0;
986 var->transp.msb_right = 0;
987 return 0;
988}
989
2feb075a
MD		 990static int sh_mobile_lcdc_suspend(struct device *dev)
991{
992 struct platform_device *pdev = to_platform_device(dev);
993
994 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
995 return 0;
996}
997
998static int sh_mobile_lcdc_resume(struct device *dev)
999{
1000 struct platform_device *pdev = to_platform_device(dev);
1001
1002 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
1003}
1004
0246c471
MD		 1005static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
1006{
1007 struct platform_device *pdev = to_platform_device(dev);
1008 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1009 struct sh_mobile_lcdc_chan *ch;
1010 int k, n;
1011
1012 /* save per-channel registers */
1013 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1014 ch = &p->ch[k];
1015 if (!ch->enabled)
1016 continue;
1017 for (n = 0; n < NR_CH_REGS; n++)
1018 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
1019 }
1020
1021 /* save shared registers */
1022 for (n = 0; n < NR_SHARED_REGS; n++)
1023 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
1024
1025 /* turn off LCDC hardware */
1026 lcdc_write(p, _LDCNT1R, 0);
1027 return 0;
1028}
1029
1030static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1031{
1032 struct platform_device *pdev = to_platform_device(dev);
1033 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1034 struct sh_mobile_lcdc_chan *ch;
1035 int k, n;
1036
1037 /* restore per-channel registers */
1038 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1039 ch = &p->ch[k];
1040 if (!ch->enabled)
1041 continue;
1042 for (n = 0; n < NR_CH_REGS; n++)
1043 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
1044 }
1045
1046 /* restore shared registers */
1047 for (n = 0; n < NR_SHARED_REGS; n++)
1048 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
1049
1050 return 0;
1051}
1052
47145210 1053static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 1054 .suspend = sh_mobile_lcdc_suspend,
1055 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 1056 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1057 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 1058};
1059
6de9edd5 1060/* locking: called with info->lock held */
6011bdea
GL		 1061static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1062 unsigned long action, void *data)
1063{
1064 struct fb_event *event = data;
1065 struct fb_info *info = event->info;
1066 struct sh_mobile_lcdc_chan *ch = info->par;
1067 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
afe417c0 1068 int ret;
6011bdea
GL		 1069
1070 if (&ch->lcdc->notifier != nb)
baf16374 1071 return NOTIFY_DONE;
6011bdea
GL		 1072
1073 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1074 __func__, action, event->data);
1075
1076 switch(action) {
1077 case FB_EVENT_SUSPEND:
6de9edd5 1078 if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
6011bdea 1079 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 1080 module_put(board_cfg->owner);
1081 }
6011bdea 1082 pm_runtime_put(info->device);
afe417c0 1083 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL		 1084 break;
1085 case FB_EVENT_RESUME:
dd210503
GL		 1086 mutex_lock(&ch->open_lock);
1087 sh_mobile_fb_reconfig(info);
1088 mutex_unlock(&ch->open_lock);
6011bdea
GL		 1089
1090 /* HDMI must be enabled before LCDC configuration */
6de9edd5 1091 if (try_module_get(board_cfg->owner) && board_cfg->display_on) {
dd210503 1092 board_cfg->display_on(board_cfg->board_data, info);
6de9edd5 1093 module_put(board_cfg->owner);
6011bdea
GL		 1094 }
1095
afe417c0
GL		 1096 ret = sh_mobile_lcdc_start(ch->lcdc);
1097 if (!ret)
1098 pm_runtime_get_sync(info->device);
6011bdea
GL		 1099 }
1100
baf16374 1101 return NOTIFY_OK;
6011bdea
GL		 1102}
1103
cfb4f5d1
MD		 1104static int sh_mobile_lcdc_remove(struct platform_device *pdev);
1105
c2e13037 1106static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
cfb4f5d1
MD		 1107{
1108 struct fb_info *info;
1109 struct sh_mobile_lcdc_priv *priv;
01ac25b5 1110 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
cfb4f5d1
MD		 1111 struct resource *res;
1112 int error;
1113 void *buf;
1114 int i, j;
1115
01ac25b5 1116 if (!pdata) {
cfb4f5d1 1117 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1118 return -EINVAL;
cfb4f5d1
MD		 1119 }
1120
1121 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1122 i = platform_get_irq(pdev, 0);
1123 if (!res || i < 0) {
1124 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1125 return -ENOENT;
cfb4f5d1
MD		 1126 }
1127
1128 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1129 if (!priv) {
1130 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1131 return -ENOMEM;
cfb4f5d1
MD		 1132 }
1133
8bed9055
GL		 1134 platform_set_drvdata(pdev, priv);
1135
8564557a 1136 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
7ad33e74 1137 dev_name(&pdev->dev), priv);
8564557a
MD		 1138 if (error) {
1139 dev_err(&pdev->dev, "unable to request irq\n");
1140 goto err1;
1141 }
1142
1143 priv->irq = i;
5ef6b505 1144 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1
MD		 1145
1146 j = 0;
1147 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
01ac25b5 1148 struct sh_mobile_lcdc_chan *ch = priv->ch + j;
cfb4f5d1 1149
01ac25b5
GL		 1150 ch->lcdc = priv;
1151 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
cfb4f5d1 1152
01ac25b5 1153 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 1154 if (error) {
1155 dev_err(&pdev->dev, "unsupported interface type\n");
1156 goto err1;
1157 }
01ac25b5
GL		 1158 init_waitqueue_head(&ch->frame_end_wait);
1159 init_completion(&ch->vsync_completion);
1160 ch->pan_offset = 0;
cfb4f5d1
MD		 1161
1162 switch (pdata->ch[i].chan) {
1163 case LCDC_CHAN_MAINLCD:
01ac25b5
GL		 1164 ch->enabled = 1 << 1;
1165 ch->reg_offs = lcdc_offs_mainlcd;
cfb4f5d1
MD		 1166 j++;
1167 break;
1168 case LCDC_CHAN_SUBLCD:
01ac25b5
GL		 1169 ch->enabled = 1 << 2;
1170 ch->reg_offs = lcdc_offs_sublcd;
cfb4f5d1
MD		 1171 j++;
1172 break;
1173 }
1174 }
1175
1176 if (!j) {
1177 dev_err(&pdev->dev, "no channels defined\n");
1178 error = -EINVAL;
1179 goto err1;
1180 }
1181
dba6f385
GL		 1182 priv->base = ioremap_nocache(res->start, resource_size(res));
1183 if (!priv->base)
1184 goto err1;
1185
b51339ff 1186 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD		 1187 if (error) {
1188 dev_err(&pdev->dev, "unable to setup clocks\n");
1189 goto err1;
1190 }
1191
cfb4f5d1 1192 for (i = 0; i < j; i++) {
6011bdea 1193 struct fb_var_screeninfo *var;
71d3b0fc 1194 const struct fb_videomode *lcd_cfg, *max_cfg = NULL;
01ac25b5 1195 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76
GL		 1196 struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
1197 const struct fb_videomode *mode = cfg->lcd_cfg;
71d3b0fc
GL		 1198 unsigned long max_size = 0;
1199 int k;
cfb4f5d1 1200
01ac25b5
GL		 1201 ch->info = framebuffer_alloc(0, &pdev->dev);
1202 if (!ch->info) {
e33afddc
PM		 1203 dev_err(&pdev->dev, "unable to allocate fb_info\n");
1204 error = -ENOMEM;
1205 break;
1206 }
1207
01ac25b5 1208 info = ch->info;
6011bdea 1209 var = &info->var;
cfb4f5d1 1210 info->fbops = &sh_mobile_lcdc_ops;
c44f9f76 1211 info->par = ch;
dd210503
GL		 1212
1213 mutex_init(&ch->open_lock);
1214
c44f9f76
GL		 1215 for (k = 0, lcd_cfg = mode;
1216 k < cfg->num_cfg && lcd_cfg;
71d3b0fc
GL		 1217 k++, lcd_cfg++) {
1218 unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
1219
1220 if (size > max_size) {
1221 max_cfg = lcd_cfg;
1222 max_size = size;
1223 }
1224 }
1225
c44f9f76
GL		 1226 if (!mode)
1227 max_size = DEFAULT_XRES * DEFAULT_YRES;
1228 else if (max_cfg)
1229 dev_dbg(&pdev->dev, "Found largest videomode %ux%u\n",
1230 max_cfg->xres, max_cfg->yres);
71d3b0fc 1231
cfb4f5d1 1232 info->fix = sh_mobile_lcdc_fix;
71d3b0fc 1233 info->fix.smem_len = max_size * (cfg->bpp / 8) * 2;
cfb4f5d1 1234
c44f9f76
GL		 1235 if (!mode)
1236 mode = &default_720p;
1237
1238 fb_videomode_to_var(var, mode);
9dd38819 1239 /* Default Y virtual resolution is 2x panel size */
6011bdea 1240 var->yres_virtual = var->yres * 2;
6011bdea 1241 var->activate = FB_ACTIVATE_NOW;
6011bdea
GL		 1242
1243 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp);
cfb4f5d1
MD		 1244 if (error)
1245 break;
1246
cfb4f5d1 1247 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1248 &ch->dma_handle, GFP_KERNEL);
cfb4f5d1
MD		 1249 if (!buf) {
1250 dev_err(&pdev->dev, "unable to allocate buffer\n");
1251 error = -ENOMEM;
1252 break;
1253 }
1254
01ac25b5 1255 info->pseudo_palette = &ch->pseudo_palette;
cfb4f5d1
MD		 1256 info->flags = FBINFO_FLAG_DEFAULT;
1257
1258 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1259 if (error < 0) {
1260 dev_err(&pdev->dev, "unable to allocate cmap\n");
1261 dma_free_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1262 buf, ch->dma_handle);
cfb4f5d1
MD		 1263 break;
1264 }
1265
01ac25b5 1266 info->fix.smem_start = ch->dma_handle;
c44f9f76 1267 info->fix.line_length = var->xres * (cfg->bpp / 8);
cfb4f5d1
MD		 1268 info->screen_base = buf;
1269 info->device = &pdev->dev;
1c120deb 1270 ch->display_var = *var;
cfb4f5d1
MD		 1271 }
1272
1273 if (error)
1274 goto err1;
1275
1276 error = sh_mobile_lcdc_start(priv);
1277 if (error) {
1278 dev_err(&pdev->dev, "unable to start hardware\n");
1279 goto err1;
1280 }
1281
1282 for (i = 0; i < j; i++) {
1c6a307a 1283 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76
GL		 1284 const struct fb_videomode *mode = ch->cfg.lcd_cfg;
1285
1286 if (!mode)
1287 mode = &default_720p;
1c6a307a 1288
e33afddc 1289 info = ch->info;
1c6a307a
PM		 1290
1291 if (info->fbdefio) {
8bed9055 1292 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1293 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1294 if (!ch->sglist) {
1c6a307a
PM		 1295 dev_err(&pdev->dev, "cannot allocate sglist\n");
1296 goto err1;
1297 }
1298 }
1299
c44f9f76 1300 fb_videomode_to_modelist(mode, ch->cfg.num_cfg, &info->modelist);
1c6a307a 1301 error = register_framebuffer(info);
cfb4f5d1
MD		 1302 if (error < 0)
1303 goto err1;
cfb4f5d1 1304
cfb4f5d1
MD		 1305 dev_info(info->dev,
1306 "registered %s/%s as %dx%d %dbpp.\n",
1307 pdev->name,
1c6a307a 1308 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
cfb4f5d1 1309 "mainlcd" : "sublcd",
c44f9f76 1310 info->var.xres, info->var.yres,
1c6a307a 1311 ch->cfg.bpp);
8564557a
MD		 1312
1313 /* deferred io mode: disable clock to save power */
6011bdea 1314 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1315 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1316 }
1317
6011bdea
GL		 1318 /* Failure ignored */
1319 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1320 fb_register_client(&priv->notifier);
1321
cfb4f5d1 1322 return 0;
8bed9055 1323err1:
cfb4f5d1 1324 sh_mobile_lcdc_remove(pdev);
8bed9055 1325
cfb4f5d1
MD		 1326 return error;
1327}
1328
1329static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1330{
1331 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1332 struct fb_info *info;
1333 int i;
1334
6011bdea
GL		 1335 fb_unregister_client(&priv->notifier);
1336
cfb4f5d1 1337 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
8bed9055 1338 if (priv->ch[i].info && priv->ch[i].info->dev)
e33afddc 1339 unregister_framebuffer(priv->ch[i].info);
cfb4f5d1
MD		 1340
1341 sh_mobile_lcdc_stop(priv);
1342
1343 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
e33afddc 1344 info = priv->ch[i].info;
cfb4f5d1 1345
e33afddc 1346 if (!info || !info->device)
cfb4f5d1
MD		 1347 continue;
1348
1c6a307a
PM		 1349 if (priv->ch[i].sglist)
1350 vfree(priv->ch[i].sglist);
1351
1ffbb037
MD		 1352 if (info->screen_base)
1353 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1354 info->screen_base,
1355 priv->ch[i].dma_handle);
cfb4f5d1 1356 fb_dealloc_cmap(&info->cmap);
e33afddc 1357 framebuffer_release(info);
cfb4f5d1
MD		 1358 }
1359
b51339ff
MD		 1360 if (priv->dot_clk)
1361 clk_put(priv->dot_clk);
0246c471 1362
8bed9055
GL		 1363 if (priv->dev)
1364 pm_runtime_disable(priv->dev);
cfb4f5d1
MD		 1365
1366 if (priv->base)
1367 iounmap(priv->base);
1368
8564557a
MD		 1369 if (priv->irq)
1370 free_irq(priv->irq, priv);
cfb4f5d1
MD		 1371 kfree(priv);
1372 return 0;
1373}
1374
1375static struct platform_driver sh_mobile_lcdc_driver = {
1376 .driver = {
1377 .name = "sh_mobile_lcdc_fb",
1378 .owner = THIS_MODULE,
2feb075a 1379 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1380 },
1381 .probe = sh_mobile_lcdc_probe,
1382 .remove = sh_mobile_lcdc_remove,
1383};
1384
1385static int __init sh_mobile_lcdc_init(void)
1386{
1387 return platform_driver_register(&sh_mobile_lcdc_driver);
1388}
1389
1390static void __exit sh_mobile_lcdc_exit(void)
1391{
1392 platform_driver_unregister(&sh_mobile_lcdc_driver);
1393}
1394
1395module_init(sh_mobile_lcdc_init);
1396module_exit(sh_mobile_lcdc_exit);
1397
1398MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1399MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1400MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)