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atomic: use <linux/atomic.h>
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
cfb4f5d1 15#include <linux/clk.h>
0246c471 16#include <linux/pm_runtime.h>
cfb4f5d1
MD		 17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
8564557a 19#include <linux/interrupt.h>
1c6a307a 20#include <linux/vmalloc.h>
40331b21 21#include <linux/ioctl.h>
5a0e3ad6 22#include <linux/slab.h>
dd210503 23#include <linux/console.h>
3b0fd9d7
AC		 24#include <linux/backlight.h>
25#include <linux/gpio.h>
225c9a8d 26#include <video/sh_mobile_lcdc.h>
60063497 27#include <linux/atomic.h>
cfb4f5d1 28
6de9edd5 29#include "sh_mobile_lcdcfb.h"
7caa4342 30#include "sh_mobile_meram.h"
6de9edd5 31
a6f15ade
PE		 32#define SIDE_B_OFFSET 0x1000
33#define MIRROR_OFFSET 0x2000
cfb4f5d1 34
cfb4f5d1
MD		 35/* shared registers */
36#define _LDDCKR 0x410
37#define _LDDCKSTPR 0x414
38#define _LDINTR 0x468
39#define _LDSR 0x46c
40#define _LDCNT1R 0x470
41#define _LDCNT2R 0x474
9dd38819 42#define _LDRCNTR 0x478
cfb4f5d1
MD		 43#define _LDDDSR 0x47c
44#define _LDDWD0R 0x800
45#define _LDDRDR 0x840
46#define _LDDWAR 0x900
47#define _LDDRAR 0x904
48
0246c471
MD		 49/* shared registers and their order for context save/restore */
50static int lcdc_shared_regs[] = {
51 _LDDCKR,
52 _LDDCKSTPR,
53 _LDINTR,
54 _LDDDSR,
55 _LDCNT1R,
56 _LDCNT2R,
57};
58#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
59
d2ecbab5
GL		 60#define MAX_XRES 1920
61#define MAX_YRES 1080
cfb4f5d1 62
0246c471 63static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 64 [LDDCKPAT1R] = 0x400,
65 [LDDCKPAT2R] = 0x404,
66 [LDMT1R] = 0x418,
67 [LDMT2R] = 0x41c,
68 [LDMT3R] = 0x420,
69 [LDDFR] = 0x424,
70 [LDSM1R] = 0x428,
8564557a 71 [LDSM2R] = 0x42c,
cfb4f5d1 72 [LDSA1R] = 0x430,
53b50314 73 [LDSA2R] = 0x434,
cfb4f5d1
MD		 74 [LDMLSR] = 0x438,
75 [LDHCNR] = 0x448,
76 [LDHSYNR] = 0x44c,
77 [LDVLNR] = 0x450,
78 [LDVSYNR] = 0x454,
79 [LDPMR] = 0x460,
6011bdea 80 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 81};
82
0246c471 83static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 84 [LDDCKPAT1R] = 0x408,
85 [LDDCKPAT2R] = 0x40c,
86 [LDMT1R] = 0x600,
87 [LDMT2R] = 0x604,
88 [LDMT3R] = 0x608,
89 [LDDFR] = 0x60c,
90 [LDSM1R] = 0x610,
8564557a 91 [LDSM2R] = 0x614,
cfb4f5d1
MD		 92 [LDSA1R] = 0x618,
93 [LDMLSR] = 0x620,
94 [LDHCNR] = 0x624,
95 [LDHSYNR] = 0x628,
96 [LDVLNR] = 0x62c,
97 [LDVSYNR] = 0x630,
98 [LDPMR] = 0x63c,
99};
100
101#define START_LCDC 0x00000001
102#define LCDC_RESET 0x00000100
103#define DISPLAY_BEU 0x00000008
104#define LCDC_ENABLE 0x00000001
8564557a 105#define LDINTR_FE 0x00000400
9dd38819
PE		 106#define LDINTR_VSE 0x00000200
107#define LDINTR_VEE 0x00000100
8564557a 108#define LDINTR_FS 0x00000004
9dd38819
PE		 109#define LDINTR_VSS 0x00000002
110#define LDINTR_VES 0x00000001
a6f15ade
PE		 111#define LDRCNTR_SRS 0x00020000
112#define LDRCNTR_SRC 0x00010000
113#define LDRCNTR_MRS 0x00000002
114#define LDRCNTR_MRC 0x00000001
40331b21 115#define LDSR_MRS 0x00000100
cfb4f5d1 116
c44f9f76
GL		 117static const struct fb_videomode default_720p = {
118 .name = "HDMI 720p",
119 .xres = 1280,
120 .yres = 720,
121
5ae0cf82
GL		 122 .left_margin = 220,
123 .right_margin = 110,
124 .hsync_len = 40,
c44f9f76
GL		 125
126 .upper_margin = 20,
127 .lower_margin = 5,
128 .vsync_len = 5,
129
130 .pixclock = 13468,
5ae0cf82 131 .refresh = 60,
c44f9f76 132 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
0246c471
MD		 133};
134
135struct sh_mobile_lcdc_priv {
136 void __iomem *base;
137 int irq;
138 atomic_t hw_usecnt;
139 struct device *dev;
140 struct clk *dot_clk;
141 unsigned long lddckr;
142 struct sh_mobile_lcdc_chan ch[2];
6011bdea 143 struct notifier_block notifier;
0246c471
MD		 144 unsigned long saved_shared_regs[NR_SHARED_REGS];
145 int started;
417d4827 146 int forced_bpp; /* 2 channel LCDC must share bpp setting */
7caa4342 147 struct sh_mobile_meram_info *meram_dev;
0246c471
MD		 148};
149
a6f15ade
PE		 150static bool banked(int reg_nr)
151{
152 switch (reg_nr) {
153 case LDMT1R:
154 case LDMT2R:
155 case LDMT3R:
156 case LDDFR:
157 case LDSM1R:
158 case LDSA1R:
53b50314 159 case LDSA2R:
a6f15ade
PE		 160 case LDMLSR:
161 case LDHCNR:
162 case LDHSYNR:
163 case LDVLNR:
164 case LDVSYNR:
165 return true;
166 }
167 return false;
168}
169
cfb4f5d1
MD		 170static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
171 int reg_nr, unsigned long data)
172{
173 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 174 if (banked(reg_nr))
175 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
176 SIDE_B_OFFSET);
177}
178
179static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
180 int reg_nr, unsigned long data)
181{
182 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
183 MIRROR_OFFSET);
cfb4f5d1
MD		 184}
185
186static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
187 int reg_nr)
188{
189 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
190}
191
192static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
193 unsigned long reg_offs, unsigned long data)
194{
195 iowrite32(data, priv->base + reg_offs);
196}
197
198static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
199 unsigned long reg_offs)
200{
201 return ioread32(priv->base + reg_offs);
202}
203
204static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
205 unsigned long reg_offs,
206 unsigned long mask, unsigned long until)
207{
208 while ((lcdc_read(priv, reg_offs) & mask) != until)
209 cpu_relax();
210}
211
212static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
213{
214 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
215}
216
217static void lcdc_sys_write_index(void *handle, unsigned long data)
218{
219 struct sh_mobile_lcdc_chan *ch = handle;
220
221 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
222 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
223 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 224 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 225}
226
227static void lcdc_sys_write_data(void *handle, unsigned long data)
228{
229 struct sh_mobile_lcdc_chan *ch = handle;
230
231 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
232 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
233 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 234 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 235}
236
237static unsigned long lcdc_sys_read_data(void *handle)
238{
239 struct sh_mobile_lcdc_chan *ch = handle;
240
241 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
242 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
243 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
244 udelay(1);
909f10de 245 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1 246
ec56b66f 247 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
cfb4f5d1
MD		 248}
249
250struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
251 lcdc_sys_write_index,
252 lcdc_sys_write_data,
253 lcdc_sys_read_data,
254};
255
8564557a
MD		 256static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
257{
0246c471
MD		 258 if (atomic_inc_and_test(&priv->hw_usecnt)) {
259 pm_runtime_get_sync(priv->dev);
8564557a
MD		 260 if (priv->dot_clk)
261 clk_enable(priv->dot_clk);
262 }
263}
264
265static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
266{
0246c471 267 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
8564557a
MD		 268 if (priv->dot_clk)
269 clk_disable(priv->dot_clk);
0246c471 270 pm_runtime_put(priv->dev);
8564557a
MD		 271 }
272}
8564557a 273
1c6a307a
PM		 274static int sh_mobile_lcdc_sginit(struct fb_info *info,
275 struct list_head *pagelist)
276{
277 struct sh_mobile_lcdc_chan *ch = info->par;
278 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
279 struct page *page;
280 int nr_pages = 0;
281
282 sg_init_table(ch->sglist, nr_pages_max);
283
284 list_for_each_entry(page, pagelist, lru)
285 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
286
287 return nr_pages;
288}
289
8564557a
MD		 290static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
291 struct list_head *pagelist)
292{
293 struct sh_mobile_lcdc_chan *ch = info->par;
ef61aae4 294 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
8564557a
MD		 295
296 /* enable clocks before accessing hardware */
297 sh_mobile_lcdc_clk_on(ch->lcdc);
298
5c1a56b5
PM		 299 /*
300 * It's possible to get here without anything on the pagelist via
301 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
302 * invocation. In the former case, the acceleration routines are
303 * stepped in to when using the framebuffer console causing the
304 * workqueue to be scheduled without any dirty pages on the list.
305 *
306 * Despite this, a panel update is still needed given that the
307 * acceleration routines have their own methods for writing in
308 * that still need to be updated.
309 *
310 * The fsync() and empty pagelist case could be optimized for,
311 * but we don't bother, as any application exhibiting such
312 * behaviour is fundamentally broken anyways.
313 */
314 if (!list_empty(pagelist)) {
315 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
316
317 /* trigger panel update */
318 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 319 if (bcfg->start_transfer)
320 bcfg->start_transfer(bcfg->board_data, ch,
321 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5
PM		 322 lcdc_write_chan(ch, LDSM2R, 1);
323 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
ef61aae4
MD		 324 } else {
325 if (bcfg->start_transfer)
326 bcfg->start_transfer(bcfg->board_data, ch,
327 &sh_mobile_lcdc_sys_bus_ops);
5c1a56b5 328 lcdc_write_chan(ch, LDSM2R, 1);
ef61aae4 329 }
8564557a
MD		 330}
331
332static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
333{
334 struct fb_deferred_io *fbdefio = info->fbdefio;
335
336 if (fbdefio)
337 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
338}
339
340static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
341{
342 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 343 struct sh_mobile_lcdc_chan *ch;
8564557a 344 unsigned long tmp;
9dd38819 345 unsigned long ldintr;
2feb075a
MD		 346 int is_sub;
347 int k;
8564557a
MD		 348
349 /* acknowledge interrupt */
9dd38819
PE		 350 ldintr = tmp = lcdc_read(priv, _LDINTR);
351 /*
352 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
353 * write 0 to bits 0-6 to ack all triggered IRQs.
354 */
355 tmp &= 0xffffff00 & ~LDINTR_VEE;
8564557a
MD		 356 lcdc_write(priv, _LDINTR, tmp);
357
2feb075a
MD		 358 /* figure out if this interrupt is for main or sub lcd */
359 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
360
9dd38819 361 /* wake up channel and disable clocks */
2feb075a
MD		 362 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
363 ch = &priv->ch[k];
364
365 if (!ch->enabled)
366 continue;
367
9dd38819
PE		 368 /* Frame Start */
369 if (ldintr & LDINTR_FS) {
370 if (is_sub == lcdc_chan_is_sublcd(ch)) {
371 ch->frame_end = 1;
372 wake_up(&ch->frame_end_wait);
2feb075a 373
9dd38819
PE		 374 sh_mobile_lcdc_clk_off(priv);
375 }
376 }
377
378 /* VSYNC End */
40331b21
PE		 379 if (ldintr & LDINTR_VES)
380 complete(&ch->vsync_completion);
2feb075a
MD		 381 }
382
8564557a
MD		 383 return IRQ_HANDLED;
384}
385
cfb4f5d1
MD		 386static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
387 int start)
388{
389 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
390 int k;
391
392 /* start or stop the lcdc */
393 if (start)
394 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
395 else
396 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
397
398 /* wait until power is applied/stopped on all channels */
399 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
400 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
401 while (1) {
402 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
403 if (start && tmp == 3)
404 break;
405 if (!start && tmp == 0)
406 break;
407 cpu_relax();
408 }
409
410 if (!start)
411 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
412}
413
6011bdea
GL		 414static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
415{
1c120deb
GL		 416 struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
417 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 418 u32 tmp;
419
420 tmp = ch->ldmt1r_value;
421 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
422 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
423 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
424 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
425 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
426 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
427 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
428 lcdc_write_chan(ch, LDMT1R, tmp);
429
430 /* setup SYS bus */
431 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
432 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
433
434 /* horizontal configuration */
1c120deb
GL		 435 h_total = display_var->xres + display_var->hsync_len +
436 display_var->left_margin + display_var->right_margin;
6011bdea 437 tmp = h_total / 8; /* HTCN */
1c120deb 438 tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 439 lcdc_write_chan(ch, LDHCNR, tmp);
440
1c120deb 441 hsync_pos = display_var->xres + display_var->right_margin;
6011bdea 442 tmp = hsync_pos / 8; /* HSYNP */
1c120deb 443 tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 444 lcdc_write_chan(ch, LDHSYNR, tmp);
445
446 /* vertical configuration */
1c120deb
GL		 447 tmp = display_var->yres + display_var->vsync_len +
448 display_var->upper_margin + display_var->lower_margin; /* VTLN */
449 tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
6011bdea
GL		 450 lcdc_write_chan(ch, LDVLNR, tmp);
451
1c120deb
GL		 452 tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
453 tmp |= display_var->vsync_len << 16; /* VSYNW */
6011bdea
GL		 454 lcdc_write_chan(ch, LDVSYNR, tmp);
455
456 /* Adjust horizontal synchronisation for HDMI */
1c120deb
GL		 457 display_h_total = display_var->xres + display_var->hsync_len +
458 display_var->left_margin + display_var->right_margin;
459 tmp = ((display_var->xres & 7) << 24) |
460 ((display_h_total & 7) << 16) |
461 ((display_var->hsync_len & 7) << 8) |
6011bdea
GL		 462 hsync_pos;
463 lcdc_write_chan(ch, LDHAJR, tmp);
464}
465
cfb4f5d1
MD		 466static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
467{
468 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD		 469 struct sh_mobile_lcdc_board_cfg *board_cfg;
470 unsigned long tmp;
417d4827 471 int bpp = 0;
53b50314 472 unsigned long ldddsr;
554cc102 473 int k, m, ret;
cfb4f5d1 474
8564557a 475 /* enable clocks before accessing the hardware */
417d4827
MD		 476 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
477 if (priv->ch[k].enabled) {
8564557a 478 sh_mobile_lcdc_clk_on(priv);
417d4827
MD		 479 if (!bpp)
480 bpp = priv->ch[k].info->var.bits_per_pixel;
481 }
482 }
8564557a 483
cfb4f5d1
MD		 484 /* reset */
485 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
486 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
487
488 /* enable LCDC channels */
489 tmp = lcdc_read(priv, _LDCNT2R);
490 tmp |= priv->ch[0].enabled;
491 tmp |= priv->ch[1].enabled;
492 lcdc_write(priv, _LDCNT2R, tmp);
493
494 /* read data from external memory, avoid using the BEU for now */
495 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
496
497 /* stop the lcdc first */
498 sh_mobile_lcdc_start_stop(priv, 0);
499
500 /* configure clocks */
501 tmp = priv->lddckr;
502 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
503 ch = &priv->ch[k];
504
505 if (!priv->ch[k].enabled)
506 continue;
507
508 m = ch->cfg.clock_divider;
509 if (!m)
510 continue;
511
512 if (m == 1)
513 m = 1 << 6;
514 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
515
dd210503 516 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider denominator */
1c120deb 517 lcdc_write_chan(ch, LDDCKPAT1R, 0);
cfb4f5d1
MD		 518 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
519 }
520
521 lcdc_write(priv, _LDDCKR, tmp);
522
523 /* start dotclock again */
524 lcdc_write(priv, _LDDCKSTPR, 0);
525 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
526
8564557a 527 /* interrupts are disabled to begin with */
cfb4f5d1
MD		 528 lcdc_write(priv, _LDINTR, 0);
529
530 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
531 ch = &priv->ch[k];
cfb4f5d1
MD		 532
533 if (!ch->enabled)
534 continue;
535
6011bdea 536 sh_mobile_lcdc_geometry(ch);
cfb4f5d1
MD		 537
538 /* power supply */
539 lcdc_write_chan(ch, LDPMR, 0);
540
cfb4f5d1 541 board_cfg = &ch->cfg.board_cfg;
69843ba7 542 if (board_cfg->setup_sys) {
554cc102 543 ret = board_cfg->setup_sys(board_cfg->board_data,
69843ba7
GL		 544 ch, &sh_mobile_lcdc_sys_bus_ops);
545 if (ret)
546 return ret;
547 }
cfb4f5d1
MD		 548 }
549
cfb4f5d1 550 /* word and long word swap */
53b50314
DHG		 551 ldddsr = lcdc_read(priv, _LDDDSR);
552 if (priv->ch[0].info->var.nonstd)
553 lcdc_write(priv, _LDDDSR, ldddsr | 7);
554 else {
555 switch (bpp) {
556 case 16:
557 lcdc_write(priv, _LDDDSR, ldddsr | 6);
558 break;
559 case 24:
560 lcdc_write(priv, _LDDDSR, ldddsr | 7);
561 break;
562 case 32:
563 lcdc_write(priv, _LDDDSR, ldddsr | 4);
564 break;
565 }
417d4827 566 }
cfb4f5d1
MD		 567
568 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
7caa4342
DHG		 569 unsigned long base_addr_y;
570 unsigned long base_addr_c = 0;
571 int pitch;
cfb4f5d1
MD		 572 ch = &priv->ch[k];
573
574 if (!priv->ch[k].enabled)
575 continue;
576
577 /* set bpp format in PKF[4:0] */
578 tmp = lcdc_read_chan(ch, LDDFR);
53b50314
DHG		 579 tmp &= ~0x0003031f;
580 if (ch->info->var.nonstd) {
581 tmp |= (ch->info->var.nonstd << 16);
582 switch (ch->info->var.bits_per_pixel) {
583 case 12:
584 break;
585 case 16:
586 tmp |= (0x1 << 8);
587 break;
588 case 24:
589 tmp |= (0x2 << 8);
590 break;
591 }
592 } else {
593 switch (ch->info->var.bits_per_pixel) {
594 case 16:
595 tmp |= 0x03;
596 break;
597 case 24:
598 tmp |= 0x0b;
599 break;
600 case 32:
601 break;
602 }
417d4827 603 }
cfb4f5d1
MD		 604 lcdc_write_chan(ch, LDDFR, tmp);
605
7caa4342
DHG		 606 base_addr_y = ch->info->fix.smem_start;
607 base_addr_c = base_addr_y +
608 ch->info->var.xres *
609 ch->info->var.yres_virtual;
610 pitch = ch->info->fix.line_length;
611
612 /* test if we can enable meram */
eae9b85b
DHG		 613 if (ch->cfg.meram_cfg && priv->meram_dev &&
614 priv->meram_dev->ops) {
7caa4342
DHG		 615 struct sh_mobile_meram_cfg *cfg;
616 struct sh_mobile_meram_info *mdev;
617 unsigned long icb_addr_y, icb_addr_c;
618 int icb_pitch;
619 int pf;
620
621 cfg = ch->cfg.meram_cfg;
622 mdev = priv->meram_dev;
623 /* we need to de-init configured ICBs before we
624 * we can re-initialize them.
625 */
626 if (ch->meram_enabled)
627 mdev->ops->meram_unregister(mdev, cfg);
628
629 ch->meram_enabled = 0;
630
3fedd2ac
DHG		 631 if (ch->info->var.nonstd) {
632 if (ch->info->var.bits_per_pixel == 24)
633 pf = SH_MOBILE_MERAM_PF_NV24;
634 else
635 pf = SH_MOBILE_MERAM_PF_NV;
636 } else {
7caa4342 637 pf = SH_MOBILE_MERAM_PF_RGB;
3fedd2ac 638 }
7caa4342
DHG		 639
640 ret = mdev->ops->meram_register(mdev, cfg, pitch,
641 ch->info->var.yres,
642 pf,
643 base_addr_y,
644 base_addr_c,
645 &icb_addr_y,
646 &icb_addr_c,
647 &icb_pitch);
648 if (!ret) {
649 /* set LDSA1R value */
650 base_addr_y = icb_addr_y;
651 pitch = icb_pitch;
652
653 /* set LDSA2R value if required */
654 if (base_addr_c)
655 base_addr_c = icb_addr_c;
656
657 ch->meram_enabled = 1;
658 }
659 }
660
cfb4f5d1 661 /* point out our frame buffer */
7caa4342 662 lcdc_write_chan(ch, LDSA1R, base_addr_y);
53b50314 663 if (ch->info->var.nonstd)
7caa4342 664 lcdc_write_chan(ch, LDSA2R, base_addr_c);
cfb4f5d1
MD		 665
666 /* set line size */
7caa4342 667 lcdc_write_chan(ch, LDMLSR, pitch);
cfb4f5d1 668
8564557a
MD		 669 /* setup deferred io if SYS bus */
670 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
671 if (ch->ldmt1r_value & (1 << 12) && tmp) {
672 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
673 ch->defio.delay = msecs_to_jiffies(tmp);
e33afddc
PM		 674 ch->info->fbdefio = &ch->defio;
675 fb_deferred_io_init(ch->info);
8564557a
MD		 676
677 /* one-shot mode */
678 lcdc_write_chan(ch, LDSM1R, 1);
679
680 /* enable "Frame End Interrupt Enable" bit */
681 lcdc_write(priv, _LDINTR, LDINTR_FE);
682
683 } else {
684 /* continuous read mode */
685 lcdc_write_chan(ch, LDSM1R, 0);
686 }
cfb4f5d1
MD		 687 }
688
689 /* display output */
690 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
691
692 /* start the lcdc */
693 sh_mobile_lcdc_start_stop(priv, 1);
8e9bb19e 694 priv->started = 1;
cfb4f5d1
MD		 695
696 /* tell the board code to enable the panel */
697 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
698 ch = &priv->ch[k];
21bc1f02
MD		 699 if (!ch->enabled)
700 continue;
701
cfb4f5d1 702 board_cfg = &ch->cfg.board_cfg;
247f9938 703 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
c2439398 704 board_cfg->display_on(board_cfg->board_data, ch->info);
6de9edd5
GL		 705 module_put(board_cfg->owner);
706 }
3b0fd9d7
AC		 707
708 if (ch->bl) {
709 ch->bl->props.power = FB_BLANK_UNBLANK;
710 backlight_update_status(ch->bl);
711 }
cfb4f5d1
MD		 712 }
713
714 return 0;
715}
716
717static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
718{
719 struct sh_mobile_lcdc_chan *ch;
720 struct sh_mobile_lcdc_board_cfg *board_cfg;
721 int k;
722
2feb075a 723 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 724 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
725 ch = &priv->ch[k];
21bc1f02
MD		 726 if (!ch->enabled)
727 continue;
8564557a 728
2feb075a
MD		 729 /* deferred io mode:
730 * flush frame, and wait for frame end interrupt
731 * clean up deferred io and enable clock
732 */
5ef6b505 733 if (ch->info && ch->info->fbdefio) {
2feb075a 734 ch->frame_end = 0;
e33afddc 735 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 736 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 737 fb_deferred_io_cleanup(ch->info);
738 ch->info->fbdefio = NULL;
2feb075a 739 sh_mobile_lcdc_clk_on(priv);
8564557a 740 }
2feb075a 741
3b0fd9d7
AC		 742 if (ch->bl) {
743 ch->bl->props.power = FB_BLANK_POWERDOWN;
744 backlight_update_status(ch->bl);
745 }
746
2feb075a 747 board_cfg = &ch->cfg.board_cfg;
247f9938 748 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
2feb075a 749 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 750 module_put(board_cfg->owner);
751 }
7caa4342
DHG		 752
753 /* disable the meram */
754 if (ch->meram_enabled) {
755 struct sh_mobile_meram_cfg *cfg;
756 struct sh_mobile_meram_info *mdev;
757 cfg = ch->cfg.meram_cfg;
758 mdev = priv->meram_dev;
759 mdev->ops->meram_unregister(mdev, cfg);
760 ch->meram_enabled = 0;
761 }
762
cfb4f5d1
MD		 763 }
764
765 /* stop the lcdc */
8e9bb19e
MD		 766 if (priv->started) {
767 sh_mobile_lcdc_start_stop(priv, 0);
768 priv->started = 0;
769 }
b51339ff 770
8564557a
MD		 771 /* stop clocks */
772 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
773 if (priv->ch[k].enabled)
774 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 775}
776
777static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
778{
779 int ifm, miftyp;
780
781 switch (ch->cfg.interface_type) {
782 case RGB8: ifm = 0; miftyp = 0; break;
783 case RGB9: ifm = 0; miftyp = 4; break;
784 case RGB12A: ifm = 0; miftyp = 5; break;
785 case RGB12B: ifm = 0; miftyp = 6; break;
786 case RGB16: ifm = 0; miftyp = 7; break;
787 case RGB18: ifm = 0; miftyp = 10; break;
788 case RGB24: ifm = 0; miftyp = 11; break;
789 case SYS8A: ifm = 1; miftyp = 0; break;
790 case SYS8B: ifm = 1; miftyp = 1; break;
791 case SYS8C: ifm = 1; miftyp = 2; break;
792 case SYS8D: ifm = 1; miftyp = 3; break;
793 case SYS9: ifm = 1; miftyp = 4; break;
794 case SYS12: ifm = 1; miftyp = 5; break;
795 case SYS16A: ifm = 1; miftyp = 7; break;
796 case SYS16B: ifm = 1; miftyp = 8; break;
797 case SYS16C: ifm = 1; miftyp = 9; break;
798 case SYS18: ifm = 1; miftyp = 10; break;
799 case SYS24: ifm = 1; miftyp = 11; break;
800 default: goto bad;
801 }
802
803 /* SUBLCD only supports SYS interface */
804 if (lcdc_chan_is_sublcd(ch)) {
805 if (ifm == 0)
806 goto bad;
807 else
808 ifm = 0;
809 }
810
811 ch->ldmt1r_value = (ifm << 12) | miftyp;
812 return 0;
813 bad:
814 return -EINVAL;
815}
816
b51339ff
MD		 817static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
818 int clock_source,
cfb4f5d1
MD		 819 struct sh_mobile_lcdc_priv *priv)
820{
821 char *str;
822 int icksel;
823
824 switch (clock_source) {
825 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
826 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
827 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
828 default:
829 return -EINVAL;
830 }
831
832 priv->lddckr = icksel << 16;
833
834 if (str) {
b51339ff
MD		 835 priv->dot_clk = clk_get(&pdev->dev, str);
836 if (IS_ERR(priv->dot_clk)) {
837 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
b51339ff 838 return PTR_ERR(priv->dot_clk);
cfb4f5d1 839 }
cfb4f5d1 840 }
0246c471
MD		 841
842 /* Runtime PM support involves two step for this driver:
843 * 1) Enable Runtime PM
844 * 2) Force Runtime PM Resume since hardware is accessed from probe()
845 */
8bed9055 846 priv->dev = &pdev->dev;
0246c471
MD		 847 pm_runtime_enable(priv->dev);
848 pm_runtime_resume(priv->dev);
cfb4f5d1
MD		 849 return 0;
850}
851
852static int sh_mobile_lcdc_setcolreg(u_int regno,
853 u_int red, u_int green, u_int blue,
854 u_int transp, struct fb_info *info)
855{
856 u32 *palette = info->pseudo_palette;
857
858 if (regno >= PALETTE_NR)
859 return -EINVAL;
860
861 /* only FB_VISUAL_TRUECOLOR supported */
862
863 red >>= 16 - info->var.red.length;
864 green >>= 16 - info->var.green.length;
865 blue >>= 16 - info->var.blue.length;
866 transp >>= 16 - info->var.transp.length;
867
868 palette[regno] = (red << info->var.red.offset) |
869 (green << info->var.green.offset) |
870 (blue << info->var.blue.offset) |
871 (transp << info->var.transp.offset);
872
873 return 0;
874}
875
876static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
877 .id = "SH Mobile LCDC",
878 .type = FB_TYPE_PACKED_PIXELS,
879 .visual = FB_VISUAL_TRUECOLOR,
880 .accel = FB_ACCEL_NONE,
9dd38819
PE		 881 .xpanstep = 0,
882 .ypanstep = 1,
883 .ywrapstep = 0,
cfb4f5d1
MD		 884};
885
8564557a
MD		 886static void sh_mobile_lcdc_fillrect(struct fb_info *info,
887 const struct fb_fillrect *rect)
888{
889 sys_fillrect(info, rect);
890 sh_mobile_lcdc_deferred_io_touch(info);
891}
892
893static void sh_mobile_lcdc_copyarea(struct fb_info *info,
894 const struct fb_copyarea *area)
895{
896 sys_copyarea(info, area);
897 sh_mobile_lcdc_deferred_io_touch(info);
898}
899
900static void sh_mobile_lcdc_imageblit(struct fb_info *info,
901 const struct fb_image *image)
902{
903 sys_imageblit(info, image);
904 sh_mobile_lcdc_deferred_io_touch(info);
905}
906
9dd38819
PE		 907static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
908 struct fb_info *info)
909{
910 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 911 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
912 unsigned long ldrcntr;
913 unsigned long new_pan_offset;
53b50314
DHG		 914 unsigned long base_addr_y, base_addr_c;
915 unsigned long c_offset;
92e1f9a7 916
53b50314
DHG		 917 if (!var->nonstd)
918 new_pan_offset = (var->yoffset * info->fix.line_length) +
919 (var->xoffset * (info->var.bits_per_pixel / 8));
920 else
921 new_pan_offset = (var->yoffset * info->fix.line_length) +
922 (var->xoffset);
9dd38819 923
92e1f9a7 924 if (new_pan_offset == ch->pan_offset)
9dd38819
PE		 925 return 0; /* No change, do nothing */
926
92e1f9a7 927 ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 928
92e1f9a7 929 /* Set the source address for the next refresh */
53b50314
DHG		 930 base_addr_y = ch->dma_handle + new_pan_offset;
931 if (var->nonstd) {
932 /* Set y offset */
933 c_offset = (var->yoffset *
934 info->fix.line_length *
935 (info->var.bits_per_pixel - 8)) / 8;
936 base_addr_c = ch->dma_handle + var->xres * var->yres_virtual +
937 c_offset;
938 /* Set x offset */
939 if (info->var.bits_per_pixel == 24)
940 base_addr_c += 2 * var->xoffset;
941 else
942 base_addr_c += var->xoffset;
943 } else
944 base_addr_c = 0;
945
7caa4342
DHG		 946 if (!ch->meram_enabled) {
947 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
948 if (base_addr_c)
949 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
950 } else {
951 struct sh_mobile_meram_cfg *cfg;
952 struct sh_mobile_meram_info *mdev;
953 unsigned long icb_addr_y, icb_addr_c;
954 int ret;
955
956 cfg = ch->cfg.meram_cfg;
957 mdev = priv->meram_dev;
958 ret = mdev->ops->meram_update(mdev, cfg,
959 base_addr_y, base_addr_c,
960 &icb_addr_y, &icb_addr_c);
961 if (ret)
962 return ret;
963
964 lcdc_write_chan_mirror(ch, LDSA1R, icb_addr_y);
965 if (icb_addr_c)
966 lcdc_write_chan_mirror(ch, LDSA2R, icb_addr_c);
967
968 }
53b50314 969
92e1f9a7
PE		 970 if (lcdc_chan_is_sublcd(ch))
971 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
972 else
973 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
974
975 ch->pan_offset = new_pan_offset;
976
977 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 978
979 return 0;
980}
981
40331b21
PE		 982static int sh_mobile_wait_for_vsync(struct fb_info *info)
983{
984 struct sh_mobile_lcdc_chan *ch = info->par;
985 unsigned long ldintr;
986 int ret;
987
988 /* Enable VSync End interrupt */
989 ldintr = lcdc_read(ch->lcdc, _LDINTR);
990 ldintr |= LDINTR_VEE;
991 lcdc_write(ch->lcdc, _LDINTR, ldintr);
992
993 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
994 msecs_to_jiffies(100));
995 if (!ret)
996 return -ETIMEDOUT;
997
998 return 0;
999}
1000
1001static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
1002 unsigned long arg)
1003{
1004 int retval;
1005
1006 switch (cmd) {
1007 case FBIO_WAITFORVSYNC:
1008 retval = sh_mobile_wait_for_vsync(info);
1009 break;
1010
1011 default:
1012 retval = -ENOIOCTLCMD;
1013 break;
1014 }
1015 return retval;
1016}
1017
dd210503
GL		 1018static void sh_mobile_fb_reconfig(struct fb_info *info)
1019{
1020 struct sh_mobile_lcdc_chan *ch = info->par;
1021 struct fb_videomode mode1, mode2;
1022 struct fb_event event;
1023 int evnt = FB_EVENT_MODE_CHANGE_ALL;
1024
1025 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1026 /* More framebuffer users are active */
1027 return;
1028
1029 fb_var_to_videomode(&mode1, &ch->display_var);
1030 fb_var_to_videomode(&mode2, &info->var);
1031
1032 if (fb_mode_is_equal(&mode1, &mode2))
1033 return;
1034
1035 /* Display has been re-plugged, framebuffer is free now, reconfigure */
1036 if (fb_set_var(info, &ch->display_var) < 0)
1037 /* Couldn't reconfigure, hopefully, can continue as before */
1038 return;
1039
53b50314
DHG		 1040 if (info->var.nonstd)
1041 info->fix.line_length = mode1.xres;
1042 else
1043 info->fix.line_length = mode1.xres * (ch->cfg.bpp / 8);
dd210503
GL		 1044
1045 /*
1046 * fb_set_var() calls the notifier change internally, only if
1047 * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
1048 * user event, we have to call the chain ourselves.
1049 */
1050 event.info = info;
cc267ec5 1051 event.data = &mode1;
dd210503
GL		 1052 fb_notifier_call_chain(evnt, &event);
1053}
1054
1055/*
1056 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1057 * user == 1, or with console sem held, if user == 0.
1058 */
1059static int sh_mobile_release(struct fb_info *info, int user)
1060{
1061 struct sh_mobile_lcdc_chan *ch = info->par;
1062
1063 mutex_lock(&ch->open_lock);
1064 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1065
1066 ch->use_count--;
1067
1068 /* Nothing to reconfigure, when called from fbcon */
1069 if (user) {
ac751efa 1070 console_lock();
dd210503 1071 sh_mobile_fb_reconfig(info);
ac751efa 1072 console_unlock();
dd210503
GL		 1073 }
1074
1075 mutex_unlock(&ch->open_lock);
1076
1077 return 0;
1078}
1079
1080static int sh_mobile_open(struct fb_info *info, int user)
1081{
1082 struct sh_mobile_lcdc_chan *ch = info->par;
1083
1084 mutex_lock(&ch->open_lock);
1085 ch->use_count++;
1086
1087 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1088 mutex_unlock(&ch->open_lock);
1089
1090 return 0;
1091}
1092
1093static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1094{
1095 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1096 struct sh_mobile_lcdc_priv *p = ch->lcdc;
dd210503 1097
d2ecbab5 1098 if (var->xres > MAX_XRES || var->yres > MAX_YRES ||
dd210503 1099 var->xres * var->yres * (ch->cfg.bpp / 8) * 2 > info->fix.smem_len) {
830539d1 1100 dev_warn(info->dev, "Invalid info: %u-%u-%u-%u x %u-%u-%u-%u @ %lukHz!\n",
d2ecbab5
GL		 1101 var->left_margin, var->xres, var->right_margin, var->hsync_len,
1102 var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
1103 PICOS2KHZ(var->pixclock));
dd210503
GL		 1104 return -EINVAL;
1105 }
417d4827
MD		 1106
1107 /* only accept the forced_bpp for dual channel configurations */
1108 if (p->forced_bpp && p->forced_bpp != var->bits_per_pixel)
1109 return -EINVAL;
1110
1111 switch (var->bits_per_pixel) {
1112 case 16: /* PKF[4:0] = 00011 - RGB 565 */
1113 case 24: /* PKF[4:0] = 01011 - RGB 888 */
1114 case 32: /* PKF[4:0] = 00000 - RGBA 888 */
1115 break;
1116 default:
1117 return -EINVAL;
1118 }
1119
dd210503
GL		 1120 return 0;
1121}
40331b21 1122
8857b9aa
AC		 1123/*
1124 * Screen blanking. Behavior is as follows:
1125 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
1126 * FB_BLANK_NORMAL: screen blanked, clocks enabled
1127 * FB_BLANK_VSYNC,
1128 * FB_BLANK_HSYNC,
1129 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
1130 */
1131static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
1132{
1133 struct sh_mobile_lcdc_chan *ch = info->par;
1134 struct sh_mobile_lcdc_priv *p = ch->lcdc;
1135
1136 /* blank the screen? */
1137 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
1138 struct fb_fillrect rect = {
1139 .width = info->var.xres,
1140 .height = info->var.yres,
1141 };
1142 sh_mobile_lcdc_fillrect(info, &rect);
1143 }
1144 /* turn clocks on? */
1145 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
1146 sh_mobile_lcdc_clk_on(p);
1147 }
1148 /* turn clocks off? */
1149 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
1150 /* make sure the screen is updated with the black fill before
1151 * switching the clocks off. one vsync is not enough since
1152 * blanking may occur in the middle of a refresh. deferred io
1153 * mode will reenable the clocks and update the screen in time,
1154 * so it does not need this. */
1155 if (!info->fbdefio) {
1156 sh_mobile_wait_for_vsync(info);
1157 sh_mobile_wait_for_vsync(info);
1158 }
1159 sh_mobile_lcdc_clk_off(p);
1160 }
1161
1162 ch->blank_status = blank;
1163 return 0;
1164}
1165
cfb4f5d1 1166static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 1167 .owner = THIS_MODULE,
cfb4f5d1 1168 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 1169 .fb_read = fb_sys_read,
1170 .fb_write = fb_sys_write,
8564557a
MD		 1171 .fb_fillrect = sh_mobile_lcdc_fillrect,
1172 .fb_copyarea = sh_mobile_lcdc_copyarea,
1173 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 1174 .fb_blank = sh_mobile_lcdc_blank,
9dd38819 1175 .fb_pan_display = sh_mobile_fb_pan_display,
40331b21 1176 .fb_ioctl = sh_mobile_ioctl,
dd210503
GL		 1177 .fb_open = sh_mobile_open,
1178 .fb_release = sh_mobile_release,
1179 .fb_check_var = sh_mobile_check_var,
cfb4f5d1
MD		 1180};
1181
3b0fd9d7
AC		 1182static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
1183{
1184 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1185 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1186 int brightness = bdev->props.brightness;
1187
1188 if (bdev->props.power != FB_BLANK_UNBLANK ||
1189 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
1190 brightness = 0;
1191
1192 return cfg->set_brightness(cfg->board_data, brightness);
1193}
1194
1195static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
1196{
1197 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
1198 struct sh_mobile_lcdc_board_cfg *cfg = &ch->cfg.board_cfg;
1199
1200 return cfg->get_brightness(cfg->board_data);
1201}
1202
1203static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
1204 struct fb_info *info)
1205{
1206 return (info->bl_dev == bdev);
1207}
1208
1209static struct backlight_ops sh_mobile_lcdc_bl_ops = {
1210 .options = BL_CORE_SUSPENDRESUME,
1211 .update_status = sh_mobile_lcdc_update_bl,
1212 .get_brightness = sh_mobile_lcdc_get_brightness,
1213 .check_fb = sh_mobile_lcdc_check_fb,
1214};
1215
1216static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
1217 struct sh_mobile_lcdc_chan *ch)
1218{
1219 struct backlight_device *bl;
1220
1221 bl = backlight_device_register(ch->cfg.bl_info.name, parent, ch,
1222 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 1223 if (IS_ERR(bl)) {
1224 dev_err(parent, "unable to register backlight device: %ld\n",
1225 PTR_ERR(bl));
3b0fd9d7
AC		 1226 return NULL;
1227 }
1228
1229 bl->props.max_brightness = ch->cfg.bl_info.max_brightness;
1230 bl->props.brightness = bl->props.max_brightness;
1231 backlight_update_status(bl);
1232
1233 return bl;
1234}
1235
1236static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
1237{
1238 backlight_device_unregister(bdev);
1239}
1240
53b50314
DHG		 1241static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp,
1242 int nonstd)
cfb4f5d1 1243{
53b50314
DHG		 1244 if (nonstd) {
1245 switch (bpp) {
1246 case 12:
1247 case 16:
1248 case 24:
1249 var->bits_per_pixel = bpp;
1250 var->nonstd = nonstd;
1251 return 0;
1252 default:
1253 return -EINVAL;
1254 }
1255 }
1256
cfb4f5d1
MD		 1257 switch (bpp) {
1258 case 16: /* PKF[4:0] = 00011 - RGB 565 */
1259 var->red.offset = 11;
1260 var->red.length = 5;
1261 var->green.offset = 5;
1262 var->green.length = 6;
1263 var->blue.offset = 0;
1264 var->blue.length = 5;
1265 var->transp.offset = 0;
1266 var->transp.length = 0;
1267 break;
1268
417d4827
MD		 1269 case 24: /* PKF[4:0] = 01011 - RGB 888 */
1270 var->red.offset = 16;
cfb4f5d1 1271 var->red.length = 8;
417d4827 1272 var->green.offset = 8;
cfb4f5d1 1273 var->green.length = 8;
417d4827 1274 var->blue.offset = 0;
cfb4f5d1
MD		 1275 var->blue.length = 8;
1276 var->transp.offset = 0;
1277 var->transp.length = 0;
1278 break;
417d4827
MD		 1279
1280 case 32: /* PKF[4:0] = 00000 - RGBA 888 */
1281 var->red.offset = 16;
1282 var->red.length = 8;
1283 var->green.offset = 8;
1284 var->green.length = 8;
1285 var->blue.offset = 0;
1286 var->blue.length = 8;
1287 var->transp.offset = 24;
1288 var->transp.length = 8;
1289 break;
cfb4f5d1
MD		 1290 default:
1291 return -EINVAL;
1292 }
1293 var->bits_per_pixel = bpp;
1294 var->red.msb_right = 0;
1295 var->green.msb_right = 0;
1296 var->blue.msb_right = 0;
1297 var->transp.msb_right = 0;
1298 return 0;
1299}
1300
2feb075a
MD		 1301static int sh_mobile_lcdc_suspend(struct device *dev)
1302{
1303 struct platform_device *pdev = to_platform_device(dev);
1304
1305 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
1306 return 0;
1307}
1308
1309static int sh_mobile_lcdc_resume(struct device *dev)
1310{
1311 struct platform_device *pdev = to_platform_device(dev);
1312
1313 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
1314}
1315
0246c471
MD		 1316static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
1317{
1318 struct platform_device *pdev = to_platform_device(dev);
1319 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1320 struct sh_mobile_lcdc_chan *ch;
1321 int k, n;
1322
1323 /* save per-channel registers */
1324 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1325 ch = &p->ch[k];
1326 if (!ch->enabled)
1327 continue;
1328 for (n = 0; n < NR_CH_REGS; n++)
1329 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
1330 }
1331
1332 /* save shared registers */
1333 for (n = 0; n < NR_SHARED_REGS; n++)
1334 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
1335
1336 /* turn off LCDC hardware */
1337 lcdc_write(p, _LDCNT1R, 0);
1338 return 0;
1339}
1340
1341static int sh_mobile_lcdc_runtime_resume(struct device *dev)
1342{
1343 struct platform_device *pdev = to_platform_device(dev);
1344 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
1345 struct sh_mobile_lcdc_chan *ch;
1346 int k, n;
1347
1348 /* restore per-channel registers */
1349 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
1350 ch = &p->ch[k];
1351 if (!ch->enabled)
1352 continue;
1353 for (n = 0; n < NR_CH_REGS; n++)
1354 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
1355 }
1356
1357 /* restore shared registers */
1358 for (n = 0; n < NR_SHARED_REGS; n++)
1359 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
1360
1361 return 0;
1362}
1363
47145210 1364static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 1365 .suspend = sh_mobile_lcdc_suspend,
1366 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 1367 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
1368 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 1369};
1370
6de9edd5 1371/* locking: called with info->lock held */
6011bdea
GL		 1372static int sh_mobile_lcdc_notify(struct notifier_block *nb,
1373 unsigned long action, void *data)
1374{
1375 struct fb_event *event = data;
1376 struct fb_info *info = event->info;
1377 struct sh_mobile_lcdc_chan *ch = info->par;
1378 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
6011bdea
GL		 1379
1380 if (&ch->lcdc->notifier != nb)
baf16374 1381 return NOTIFY_DONE;
6011bdea
GL		 1382
1383 dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
1384 __func__, action, event->data);
1385
1386 switch(action) {
1387 case FB_EVENT_SUSPEND:
247f9938 1388 if (board_cfg->display_off && try_module_get(board_cfg->owner)) {
6011bdea 1389 board_cfg->display_off(board_cfg->board_data);
6de9edd5
GL		 1390 module_put(board_cfg->owner);
1391 }
afe417c0 1392 sh_mobile_lcdc_stop(ch->lcdc);
6011bdea
GL		 1393 break;
1394 case FB_EVENT_RESUME:
dd210503
GL		 1395 mutex_lock(&ch->open_lock);
1396 sh_mobile_fb_reconfig(info);
1397 mutex_unlock(&ch->open_lock);
6011bdea
GL		 1398
1399 /* HDMI must be enabled before LCDC configuration */
247f9938 1400 if (board_cfg->display_on && try_module_get(board_cfg->owner)) {
dd210503 1401 board_cfg->display_on(board_cfg->board_data, info);
6de9edd5 1402 module_put(board_cfg->owner);
6011bdea
GL		 1403 }
1404
ebe5e12d 1405 sh_mobile_lcdc_start(ch->lcdc);
6011bdea
GL		 1406 }
1407
baf16374 1408 return NOTIFY_OK;
6011bdea
GL		 1409}
1410
cfb4f5d1
MD		 1411static int sh_mobile_lcdc_remove(struct platform_device *pdev);
1412
c2e13037 1413static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
cfb4f5d1
MD		 1414{
1415 struct fb_info *info;
1416 struct sh_mobile_lcdc_priv *priv;
01ac25b5 1417 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
cfb4f5d1
MD		 1418 struct resource *res;
1419 int error;
1420 void *buf;
1421 int i, j;
1422
01ac25b5 1423 if (!pdata) {
cfb4f5d1 1424 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 1425 return -EINVAL;
cfb4f5d1
MD		 1426 }
1427
1428 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 1429 i = platform_get_irq(pdev, 0);
1430 if (!res || i < 0) {
1431 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 1432 return -ENOENT;
cfb4f5d1
MD		 1433 }
1434
1435 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1436 if (!priv) {
1437 dev_err(&pdev->dev, "cannot allocate device data\n");
8bed9055 1438 return -ENOMEM;
cfb4f5d1
MD		 1439 }
1440
8bed9055
GL		 1441 platform_set_drvdata(pdev, priv);
1442
8564557a 1443 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
7ad33e74 1444 dev_name(&pdev->dev), priv);
8564557a
MD		 1445 if (error) {
1446 dev_err(&pdev->dev, "unable to request irq\n");
1447 goto err1;
1448 }
1449
1450 priv->irq = i;
5ef6b505 1451 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1
MD		 1452
1453 j = 0;
1454 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
01ac25b5 1455 struct sh_mobile_lcdc_chan *ch = priv->ch + j;
cfb4f5d1 1456
01ac25b5
GL		 1457 ch->lcdc = priv;
1458 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
cfb4f5d1 1459
01ac25b5 1460 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 1461 if (error) {
1462 dev_err(&pdev->dev, "unsupported interface type\n");
1463 goto err1;
1464 }
01ac25b5
GL		 1465 init_waitqueue_head(&ch->frame_end_wait);
1466 init_completion(&ch->vsync_completion);
1467 ch->pan_offset = 0;
cfb4f5d1 1468
3b0fd9d7
AC		 1469 /* probe the backlight is there is one defined */
1470 if (ch->cfg.bl_info.max_brightness)
1471 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
1472
cfb4f5d1
MD		 1473 switch (pdata->ch[i].chan) {
1474 case LCDC_CHAN_MAINLCD:
01ac25b5
GL		 1475 ch->enabled = 1 << 1;
1476 ch->reg_offs = lcdc_offs_mainlcd;
cfb4f5d1
MD		 1477 j++;
1478 break;
1479 case LCDC_CHAN_SUBLCD:
01ac25b5
GL		 1480 ch->enabled = 1 << 2;
1481 ch->reg_offs = lcdc_offs_sublcd;
cfb4f5d1
MD		 1482 j++;
1483 break;
1484 }
1485 }
1486
1487 if (!j) {
1488 dev_err(&pdev->dev, "no channels defined\n");
1489 error = -EINVAL;
1490 goto err1;
1491 }
1492
417d4827
MD		 1493 /* for dual channel LCDC (MAIN + SUB) force shared bpp setting */
1494 if (j == 2)
1495 priv->forced_bpp = pdata->ch[0].bpp;
1496
dba6f385
GL		 1497 priv->base = ioremap_nocache(res->start, resource_size(res));
1498 if (!priv->base)
1499 goto err1;
1500
b51339ff 1501 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD		 1502 if (error) {
1503 dev_err(&pdev->dev, "unable to setup clocks\n");
1504 goto err1;
1505 }
1506
7caa4342
DHG		 1507 priv->meram_dev = pdata->meram_dev;
1508
cfb4f5d1 1509 for (i = 0; i < j; i++) {
6011bdea 1510 struct fb_var_screeninfo *var;
71d3b0fc 1511 const struct fb_videomode *lcd_cfg, *max_cfg = NULL;
01ac25b5 1512 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
c44f9f76
GL		 1513 struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
1514 const struct fb_videomode *mode = cfg->lcd_cfg;
71d3b0fc
GL		 1515 unsigned long max_size = 0;
1516 int k;
5fd284e6 1517 int num_cfg;
cfb4f5d1 1518
01ac25b5
GL		 1519 ch->info = framebuffer_alloc(0, &pdev->dev);
1520 if (!ch->info) {
e33afddc
PM		 1521 dev_err(&pdev->dev, "unable to allocate fb_info\n");
1522 error = -ENOMEM;
1523 break;
1524 }
1525
01ac25b5 1526 info = ch->info;
6011bdea 1527 var = &info->var;
cfb4f5d1 1528 info->fbops = &sh_mobile_lcdc_ops;
c44f9f76 1529 info->par = ch;
dd210503
GL		 1530
1531 mutex_init(&ch->open_lock);
1532
c44f9f76
GL		 1533 for (k = 0, lcd_cfg = mode;
1534 k < cfg->num_cfg && lcd_cfg;
71d3b0fc
GL		 1535 k++, lcd_cfg++) {
1536 unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
53b50314
DHG		 1537 /* NV12 buffers must have even number of lines */
1538 if ((cfg->nonstd) && cfg->bpp == 12 &&
1539 (lcd_cfg->yres & 0x1)) {
1540 dev_err(&pdev->dev, "yres must be multiple of 2"
1541 " for YCbCr420 mode.\n");
1542 error = -EINVAL;
1543 goto err1;
1544 }
71d3b0fc
GL		 1545
1546 if (size > max_size) {
1547 max_cfg = lcd_cfg;
1548 max_size = size;
1549 }
1550 }
1551
c44f9f76 1552 if (!mode)
d2ecbab5 1553 max_size = MAX_XRES * MAX_YRES;
c44f9f76
GL		 1554 else if (max_cfg)
1555 dev_dbg(&pdev->dev, "Found largest videomode %ux%u\n",
1556 max_cfg->xres, max_cfg->yres);
71d3b0fc 1557
cfb4f5d1 1558 info->fix = sh_mobile_lcdc_fix;
53b50314
DHG		 1559 info->fix.smem_len = max_size * 2 * cfg->bpp / 8;
1560
1561 /* Only pan in 2 line steps for NV12 */
1562 if (cfg->nonstd && cfg->bpp == 12)
1563 info->fix.ypanstep = 2;
cfb4f5d1 1564
5fd284e6 1565 if (!mode) {
c44f9f76 1566 mode = &default_720p;
5fd284e6
GL		 1567 num_cfg = 1;
1568 } else {
e0b9fb26 1569 num_cfg = cfg->num_cfg;
5fd284e6
GL		 1570 }
1571
1572 fb_videomode_to_modelist(mode, num_cfg, &info->modelist);
c44f9f76
GL		 1573
1574 fb_videomode_to_var(var, mode);
e0b9fb26
GL		 1575 var->width = cfg->lcd_size_cfg.width;
1576 var->height = cfg->lcd_size_cfg.height;
9dd38819 1577 /* Default Y virtual resolution is 2x panel size */
6011bdea 1578 var->yres_virtual = var->yres * 2;
6011bdea 1579 var->activate = FB_ACTIVATE_NOW;
6011bdea 1580
53b50314 1581 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp, cfg->nonstd);
cfb4f5d1
MD		 1582 if (error)
1583 break;
1584
cfb4f5d1 1585 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1586 &ch->dma_handle, GFP_KERNEL);
cfb4f5d1
MD		 1587 if (!buf) {
1588 dev_err(&pdev->dev, "unable to allocate buffer\n");
1589 error = -ENOMEM;
1590 break;
1591 }
1592
01ac25b5 1593 info->pseudo_palette = &ch->pseudo_palette;
cfb4f5d1
MD		 1594 info->flags = FBINFO_FLAG_DEFAULT;
1595
1596 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1597 if (error < 0) {
1598 dev_err(&pdev->dev, "unable to allocate cmap\n");
1599 dma_free_coherent(&pdev->dev, info->fix.smem_len,
01ac25b5 1600 buf, ch->dma_handle);
cfb4f5d1
MD		 1601 break;
1602 }
1603
01ac25b5 1604 info->fix.smem_start = ch->dma_handle;
53b50314
DHG		 1605 if (var->nonstd)
1606 info->fix.line_length = var->xres;
1607 else
1608 info->fix.line_length = var->xres * (cfg->bpp / 8);
1609
cfb4f5d1
MD		 1610 info->screen_base = buf;
1611 info->device = &pdev->dev;
1c120deb 1612 ch->display_var = *var;
cfb4f5d1
MD		 1613 }
1614
1615 if (error)
1616 goto err1;
1617
1618 error = sh_mobile_lcdc_start(priv);
1619 if (error) {
1620 dev_err(&pdev->dev, "unable to start hardware\n");
1621 goto err1;
1622 }
1623
1624 for (i = 0; i < j; i++) {
1c6a307a
PM		 1625 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1626
e33afddc 1627 info = ch->info;
1c6a307a
PM		 1628
1629 if (info->fbdefio) {
8bed9055 1630 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1c6a307a 1631 info->fix.smem_len >> PAGE_SHIFT);
8bed9055 1632 if (!ch->sglist) {
1c6a307a
PM		 1633 dev_err(&pdev->dev, "cannot allocate sglist\n");
1634 goto err1;
1635 }
1636 }
1637
3b0fd9d7
AC		 1638 info->bl_dev = ch->bl;
1639
1c6a307a 1640 error = register_framebuffer(info);
cfb4f5d1
MD		 1641 if (error < 0)
1642 goto err1;
cfb4f5d1 1643
cfb4f5d1
MD		 1644 dev_info(info->dev,
1645 "registered %s/%s as %dx%d %dbpp.\n",
1646 pdev->name,
1c6a307a 1647 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
cfb4f5d1 1648 "mainlcd" : "sublcd",
c44f9f76 1649 info->var.xres, info->var.yres,
1c6a307a 1650 ch->cfg.bpp);
8564557a
MD		 1651
1652 /* deferred io mode: disable clock to save power */
6011bdea 1653 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
8564557a 1654 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1655 }
1656
6011bdea
GL		 1657 /* Failure ignored */
1658 priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1659 fb_register_client(&priv->notifier);
1660
cfb4f5d1 1661 return 0;
8bed9055 1662err1:
cfb4f5d1 1663 sh_mobile_lcdc_remove(pdev);
8bed9055 1664
cfb4f5d1
MD		 1665 return error;
1666}
1667
1668static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1669{
1670 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1671 struct fb_info *info;
1672 int i;
1673
6011bdea
GL		 1674 fb_unregister_client(&priv->notifier);
1675
cfb4f5d1 1676 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
8bed9055 1677 if (priv->ch[i].info && priv->ch[i].info->dev)
e33afddc 1678 unregister_framebuffer(priv->ch[i].info);
cfb4f5d1
MD		 1679
1680 sh_mobile_lcdc_stop(priv);
1681
1682 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
e33afddc 1683 info = priv->ch[i].info;
cfb4f5d1 1684
e33afddc 1685 if (!info || !info->device)
cfb4f5d1
MD		 1686 continue;
1687
1c6a307a
PM		 1688 if (priv->ch[i].sglist)
1689 vfree(priv->ch[i].sglist);
1690
1ffbb037
MD		 1691 if (info->screen_base)
1692 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1693 info->screen_base,
1694 priv->ch[i].dma_handle);
cfb4f5d1 1695 fb_dealloc_cmap(&info->cmap);
e33afddc 1696 framebuffer_release(info);
cfb4f5d1
MD		 1697 }
1698
3b0fd9d7
AC		 1699 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1700 if (priv->ch[i].bl)
1701 sh_mobile_lcdc_bl_remove(priv->ch[i].bl);
1702 }
1703
b51339ff
MD		 1704 if (priv->dot_clk)
1705 clk_put(priv->dot_clk);
0246c471 1706
8bed9055
GL		 1707 if (priv->dev)
1708 pm_runtime_disable(priv->dev);
cfb4f5d1
MD		 1709
1710 if (priv->base)
1711 iounmap(priv->base);
1712
8564557a
MD		 1713 if (priv->irq)
1714 free_irq(priv->irq, priv);
cfb4f5d1
MD		 1715 kfree(priv);
1716 return 0;
1717}
1718
1719static struct platform_driver sh_mobile_lcdc_driver = {
1720 .driver = {
1721 .name = "sh_mobile_lcdc_fb",
1722 .owner = THIS_MODULE,
2feb075a 1723 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1724 },
1725 .probe = sh_mobile_lcdc_probe,
1726 .remove = sh_mobile_lcdc_remove,
1727};
1728
1729static int __init sh_mobile_lcdc_init(void)
1730{
1731 return platform_driver_register(&sh_mobile_lcdc_driver);
1732}
1733
1734static void __exit sh_mobile_lcdc_exit(void)
1735{
1736 platform_driver_unregister(&sh_mobile_lcdc_driver);
1737}
1738
1739module_init(sh_mobile_lcdc_init);
1740module_exit(sh_mobile_lcdc_exit);
1741
1742MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1743MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1744MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)