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Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pm3fb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
f23a06f0
KH		 3 *
4 * Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
5 *
6 * Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
7 * based on pm2fb.c
8 *
1da177e4 9 * Based on code written by:
f23a06f0
KH		 10 * Sven Luther, <luther@dpt-info.u-strasbg.fr>
11 * Alan Hourihane, <alanh@fairlite.demon.co.uk>
12 * Russell King, <rmk@arm.linux.org.uk>
1da177e4
LT		 13 * Based on linux/drivers/video/skeletonfb.c:
14 * Copyright (C) 1997 Geert Uytterhoeven
15 * Based on linux/driver/video/pm2fb.c:
f23a06f0
KH		 16 * Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
17 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
1da177e4
LT		 18 *
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file COPYING in the main directory of this archive for
21 * more details.
22 *
1da177e4
LT		 23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/errno.h>
28#include <linux/string.h>
29#include <linux/mm.h>
1da177e4 30#include <linux/slab.h>
1da177e4 31#include <linux/delay.h>
1da177e4
LT		 32#include <linux/fb.h>
33#include <linux/init.h>
34#include <linux/pci.h>
d5383fcc
KH		 35#ifdef CONFIG_MTRR
36#include <asm/mtrr.h>
37#endif
1da177e4 38
f23a06f0 39#include <video/pm3fb.h>
1da177e4 40
f23a06f0
KH		 41#if !defined(CONFIG_PCI)
42#error "Only generic PCI cards supported."
1da177e4
LT		 43#endif
44
f23a06f0
KH		 45#undef PM3FB_MASTER_DEBUG
46#ifdef PM3FB_MASTER_DEBUG
57bac0f0 47#define DPRINTK(a, b...) \
5ae12170 48 printk(KERN_DEBUG "pm3fb: %s: " a, __func__ , ## b)
f23a06f0 49#else
57bac0f0 50#define DPRINTK(a, b...)
1da177e4 51#endif
1da177e4 52
b0a318e2
KH		 53#define PM3_PIXMAP_SIZE (2048 * 4)
54
f23a06f0
KH		 55/*
56 * Driver data
57 */
1d677a6d 58static int hwcursor = 1;
48c68c4f
GKH		 59static char *mode_option;
60static bool noaccel;
d5383fcc
KH		 61
62/* mtrr option */
63#ifdef CONFIG_MTRR
48c68c4f 64static bool nomtrr;
d5383fcc 65#endif
1da177e4 66
f23a06f0
KH		 67/*
68 * This structure defines the hardware state of the graphics card. Normally
69 * you place this in a header file in linux/include/video. This file usually
70 * also includes register information. That allows other driver subsystems
71 * and userland applications the ability to use the same header file to
72 * avoid duplicate work and easy porting of software.
73 */
74struct pm3_par {
75 unsigned char __iomem *v_regs;/* virtual address of p_regs */
76 u32 video; /* video flags before blanking */
57bac0f0 77 u32 base; /* screen base in 128 bits unit */
2686ba89 78 u32 palette[16];
d5383fcc 79 int mtrr_handle;
1da177e4
LT		 80};
81
f23a06f0
KH		 82/*
83 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
84 * if we don't use modedb. If we do use modedb see pm3fb_init how to use it
85 * to get a fb_var_screeninfo. Otherwise define a default var as well.
86 */
48c68c4f 87static struct fb_fix_screeninfo pm3fb_fix = {
f23a06f0
KH		 88 .id = "Permedia3",
89 .type = FB_TYPE_PACKED_PIXELS,
90 .visual = FB_VISUAL_PSEUDOCOLOR,
91 .xpanstep = 1,
92 .ypanstep = 1,
93 .ywrapstep = 0,
a58d67ce 94 .accel = FB_ACCEL_3DLABS_PERMEDIA3,
1da177e4
LT		 95};
96
f23a06f0
KH		 97/*
98 * Utility functions
99 */
1da177e4 100
f23a06f0
KH		 101static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
102{
103 return fb_readl(par->v_regs + off);
104}
1da177e4 105
f23a06f0
KH		 106static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
107{
108 fb_writel(v, par->v_regs + off);
109}
1da177e4 110
f23a06f0
KH		 111static inline void PM3_WAIT(struct pm3_par *par, u32 n)
112{
deea62d3
KH		 113 while (PM3_READ_REG(par, PM3InFIFOSpace) < n)
114 cpu_relax();
1da177e4
LT		 115}
116
f23a06f0 117static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
1da177e4 118{
2686ba89
KH		 119 PM3_WAIT(par, 3);
120 PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
121 PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
f23a06f0
KH		 122 wmb();
123 PM3_WRITE_REG(par, PM3RD_IndexedData, v);
2686ba89 124 wmb();
1da177e4
LT		 125}
126
f23a06f0
KH		 127static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
128 unsigned char r, unsigned char g, unsigned char b)
1da177e4 129{
2686ba89
KH		 130 PM3_WAIT(par, 4);
131 PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
132 wmb();
133 PM3_WRITE_REG(par, PM3RD_PaletteData, r);
134 wmb();
135 PM3_WRITE_REG(par, PM3RD_PaletteData, g);
136 wmb();
137 PM3_WRITE_REG(par, PM3RD_PaletteData, b);
138 wmb();
f23a06f0
KH		 139}
140
141static void pm3fb_clear_colormap(struct pm3_par *par,
142 unsigned char r, unsigned char g, unsigned char b)
143{
144 int i;
145
2686ba89 146 for (i = 0; i < 256 ; i++)
f23a06f0
KH		 147 pm3fb_set_color(par, i, r, g, b);
148
1da177e4
LT		 149}
150
0ddf7849 151/* Calculating various clock parameters */
f23a06f0
KH		 152static void pm3fb_calculate_clock(unsigned long reqclock,
153 unsigned char *prescale,
154 unsigned char *feedback,
155 unsigned char *postscale)
1da177e4
LT		 156{
157 int f, pre, post;
158 unsigned long freq;
159 long freqerr = 1000;
f23a06f0 160 long currerr;
1da177e4
LT		 161
162 for (f = 1; f < 256; f++) {
163 for (pre = 1; pre < 256; pre++) {
164 for (post = 0; post < 5; post++) {
f23a06f0
KH		 165 freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
166 currerr = (reqclock > freq)
167 ? reqclock - freq
168 : freq - reqclock;
169 if (currerr < freqerr) {
170 freqerr = currerr;
1da177e4
LT		 171 *feedback = f;
172 *prescale = pre;
173 *postscale = post;
1da177e4
LT		 174 }
175 }
176 }
177 }
1da177e4
LT		 178}
179
2686ba89 180static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
1da177e4 181{
0ddf7849 182 if (var->bits_per_pixel == 16)
2686ba89
KH		 183 return var->red.length + var->green.length
184 + var->blue.length;
185
186 return var->bits_per_pixel;
187}
188
189static inline int pm3fb_shift_bpp(unsigned bpp, int v)
190{
191 switch (bpp) {
1da177e4
LT		 192 case 8:
193 return (v >> 4);
1da177e4
LT		 194 case 16:
195 return (v >> 3);
196 case 32:
197 return (v >> 2);
198 }
2686ba89 199 DPRINTK("Unsupported depth %u\n", bpp);
f23a06f0 200 return 0;
1da177e4
LT		 201}
202
a58d67ce
KH		 203/* acceleration */
204static int pm3fb_sync(struct fb_info *info)
205{
206 struct pm3_par *par = info->par;
207
208 PM3_WAIT(par, 2);
209 PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
210 PM3_WRITE_REG(par, PM3Sync, 0);
211 mb();
212 do {
deea62d3
KH		 213 while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0)
214 cpu_relax();
a58d67ce
KH		 215 } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
216
217 return 0;
218}
219
220static void pm3fb_init_engine(struct fb_info *info)
221{
222 struct pm3_par *par = info->par;
223 const u32 width = (info->var.xres_virtual + 7) & ~7;
224
225 PM3_WAIT(par, 50);
226 PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
227 PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
228 PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
229 PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
230 PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
231 PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
232 PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
233 PM3_WRITE_REG(par, PM3GIDMode, 0x0);
234 PM3_WRITE_REG(par, PM3DepthMode, 0x0);
235 PM3_WRITE_REG(par, PM3StencilMode, 0x0);
236 PM3_WRITE_REG(par, PM3StencilData, 0x0);
237 PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
238 PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
239 PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
240 PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
241 PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
242 PM3_WRITE_REG(par, PM3LUTMode, 0x0);
243 PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
244 PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
245 PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
246 PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
247 PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
248 PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
249 PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
250 PM3_WRITE_REG(par, PM3FogMode, 0x0);
251 PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
252 PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
253 PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
254 PM3_WRITE_REG(par, PM3YUVMode, 0x0);
255 PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
256 PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
257 PM3_WRITE_REG(par, PM3DitherMode, 0x0);
258 PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
259 PM3_WRITE_REG(par, PM3RouterMode, 0x0);
260 PM3_WRITE_REG(par, PM3Window, 0x0);
261
262 PM3_WRITE_REG(par, PM3Config2D, 0x0);
263
264 PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
265
266 PM3_WRITE_REG(par, PM3XBias, 0x0);
267 PM3_WRITE_REG(par, PM3YBias, 0x0);
268 PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
269
270 PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
271
272 PM3_WRITE_REG(par, PM3FBDestReadEnables,
273 PM3FBDestReadEnables_E(0xff) |
274 PM3FBDestReadEnables_R(0xff) |
275 PM3FBDestReadEnables_ReferenceAlpha(0xff));
276 PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
277 PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
278 PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
279 PM3FBDestReadBufferWidth_Width(width));
280
281 PM3_WRITE_REG(par, PM3FBDestReadMode,
282 PM3FBDestReadMode_ReadEnable |
283 PM3FBDestReadMode_Enable0);
284 PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
285 PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
286 PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
287 PM3FBSourceReadBufferWidth_Width(width));
288 PM3_WRITE_REG(par, PM3FBSourceReadMode,
289 PM3FBSourceReadMode_Blocking |
290 PM3FBSourceReadMode_ReadEnable);
291
292 PM3_WAIT(par, 2);
293 {
e7f76df9
KH		 294 /* invert bits in bitmask */
295 unsigned long rm = 1 | (3 << 7);
a58d67ce
KH		 296 switch (info->var.bits_per_pixel) {
297 case 8:
298 PM3_WRITE_REG(par, PM3PixelSize,
299 PM3PixelSize_GLOBAL_8BIT);
e7f76df9
KH		 300#ifdef __BIG_ENDIAN
301 rm |= 3 << 15;
302#endif
a58d67ce
KH		 303 break;
304 case 16:
305 PM3_WRITE_REG(par, PM3PixelSize,
306 PM3PixelSize_GLOBAL_16BIT);
e7f76df9
KH		 307#ifdef __BIG_ENDIAN
308 rm |= 2 << 15;
309#endif
a58d67ce
KH		 310 break;
311 case 32:
312 PM3_WRITE_REG(par, PM3PixelSize,
313 PM3PixelSize_GLOBAL_32BIT);
314 break;
315 default:
316 DPRINTK(1, "Unsupported depth %d\n",
317 info->var.bits_per_pixel);
318 break;
319 }
320 PM3_WRITE_REG(par, PM3RasterizerMode, rm);
321 }
322
323 PM3_WAIT(par, 20);
324 PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
325 PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
326 PM3_WRITE_REG(par, PM3FBWriteMode,
327 PM3FBWriteMode_WriteEnable |
328 PM3FBWriteMode_OpaqueSpan |
329 PM3FBWriteMode_Enable0);
330 PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
331 PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
332 PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
333 PM3FBWriteBufferWidth_Width(width));
334
335 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
336 {
337 /* size in lines of FB */
338 unsigned long sofb = info->screen_size /
339 info->fix.line_length;
340 if (sofb > 4095)
341 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
342 else
343 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
344
345 switch (info->var.bits_per_pixel) {
346 case 8:
347 PM3_WRITE_REG(par, PM3DitherMode,
348 (1 << 10) | (2 << 3));
349 break;
350 case 16:
351 PM3_WRITE_REG(par, PM3DitherMode,
352 (1 << 10) | (1 << 3));
353 break;
354 case 32:
355 PM3_WRITE_REG(par, PM3DitherMode,
356 (1 << 10) | (0 << 3));
357 break;
358 default:
359 DPRINTK(1, "Unsupported depth %d\n",
360 info->current_par->depth);
361 break;
362 }
363 }
364
365 PM3_WRITE_REG(par, PM3dXDom, 0x0);
366 PM3_WRITE_REG(par, PM3dXSub, 0x0);
0ddf7849 367 PM3_WRITE_REG(par, PM3dY, 1 << 16);
a58d67ce
KH		 368 PM3_WRITE_REG(par, PM3StartXDom, 0x0);
369 PM3_WRITE_REG(par, PM3StartXSub, 0x0);
370 PM3_WRITE_REG(par, PM3StartY, 0x0);
371 PM3_WRITE_REG(par, PM3Count, 0x0);
372
373/* Disable LocalBuffer. better safe than sorry */
374 PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
375 PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
376 PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
377 PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
378
379 pm3fb_sync(info);
380}
381
57bac0f0 382static void pm3fb_fillrect(struct fb_info *info,
a58d67ce
KH		 383 const struct fb_fillrect *region)
384{
385 struct pm3_par *par = info->par;
386 struct fb_fillrect modded;
387 int vxres, vyres;
0ddf7849 388 int rop;
a58d67ce 389 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
57bac0f0 390 ((u32 *)info->pseudo_palette)[region->color] : region->color;
a58d67ce
KH		 391
392 if (info->state != FBINFO_STATE_RUNNING)
393 return;
0ddf7849 394 if (info->flags & FBINFO_HWACCEL_DISABLED) {
a58d67ce
KH		 395 cfb_fillrect(info, region);
396 return;
397 }
0ddf7849
KH		 398 if (region->rop == ROP_COPY )
399 rop = PM3Config2D_ForegroundROP(0x3); /* GXcopy */
400 else
401 rop = PM3Config2D_ForegroundROP(0x6) | /* GXxor */
402 PM3Config2D_FBDestReadEnable;
a58d67ce
KH		 403
404 vxres = info->var.xres_virtual;
405 vyres = info->var.yres_virtual;
406
407 memcpy(&modded, region, sizeof(struct fb_fillrect));
408
57bac0f0
KH		 409 if (!modded.width || !modded.height ||
410 modded.dx >= vxres || modded.dy >= vyres)
a58d67ce
KH		 411 return;
412
57bac0f0 413 if (modded.dx + modded.width > vxres)
a58d67ce 414 modded.width = vxres - modded.dx;
57bac0f0 415 if (modded.dy + modded.height > vyres)
a58d67ce
KH		 416 modded.height = vyres - modded.dy;
417
57bac0f0 418 if (info->var.bits_per_pixel == 8)
a58d67ce 419 color |= color << 8;
57bac0f0 420 if (info->var.bits_per_pixel <= 16)
a58d67ce
KH		 421 color |= color << 16;
422
423 PM3_WAIT(par, 4);
e7f76df9 424 /* ROP Ox3 is GXcopy */
a58d67ce 425 PM3_WRITE_REG(par, PM3Config2D,
e7f76df9
KH		 426 PM3Config2D_UseConstantSource |
427 PM3Config2D_ForegroundROPEnable |
0ddf7849 428 rop |
e7f76df9 429 PM3Config2D_FBWriteEnable);
a58d67ce
KH		 430
431 PM3_WRITE_REG(par, PM3ForegroundColor, color);
432
433 PM3_WRITE_REG(par, PM3RectanglePosition,
0ddf7849
KH		 434 PM3RectanglePosition_XOffset(modded.dx) |
435 PM3RectanglePosition_YOffset(modded.dy));
a58d67ce
KH		 436
437 PM3_WRITE_REG(par, PM3Render2D,
438 PM3Render2D_XPositive |
439 PM3Render2D_YPositive |
440 PM3Render2D_Operation_Normal |
441 PM3Render2D_SpanOperation |
0ddf7849
KH		 442 PM3Render2D_Width(modded.width) |
443 PM3Render2D_Height(modded.height));
a58d67ce 444}
e7f76df9
KH		 445
446static void pm3fb_copyarea(struct fb_info *info,
447 const struct fb_copyarea *area)
448{
449 struct pm3_par *par = info->par;
450 struct fb_copyarea modded;
451 u32 vxres, vyres;
452 int x_align, o_x, o_y;
453
454 if (info->state != FBINFO_STATE_RUNNING)
455 return;
456 if (info->flags & FBINFO_HWACCEL_DISABLED) {
457 cfb_copyarea(info, area);
458 return;
459 }
460
461 memcpy(&modded, area, sizeof(struct fb_copyarea));
462
463 vxres = info->var.xres_virtual;
464 vyres = info->var.yres_virtual;
465
57bac0f0
KH		 466 if (!modded.width || !modded.height ||
467 modded.sx >= vxres || modded.sy >= vyres ||
468 modded.dx >= vxres || modded.dy >= vyres)
e7f76df9
KH		 469 return;
470
57bac0f0 471 if (modded.sx + modded.width > vxres)
e7f76df9 472 modded.width = vxres - modded.sx;
57bac0f0 473 if (modded.dx + modded.width > vxres)
e7f76df9 474 modded.width = vxres - modded.dx;
57bac0f0 475 if (modded.sy + modded.height > vyres)
e7f76df9 476 modded.height = vyres - modded.sy;
57bac0f0 477 if (modded.dy + modded.height > vyres)
e7f76df9
KH		 478 modded.height = vyres - modded.dy;
479
480 o_x = modded.sx - modded.dx; /*(sx > dx ) ? (sx - dx) : (dx - sx); */
481 o_y = modded.sy - modded.dy; /*(sy > dy ) ? (sy - dy) : (dy - sy); */
482
483 x_align = (modded.sx & 0x1f);
484
485 PM3_WAIT(par, 6);
486
487 PM3_WRITE_REG(par, PM3Config2D,
488 PM3Config2D_UserScissorEnable |
489 PM3Config2D_ForegroundROPEnable |
490 PM3Config2D_Blocking |
0ddf7849 491 PM3Config2D_ForegroundROP(0x3) | /* Ox3 is GXcopy */
e7f76df9
KH		 492 PM3Config2D_FBWriteEnable);
493
494 PM3_WRITE_REG(par, PM3ScissorMinXY,
495 ((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff));
496 PM3_WRITE_REG(par, PM3ScissorMaxXY,
497 (((modded.dy + modded.height) & 0x0fff) << 16) |
498 ((modded.dx + modded.width) & 0x0fff));
499
500 PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
501 PM3FBSourceReadBufferOffset_XOffset(o_x) |
502 PM3FBSourceReadBufferOffset_YOffset(o_y));
503
504 PM3_WRITE_REG(par, PM3RectanglePosition,
0ddf7849
KH		 505 PM3RectanglePosition_XOffset(modded.dx - x_align) |
506 PM3RectanglePosition_YOffset(modded.dy));
e7f76df9
KH		 507
508 PM3_WRITE_REG(par, PM3Render2D,
509 ((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) |
510 ((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) |
511 PM3Render2D_Operation_Normal |
512 PM3Render2D_SpanOperation |
513 PM3Render2D_FBSourceReadEnable |
0ddf7849
KH		 514 PM3Render2D_Width(modded.width + x_align) |
515 PM3Render2D_Height(modded.height));
e7f76df9
KH		 516}
517
518static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image)
519{
520 struct pm3_par *par = info->par;
521 u32 height = image->height;
522 u32 fgx, bgx;
57bac0f0 523 const u32 *src = (const u32 *)image->data;
e7f76df9 524
0ddf7849
KH		 525 if (info->state != FBINFO_STATE_RUNNING)
526 return;
527 if (info->flags & FBINFO_HWACCEL_DISABLED) {
528 cfb_imageblit(info, image);
529 return;
530 }
e7f76df9 531 switch (info->fix.visual) {
57bac0f0
KH		 532 case FB_VISUAL_PSEUDOCOLOR:
533 fgx = image->fg_color;
534 bgx = image->bg_color;
535 break;
536 case FB_VISUAL_TRUECOLOR:
537 default:
538 fgx = par->palette[image->fg_color];
539 bgx = par->palette[image->bg_color];
540 break;
e7f76df9 541 }
7654532d
HE		 542 if (image->depth != 1) {
543 cfb_imageblit(info, image);
544 return;
545 }
57bac0f0 546
e7f76df9
KH		 547 if (info->var.bits_per_pixel == 8) {
548 fgx |= fgx << 8;
549 bgx |= bgx << 8;
550 }
551 if (info->var.bits_per_pixel <= 16) {
552 fgx |= fgx << 16;
553 bgx |= bgx << 16;
554 }
555
b0a318e2 556 PM3_WAIT(par, 7);
e7f76df9
KH		 557
558 PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
559 PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
560
561 /* ROP Ox3 is GXcopy */
562 PM3_WRITE_REG(par, PM3Config2D,
b0a318e2 563 PM3Config2D_UserScissorEnable |
e7f76df9
KH		 564 PM3Config2D_UseConstantSource |
565 PM3Config2D_ForegroundROPEnable |
0ddf7849 566 PM3Config2D_ForegroundROP(0x3) |
e7f76df9
KH		 567 PM3Config2D_OpaqueSpan |
568 PM3Config2D_FBWriteEnable);
b0a318e2
KH		 569 PM3_WRITE_REG(par, PM3ScissorMinXY,
570 ((image->dy & 0x0fff) << 16) | (image->dx & 0x0fff));
571 PM3_WRITE_REG(par, PM3ScissorMaxXY,
572 (((image->dy + image->height) & 0x0fff) << 16) |
573 ((image->dx + image->width) & 0x0fff));
e7f76df9 574 PM3_WRITE_REG(par, PM3RectanglePosition,
0ddf7849
KH		 575 PM3RectanglePosition_XOffset(image->dx) |
576 PM3RectanglePosition_YOffset(image->dy));
e7f76df9
KH		 577 PM3_WRITE_REG(par, PM3Render2D,
578 PM3Render2D_XPositive |
579 PM3Render2D_YPositive |
580 PM3Render2D_Operation_SyncOnBitMask |
581 PM3Render2D_SpanOperation |
0ddf7849
KH		 582 PM3Render2D_Width(image->width) |
583 PM3Render2D_Height(image->height));
e7f76df9
KH		 584
585
586 while (height--) {
c79ba28c
KH		 587 int width = ((image->width + 7) >> 3)
588 + info->pixmap.scan_align - 1;
b0a318e2 589 width >>= 2;
e7f76df9
KH		 590
591 while (width >= PM3_FIFO_SIZE) {
592 int i = PM3_FIFO_SIZE - 1;
593
594 PM3_WAIT(par, PM3_FIFO_SIZE);
595 while (i--) {
596 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
597 src++;
598 }
599 width -= PM3_FIFO_SIZE - 1;
600 }
601
602 PM3_WAIT(par, width + 1);
603 while (width--) {
604 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
605 src++;
606 }
607 }
608}
a58d67ce
KH		 609/* end of acceleration functions */
610
1d677a6d
KH		 611/*
612 * Hardware Cursor support.
613 */
614static const u8 cursor_bits_lookup[16] = {
615 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
616 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
617};
618
619static int pm3fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
620{
621 struct pm3_par *par = info->par;
622 u8 mode;
623
624 if (!hwcursor)
625 return -EINVAL; /* just to force soft_cursor() call */
626
627 /* Too large of a cursor or wrong bpp :-( */
628 if (cursor->image.width > 64 ||
629 cursor->image.height > 64 ||
630 cursor->image.depth > 1)
631 return -EINVAL;
632
633 mode = PM3RD_CursorMode_TYPE_X;
634 if (cursor->enable)
635 mode |= PM3RD_CursorMode_CURSOR_ENABLE;
636
637 PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, mode);
638
639 /*
640 * If the cursor is not be changed this means either we want the
641 * current cursor state (if enable is set) or we want to query what
642 * we can do with the cursor (if enable is not set)
643 */
644 if (!cursor->set)
645 return 0;
646
647 if (cursor->set & FB_CUR_SETPOS) {
648 int x = cursor->image.dx - info->var.xoffset;
649 int y = cursor->image.dy - info->var.yoffset;
650
651 PM3_WRITE_DAC_REG(par, PM3RD_CursorXLow, x & 0xff);
652 PM3_WRITE_DAC_REG(par, PM3RD_CursorXHigh, (x >> 8) & 0xf);
653 PM3_WRITE_DAC_REG(par, PM3RD_CursorYLow, y & 0xff);
654 PM3_WRITE_DAC_REG(par, PM3RD_CursorYHigh, (y >> 8) & 0xf);
655 }
656
657 if (cursor->set & FB_CUR_SETHOT) {
658 PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotX,
659 cursor->hot.x & 0x3f);
660 PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotY,
661 cursor->hot.y & 0x3f);
662 }
663
664 if (cursor->set & FB_CUR_SETCMAP) {
665 u32 fg_idx = cursor->image.fg_color;
666 u32 bg_idx = cursor->image.bg_color;
667 struct fb_cmap cmap = info->cmap;
668
669 /* the X11 driver says one should use these color registers */
670 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(39),
671 cmap.red[fg_idx] >> 8 );
672 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(40),
673 cmap.green[fg_idx] >> 8 );
674 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(41),
675 cmap.blue[fg_idx] >> 8 );
676
677 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(42),
678 cmap.red[bg_idx] >> 8 );
679 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(43),
680 cmap.green[bg_idx] >> 8 );
681 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(44),
682 cmap.blue[bg_idx] >> 8 );
683 }
684
685 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
686 u8 *bitmap = (u8 *)cursor->image.data;
687 u8 *mask = (u8 *)cursor->mask;
688 int i;
689 int pos = PM3RD_CursorPattern(0);
690
691 for (i = 0; i < cursor->image.height; i++) {
692 int j = (cursor->image.width + 7) >> 3;
693 int k = 8 - j;
694
695 for (; j > 0; j--) {
696 u8 data = *bitmap ^ *mask;
697
698 if (cursor->rop == ROP_COPY)
699 data = *mask & *bitmap;
700 /* Upper 4 bits of bitmap data */
701 PM3_WRITE_DAC_REG(par, pos++,
702 cursor_bits_lookup[data >> 4] |
703 (cursor_bits_lookup[*mask >> 4] << 1));
704 /* Lower 4 bits of bitmap */
705 PM3_WRITE_DAC_REG(par, pos++,
706 cursor_bits_lookup[data & 0xf] |
707 (cursor_bits_lookup[*mask & 0xf] << 1));
708 bitmap++;
709 mask++;
710 }
711 for (; k > 0; k--) {
712 PM3_WRITE_DAC_REG(par, pos++, 0);
713 PM3_WRITE_DAC_REG(par, pos++, 0);
714 }
715 }
716 while (pos < PM3RD_CursorPattern(1024))
717 PM3_WRITE_DAC_REG(par, pos++, 0);
718 }
719 return 0;
720}
721
1da177e4 722/* write the mode to registers */
f23a06f0 723static void pm3fb_write_mode(struct fb_info *info)
1da177e4 724{
f23a06f0 725 struct pm3_par *par = info->par;
57bac0f0
KH		 726 char tempsync = 0x00;
727 char tempmisc = 0x00;
f23a06f0
KH		 728 const u32 hsstart = info->var.right_margin;
729 const u32 hsend = hsstart + info->var.hsync_len;
730 const u32 hbend = hsend + info->var.left_margin;
731 const u32 xres = (info->var.xres + 31) & ~31;
732 const u32 htotal = xres + hbend;
733 const u32 vsstart = info->var.lower_margin;
734 const u32 vsend = vsstart + info->var.vsync_len;
735 const u32 vbend = vsend + info->var.upper_margin;
736 const u32 vtotal = info->var.yres + vbend;
737 const u32 width = (info->var.xres_virtual + 7) & ~7;
2686ba89
KH		 738 const unsigned bpp = info->var.bits_per_pixel;
739
740 PM3_WAIT(par, 20);
741 PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
742 PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
743 PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
744 PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
745
746 PM3_WRITE_REG(par, PM3HTotal,
747 pm3fb_shift_bpp(bpp, htotal - 1));
748 PM3_WRITE_REG(par, PM3HsEnd,
749 pm3fb_shift_bpp(bpp, hsend));
750 PM3_WRITE_REG(par, PM3HsStart,
751 pm3fb_shift_bpp(bpp, hsstart));
752 PM3_WRITE_REG(par, PM3HbEnd,
753 pm3fb_shift_bpp(bpp, hbend));
754 PM3_WRITE_REG(par, PM3HgEnd,
755 pm3fb_shift_bpp(bpp, hbend));
756 PM3_WRITE_REG(par, PM3ScreenStride,
757 pm3fb_shift_bpp(bpp, width));
758 PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
759 PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
760 PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
761 PM3_WRITE_REG(par, PM3VbEnd, vbend);
762
763 switch (bpp) {
1da177e4 764 case 8:
2686ba89 765 PM3_WRITE_REG(par, PM3ByAperture1Mode,
1da177e4 766 PM3ByApertureMode_PIXELSIZE_8BIT);
2686ba89 767 PM3_WRITE_REG(par, PM3ByAperture2Mode,
1da177e4
LT		 768 PM3ByApertureMode_PIXELSIZE_8BIT);
769 break;
770
1da177e4
LT		 771 case 16:
772#ifndef __BIG_ENDIAN
2686ba89 773 PM3_WRITE_REG(par, PM3ByAperture1Mode,
1da177e4 774 PM3ByApertureMode_PIXELSIZE_16BIT);
2686ba89 775 PM3_WRITE_REG(par, PM3ByAperture2Mode,
1da177e4
LT		 776 PM3ByApertureMode_PIXELSIZE_16BIT);
777#else
2686ba89 778 PM3_WRITE_REG(par, PM3ByAperture1Mode,
1da177e4
LT		 779 PM3ByApertureMode_PIXELSIZE_16BIT |
780 PM3ByApertureMode_BYTESWAP_BADC);
2686ba89 781 PM3_WRITE_REG(par, PM3ByAperture2Mode,
1da177e4
LT		 782 PM3ByApertureMode_PIXELSIZE_16BIT |
783 PM3ByApertureMode_BYTESWAP_BADC);
784#endif /* ! __BIG_ENDIAN */
785 break;
786
787 case 32:
788#ifndef __BIG_ENDIAN
2686ba89 789 PM3_WRITE_REG(par, PM3ByAperture1Mode,
1da177e4 790 PM3ByApertureMode_PIXELSIZE_32BIT);
2686ba89 791 PM3_WRITE_REG(par, PM3ByAperture2Mode,
1da177e4
LT		 792 PM3ByApertureMode_PIXELSIZE_32BIT);
793#else
2686ba89 794 PM3_WRITE_REG(par, PM3ByAperture1Mode,
1da177e4
LT		 795 PM3ByApertureMode_PIXELSIZE_32BIT |
796 PM3ByApertureMode_BYTESWAP_DCBA);
2686ba89 797 PM3_WRITE_REG(par, PM3ByAperture2Mode,
1da177e4
LT		 798 PM3ByApertureMode_PIXELSIZE_32BIT |
799 PM3ByApertureMode_BYTESWAP_DCBA);
800#endif /* ! __BIG_ENDIAN */
801 break;
802
803 default:
2686ba89 804 DPRINTK("Unsupported depth %d\n", bpp);
1da177e4
LT		 805 break;
806 }
807
808 /*
809 * Oxygen VX1 - it appears that setting PM3VideoControl and
810 * then PM3RD_SyncControl to the same SYNC settings undoes
811 * any net change - they seem to xor together. Only set the
812 * sync options in PM3RD_SyncControl. --rmk
813 */
814 {
f23a06f0 815 unsigned int video = par->video;
1da177e4
LT		 816
817 video &= ~(PM3VideoControl_HSYNC_MASK |
818 PM3VideoControl_VSYNC_MASK);
819 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
820 PM3VideoControl_VSYNC_ACTIVE_HIGH;
2686ba89 821 PM3_WRITE_REG(par, PM3VideoControl, video);
1da177e4 822 }
2686ba89 823 PM3_WRITE_REG(par, PM3VClkCtl,
f23a06f0 824 (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
2686ba89
KH		 825 PM3_WRITE_REG(par, PM3ScreenBase, par->base);
826 PM3_WRITE_REG(par, PM3ChipConfig,
f23a06f0 827 (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
1da177e4 828
2686ba89 829 wmb();
1da177e4 830 {
f23a06f0
KH		 831 unsigned char uninitialized_var(m); /* ClkPreScale */
832 unsigned char uninitialized_var(n); /* ClkFeedBackScale */
833 unsigned char uninitialized_var(p); /* ClkPostScale */
834 unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
835
836 (void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
837
838 DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
839 pixclock, (int) m, (int) n, (int) p);
840
841 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
842 PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
843 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
1da177e4
LT		 844 }
845 /*
f23a06f0 846 PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
1da177e4
LT		 847 */
848 /*
f23a06f0 849 PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
1da177e4 850 */
f23a06f0 851 if ((par->video & PM3VideoControl_HSYNC_MASK) ==
1da177e4
LT		 852 PM3VideoControl_HSYNC_ACTIVE_HIGH)
853 tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
f23a06f0 854 if ((par->video & PM3VideoControl_VSYNC_MASK) ==
1da177e4
LT		 855 PM3VideoControl_VSYNC_ACTIVE_HIGH)
856 tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
1da177e4 857
f23a06f0
KH		 858 PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
859 DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
860
861 PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
862
2686ba89 863 switch (pm3fb_depth(&info->var)) {
1da177e4 864 case 8:
f23a06f0 865 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
1da177e4 866 PM3RD_PixelSize_8_BIT_PIXELS);
f23a06f0 867 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
1da177e4
LT		 868 PM3RD_ColorFormat_CI8_COLOR |
869 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
870 tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
871 break;
872 case 12:
f23a06f0 873 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
1da177e4 874 PM3RD_PixelSize_16_BIT_PIXELS);
f23a06f0 875 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
1da177e4
LT		 876 PM3RD_ColorFormat_4444_COLOR |
877 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
878 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
879 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
880 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
f23a06f0 881 break;
1da177e4 882 case 15:
f23a06f0 883 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
1da177e4 884 PM3RD_PixelSize_16_BIT_PIXELS);
f23a06f0 885 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
1da177e4
LT		 886 PM3RD_ColorFormat_5551_FRONT_COLOR |
887 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
888 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
889 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
890 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
f23a06f0 891 break;
1da177e4 892 case 16:
f23a06f0 893 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
1da177e4 894 PM3RD_PixelSize_16_BIT_PIXELS);
f23a06f0 895 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
1da177e4
LT		 896 PM3RD_ColorFormat_565_FRONT_COLOR |
897 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
898 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
899 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
900 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
901 break;
902 case 32:
f23a06f0 903 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
1da177e4 904 PM3RD_PixelSize_32_BIT_PIXELS);
f23a06f0 905 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
1da177e4
LT		 906 PM3RD_ColorFormat_8888_COLOR |
907 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
908 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
909 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
910 break;
911 }
f23a06f0 912 PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
1da177e4
LT		 913}
914
f23a06f0
KH		 915/*
916 * hardware independent functions
917 */
f23a06f0
KH		 918static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
919{
920 u32 lpitch;
2686ba89
KH		 921 unsigned bpp = var->red.length + var->green.length
922 + var->blue.length + var->transp.length;
1da177e4 923
0ddf7849 924 if (bpp != var->bits_per_pixel) {
2686ba89
KH		 925 /* set predefined mode for bits_per_pixel settings */
926
57bac0f0 927 switch (var->bits_per_pixel) {
2686ba89 928 case 8:
57bac0f0
KH		 929 var->red.length = 8;
930 var->green.length = 8;
931 var->blue.length = 8;
932 var->red.offset = 0;
933 var->green.offset = 0;
934 var->blue.offset = 0;
2686ba89
KH		 935 var->transp.offset = 0;
936 var->transp.length = 0;
937 break;
938 case 16:
57bac0f0
KH		 939 var->red.length = 5;
940 var->blue.length = 5;
2686ba89
KH		 941 var->green.length = 6;
942 var->transp.length = 0;
943 break;
944 case 32:
57bac0f0
KH		 945 var->red.length = 8;
946 var->green.length = 8;
947 var->blue.length = 8;
2686ba89
KH		 948 var->transp.length = 8;
949 break;
950 default:
57bac0f0
KH		 951 DPRINTK("depth not supported: %u\n",
952 var->bits_per_pixel);
2686ba89
KH		 953 return -EINVAL;
954 }
955 }
956 /* it is assumed BGRA order */
57bac0f0 957 if (var->bits_per_pixel > 8 ) {
2686ba89
KH		 958 var->blue.offset = 0;
959 var->green.offset = var->blue.length;
960 var->red.offset = var->green.offset + var->green.length;
961 var->transp.offset = var->red.offset + var->red.length;
1da177e4 962 }
57bac0f0
KH		 963 var->height = -1;
964 var->width = -1;
1da177e4 965
f23a06f0 966 if (var->xres != var->xres_virtual) {
57bac0f0
KH		 967 DPRINTK("virtual x resolution != "
968 "physical x resolution not supported\n");
f23a06f0
KH		 969 return -EINVAL;
970 }
1da177e4 971
f23a06f0 972 if (var->yres > var->yres_virtual) {
57bac0f0
KH		 973 DPRINTK("virtual y resolution < "
974 "physical y resolution not possible\n");
f23a06f0 975 return -EINVAL;
1da177e4 976 }
1da177e4 977
f23a06f0
KH		 978 if (var->xoffset) {
979 DPRINTK("xoffset not supported\n");
980 return -EINVAL;
1da177e4
LT		 981 }
982
f23a06f0
KH		 983 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
984 DPRINTK("interlace not supported\n");
985 return -EINVAL;
1da177e4 986 }
1da177e4 987
f23a06f0 988 var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
0ddf7849 989 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
1da177e4 990
f23a06f0
KH		 991 if (var->xres < 200 || var->xres > 2048) {
992 DPRINTK("width not supported: %u\n", var->xres);
993 return -EINVAL;
994 }
1da177e4 995
f23a06f0
KH		 996 if (var->yres < 200 || var->yres > 4095) {
997 DPRINTK("height not supported: %u\n", var->yres);
998 return -EINVAL;
999 }
1da177e4 1000
f23a06f0
KH		 1001 if (lpitch * var->yres_virtual > info->fix.smem_len) {
1002 DPRINTK("no memory for screen (%ux%ux%u)\n",
1003 var->xres, var->yres_virtual, var->bits_per_pixel);
1004 return -EINVAL;
1005 }
1006
1007 if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
57bac0f0
KH		 1008 DPRINTK("pixclock too high (%ldKHz)\n",
1009 PICOS2KHZ(var->pixclock));
f23a06f0 1010 return -EINVAL;
1da177e4
LT		 1011 }
1012
f23a06f0 1013 var->accel_flags = 0; /* Can't mmap if this is on */
1da177e4 1014
f23a06f0
KH		 1015 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
1016 var->xres, var->yres, var->bits_per_pixel);
1017 return 0;
1018}
1da177e4 1019
f23a06f0
KH		 1020static int pm3fb_set_par(struct fb_info *info)
1021{
1022 struct pm3_par *par = info->par;
1023 const u32 xres = (info->var.xres + 31) & ~31;
2686ba89 1024 const unsigned bpp = info->var.bits_per_pixel;
1da177e4 1025
57bac0f0 1026 par->base = pm3fb_shift_bpp(bpp, (info->var.yoffset * xres)
f23a06f0
KH		 1027 + info->var.xoffset);
1028 par->video = 0;
1da177e4 1029
f23a06f0
KH		 1030 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
1031 par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
1032 else
1033 par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
1da177e4 1034
f23a06f0
KH		 1035 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
1036 par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
1037 else
1038 par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
1da177e4 1039
f23a06f0
KH		 1040 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
1041 par->video |= PM3VideoControl_LINE_DOUBLE_ON;
1da177e4 1042
0bd327ef 1043 if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
f23a06f0 1044 par->video |= PM3VideoControl_ENABLE;
0ddf7849 1045 else
f23a06f0 1046 DPRINTK("PM3Video disabled\n");
0ddf7849 1047
2686ba89 1048 switch (bpp) {
f23a06f0
KH		 1049 case 8:
1050 par->video |= PM3VideoControl_PIXELSIZE_8BIT;
1051 break;
f23a06f0
KH		 1052 case 16:
1053 par->video |= PM3VideoControl_PIXELSIZE_16BIT;
1054 break;
1055 case 32:
1056 par->video |= PM3VideoControl_PIXELSIZE_32BIT;
1057 break;
1058 default:
1059 DPRINTK("Unsupported depth\n");
1060 break;
1da177e4 1061 }
1da177e4 1062
f23a06f0 1063 info->fix.visual =
2686ba89 1064 (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
0ddf7849 1065 info->fix.line_length = ((info->var.xres_virtual + 7) >> 3) * bpp;
1da177e4 1066
f23a06f0
KH		 1067/* pm3fb_clear_memory(info, 0);*/
1068 pm3fb_clear_colormap(par, 0, 0, 0);
f259ebb6 1069 PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0);
a58d67ce 1070 pm3fb_init_engine(info);
f23a06f0
KH		 1071 pm3fb_write_mode(info);
1072 return 0;
1da177e4
LT		 1073}
1074
f23a06f0
KH		 1075static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1076 unsigned blue, unsigned transp,
1077 struct fb_info *info)
1da177e4 1078{
f23a06f0
KH		 1079 struct pm3_par *par = info->par;
1080
1081 if (regno >= 256) /* no. of hw registers */
1082 return -EINVAL;
1083
1084 /* grayscale works only partially under directcolor */
57bac0f0
KH		 1085 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
1086 if (info->var.grayscale)
f23a06f0 1087 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
f23a06f0
KH		 1088
1089 /* Directcolor:
1090 * var->{color}.offset contains start of bitfield
1091 * var->{color}.length contains length of bitfield
1092 * {hardwarespecific} contains width of DAC
1093 * pseudo_palette[X] is programmed to (X << red.offset) |
2686ba89
KH		 1094 * (X << green.offset) |
1095 * (X << blue.offset)
f23a06f0
KH		 1096 * RAMDAC[X] is programmed to (red, green, blue)
1097 * color depth = SUM(var->{color}.length)
1098 *
1099 * Pseudocolor:
1100 * var->{color}.offset is 0
57bac0f0
KH		 1101 * var->{color}.length contains width of DAC or the number
1102 * of unique colors available (color depth)
f23a06f0
KH		 1103 * pseudo_palette is not used
1104 * RAMDAC[X] is programmed to (red, green, blue)
1105 * color depth = var->{color}.length
1106 */
1da177e4 1107
f23a06f0
KH		 1108 /*
1109 * This is the point where the color is converted to something that
1110 * is acceptable by the hardware.
1111 */
57bac0f0 1112#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
f23a06f0
KH		 1113 red = CNVT_TOHW(red, info->var.red.length);
1114 green = CNVT_TOHW(green, info->var.green.length);
1115 blue = CNVT_TOHW(blue, info->var.blue.length);
1116 transp = CNVT_TOHW(transp, info->var.transp.length);
1117#undef CNVT_TOHW
1118
1119 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
1120 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1121 u32 v;
1122
1123 if (regno >= 16)
1124 return -EINVAL;
1125
1126 v = (red << info->var.red.offset) |
1127 (green << info->var.green.offset) |
1128 (blue << info->var.blue.offset) |
1129 (transp << info->var.transp.offset);
1130
1131 switch (info->var.bits_per_pixel) {
1132 case 8:
1133 break;
1134 case 16:
f23a06f0 1135 case 32:
57bac0f0 1136 ((u32 *)(info->pseudo_palette))[regno] = v;
f23a06f0
KH		 1137 break;
1138 }
1139 return 0;
57bac0f0 1140 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
f23a06f0 1141 pm3fb_set_color(par, regno, red, green, blue);
1da177e4 1142
f23a06f0 1143 return 0;
1da177e4
LT		 1144}
1145
f23a06f0
KH		 1146static int pm3fb_pan_display(struct fb_var_screeninfo *var,
1147 struct fb_info *info)
1da177e4 1148{
f23a06f0 1149 struct pm3_par *par = info->par;
1fdb518f 1150 const u32 xres = (info->var.xres + 31) & ~31;
1da177e4 1151
1fdb518f 1152 par->base = pm3fb_shift_bpp(info->var.bits_per_pixel,
f23a06f0
KH		 1153 (var->yoffset * xres)
1154 + var->xoffset);
2686ba89
KH		 1155 PM3_WAIT(par, 1);
1156 PM3_WRITE_REG(par, PM3ScreenBase, par->base);
f23a06f0
KH		 1157 return 0;
1158}
1da177e4 1159
f23a06f0
KH		 1160static int pm3fb_blank(int blank_mode, struct fb_info *info)
1161{
1162 struct pm3_par *par = info->par;
1163 u32 video = par->video;
1da177e4 1164
f23a06f0
KH		 1165 /*
1166 * Oxygen VX1 - it appears that setting PM3VideoControl and
1167 * then PM3RD_SyncControl to the same SYNC settings undoes
1168 * any net change - they seem to xor together. Only set the
1169 * sync options in PM3RD_SyncControl. --rmk
1170 */
1171 video &= ~(PM3VideoControl_HSYNC_MASK |
1172 PM3VideoControl_VSYNC_MASK);
1173 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
1174 PM3VideoControl_VSYNC_ACTIVE_HIGH;
1da177e4 1175
f23a06f0
KH		 1176 switch (blank_mode) {
1177 case FB_BLANK_UNBLANK:
2686ba89 1178 video |= PM3VideoControl_ENABLE;
f23a06f0 1179 break;
2686ba89 1180 case FB_BLANK_NORMAL:
0ddf7849 1181 video &= ~PM3VideoControl_ENABLE;
f23a06f0
KH		 1182 break;
1183 case FB_BLANK_HSYNC_SUSPEND:
2686ba89
KH		 1184 video &= ~(PM3VideoControl_HSYNC_MASK |
1185 PM3VideoControl_BLANK_ACTIVE_LOW);
f23a06f0
KH		 1186 break;
1187 case FB_BLANK_VSYNC_SUSPEND:
2686ba89
KH		 1188 video &= ~(PM3VideoControl_VSYNC_MASK |
1189 PM3VideoControl_BLANK_ACTIVE_LOW);
f23a06f0
KH		 1190 break;
1191 case FB_BLANK_POWERDOWN:
2686ba89
KH		 1192 video &= ~(PM3VideoControl_HSYNC_MASK |
1193 PM3VideoControl_VSYNC_MASK |
1194 PM3VideoControl_BLANK_ACTIVE_LOW);
f23a06f0
KH		 1195 break;
1196 default:
1197 DPRINTK("Unsupported blanking %d\n", blank_mode);
1198 return 1;
1da177e4
LT		 1199 }
1200
2686ba89 1201 PM3_WAIT(par, 1);
57bac0f0 1202 PM3_WRITE_REG(par, PM3VideoControl, video);
f23a06f0 1203 return 0;
1da177e4
LT		 1204}
1205
f23a06f0
KH		 1206 /*
1207 * Frame buffer operations
1208 */
1da177e4 1209
f23a06f0
KH		 1210static struct fb_ops pm3fb_ops = {
1211 .owner = THIS_MODULE,
1212 .fb_check_var = pm3fb_check_var,
1213 .fb_set_par = pm3fb_set_par,
1214 .fb_setcolreg = pm3fb_setcolreg,
1215 .fb_pan_display = pm3fb_pan_display,
a58d67ce 1216 .fb_fillrect = pm3fb_fillrect,
e7f76df9
KH		 1217 .fb_copyarea = pm3fb_copyarea,
1218 .fb_imageblit = pm3fb_imageblit,
f23a06f0 1219 .fb_blank = pm3fb_blank,
a58d67ce 1220 .fb_sync = pm3fb_sync,
1d677a6d 1221 .fb_cursor = pm3fb_cursor,
f23a06f0 1222};
1da177e4 1223
f23a06f0 1224/* ------------------------------------------------------------------------- */
1da177e4 1225
f23a06f0
KH		 1226 /*
1227 * Initialization
1228 */
1da177e4 1229
f23a06f0
KH		 1230/* mmio register are already mapped when this function is called */
1231/* the pm3fb_fix.smem_start is also set */
48c68c4f 1232static unsigned long pm3fb_size_memory(struct pm3_par *par)
1da177e4 1233{
57bac0f0
KH		 1234 unsigned long memsize = 0;
1235 unsigned long tempBypass, i, temp1, temp2;
f23a06f0 1236 unsigned char __iomem *screen_mem;
1da177e4 1237
2686ba89 1238 pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
f23a06f0
KH		 1239 /* Linear frame buffer - request region and map it. */
1240 if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1241 "pm3fb smem")) {
1242 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1243 return 0;
1da177e4 1244 }
f23a06f0
KH		 1245 screen_mem =
1246 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1247 if (!screen_mem) {
1248 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1249 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1250 return 0;
1da177e4
LT		 1251 }
1252
f23a06f0
KH		 1253 /* TODO: card-specific stuff, *before* accessing *any* FB memory */
1254 /* For Appian Jeronimo 2000 board second head */
1da177e4 1255
f23a06f0 1256 tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
1da177e4 1257
f23a06f0 1258 DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
1da177e4 1259
2686ba89
KH		 1260 PM3_WAIT(par, 1);
1261 PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
1da177e4 1262
57bac0f0
KH		 1263 /* pm3 split up memory, replicates, and do a lot of
1264 * nasty stuff IMHO ;-)
1265 */
f23a06f0
KH		 1266 for (i = 0; i < 32; i++) {
1267 fb_writel(i * 0x00345678,
1268 (screen_mem + (i * 1048576)));
1269 mb();
1270 temp1 = fb_readl((screen_mem + (i * 1048576)));
1da177e4 1271
f23a06f0
KH		 1272 /* Let's check for wrapover, write will fail at 16MB boundary */
1273 if (temp1 == (i * 0x00345678))
1274 memsize = i;
1da177e4 1275 else
f23a06f0 1276 break;
1da177e4 1277 }
1da177e4 1278
f23a06f0 1279 DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
1da177e4 1280
f23a06f0
KH		 1281 if (memsize + 1 == i) {
1282 for (i = 0; i < 32; i++) {
1283 /* Clear first 32MB ; 0 is 0, no need to byteswap */
2686ba89 1284 writel(0x0000000, (screen_mem + (i * 1048576)));
1da177e4 1285 }
2686ba89 1286 wmb();
1da177e4 1287
f23a06f0
KH		 1288 for (i = 32; i < 64; i++) {
1289 fb_writel(i * 0x00345678,
1290 (screen_mem + (i * 1048576)));
1291 mb();
1292 temp1 =
1293 fb_readl((screen_mem + (i * 1048576)));
1294 temp2 =
1295 fb_readl((screen_mem + ((i - 32) * 1048576)));
1296 /* different value, different RAM... */
1297 if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
1298 memsize = i;
1299 else
1300 break;
1da177e4 1301 }
1da177e4 1302 }
f23a06f0 1303 DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
1da177e4 1304
2686ba89
KH		 1305 PM3_WAIT(par, 1);
1306 PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
1da177e4 1307
f23a06f0
KH		 1308 iounmap(screen_mem);
1309 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1310 memsize = 1048576 * (memsize + 1);
1da177e4 1311
f23a06f0 1312 DPRINTK("Returning 0x%08lx bytes\n", memsize);
1da177e4 1313
f23a06f0 1314 return memsize;
1da177e4
LT		 1315}
1316
48c68c4f 1317static int pm3fb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1da177e4 1318{
f23a06f0
KH		 1319 struct fb_info *info;
1320 struct pm3_par *par;
57bac0f0
KH		 1321 struct device *device = &dev->dev; /* for pci drivers */
1322 int err;
1323 int retval = -ENXIO;
1da177e4 1324
f23a06f0
KH		 1325 err = pci_enable_device(dev);
1326 if (err) {
1327 printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
1328 return err;
1da177e4 1329 }
f23a06f0
KH		 1330 /*
1331 * Dynamically allocate info and par
1332 */
1333 info = framebuffer_alloc(sizeof(struct pm3_par), device);
1da177e4 1334
f23a06f0
KH		 1335 if (!info)
1336 return -ENOMEM;
1337 par = info->par;
1da177e4 1338
f23a06f0
KH		 1339 /*
1340 * Here we set the screen_base to the virtual memory address
1341 * for the framebuffer.
1342 */
1343 pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
1344 pm3fb_fix.mmio_len = PM3_REGS_SIZE;
c79ba28c
KH		 1345#if defined(__BIG_ENDIAN)
1346 pm3fb_fix.mmio_start += PM3_REGS_SIZE;
1347 DPRINTK("Adjusting register base for big-endian.\n");
1348#endif
f23a06f0
KH		 1349
1350 /* Registers - request region and map it. */
1351 if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
1352 "pm3fb regbase")) {
1353 printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
1354 goto err_exit_neither;
1355 }
1356 par->v_regs =
1357 ioremap_nocache(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1358 if (!par->v_regs) {
1359 printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
1360 pm3fb_fix.id);
1361 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1362 goto err_exit_neither;
1363 }
1364
f23a06f0
KH		 1365 /* Linear frame buffer - request region and map it. */
1366 pm3fb_fix.smem_start = pci_resource_start(dev, 1);
1367 pm3fb_fix.smem_len = pm3fb_size_memory(par);
57bac0f0 1368 if (!pm3fb_fix.smem_len) {
f23a06f0
KH		 1369 printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
1370 goto err_exit_mmio;
1da177e4 1371 }
f23a06f0
KH		 1372 if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1373 "pm3fb smem")) {
1374 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1375 goto err_exit_mmio;
1da177e4 1376 }
f23a06f0
KH		 1377 info->screen_base =
1378 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1379 if (!info->screen_base) {
1380 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1381 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1382 goto err_exit_mmio;
1da177e4 1383 }
f23a06f0 1384 info->screen_size = pm3fb_fix.smem_len;
1da177e4 1385
d5383fcc 1386#ifdef CONFIG_MTRR
57bac0f0 1387 if (!nomtrr)
d5383fcc
KH		 1388 par->mtrr_handle = mtrr_add(pm3fb_fix.smem_start,
1389 pm3fb_fix.smem_len,
1390 MTRR_TYPE_WRCOMB, 1);
d5383fcc 1391#endif
f23a06f0 1392 info->fbops = &pm3fb_ops;
1da177e4 1393
f23a06f0 1394 par->video = PM3_READ_REG(par, PM3VideoControl);
1da177e4 1395
f23a06f0
KH		 1396 info->fix = pm3fb_fix;
1397 info->pseudo_palette = par->palette;
a58d67ce 1398 info->flags = FBINFO_DEFAULT |
c79ba28c
KH		 1399 FBINFO_HWACCEL_XPAN |
1400 FBINFO_HWACCEL_YPAN |
e7f76df9
KH		 1401 FBINFO_HWACCEL_COPYAREA |
1402 FBINFO_HWACCEL_IMAGEBLIT |
1403 FBINFO_HWACCEL_FILLRECT;
1da177e4 1404
d5383fcc 1405 if (noaccel) {
57bac0f0
KH		 1406 printk(KERN_DEBUG "disabling acceleration\n");
1407 info->flags |= FBINFO_HWACCEL_DISABLED;
d5383fcc 1408 }
b0a318e2
KH		 1409 info->pixmap.addr = kmalloc(PM3_PIXMAP_SIZE, GFP_KERNEL);
1410 if (!info->pixmap.addr) {
1411 retval = -ENOMEM;
1412 goto err_exit_pixmap;
1413 }
1414 info->pixmap.size = PM3_PIXMAP_SIZE;
1415 info->pixmap.buf_align = 4;
1416 info->pixmap.scan_align = 4;
1417 info->pixmap.access_align = 32;
1418 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1419
f23a06f0
KH		 1420 /*
1421 * This should give a reasonable default video mode. The following is
1422 * done when we can set a video mode.
1423 */
1424 if (!mode_option)
1425 mode_option = "640x480@60";
1da177e4 1426
f23a06f0 1427 retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1da177e4 1428
f23a06f0
KH		 1429 if (!retval || retval == 4) {
1430 retval = -EINVAL;
1431 goto err_exit_both;
1da177e4 1432 }
1da177e4 1433
f23a06f0
KH		 1434 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1435 retval = -ENOMEM;
1436 goto err_exit_both;
1da177e4 1437 }
1da177e4 1438
f23a06f0
KH		 1439 /*
1440 * For drivers that can...
1441 */
1442 pm3fb_check_var(&info->var, info);
1da177e4 1443
f23a06f0
KH		 1444 if (register_framebuffer(info) < 0) {
1445 retval = -EINVAL;
1446 goto err_exit_all;
1da177e4 1447 }
f23a06f0
KH		 1448 printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
1449 info->fix.id);
2686ba89 1450 pci_set_drvdata(dev, info);
f23a06f0 1451 return 0;
1da177e4 1452
f23a06f0
KH		 1453 err_exit_all:
1454 fb_dealloc_cmap(&info->cmap);
1455 err_exit_both:
b0a318e2
KH		 1456 kfree(info->pixmap.addr);
1457 err_exit_pixmap:
f23a06f0
KH		 1458 iounmap(info->screen_base);
1459 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1460 err_exit_mmio:
1461 iounmap(par->v_regs);
1462 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1463 err_exit_neither:
1464 framebuffer_release(info);
1465 return retval;
1da177e4
LT		 1466}
1467
f23a06f0
KH		 1468 /*
1469 * Cleanup
1470 */
48c68c4f 1471static void pm3fb_remove(struct pci_dev *dev)
1da177e4 1472{
f23a06f0 1473 struct fb_info *info = pci_get_drvdata(dev);
1da177e4 1474
f23a06f0
KH		 1475 if (info) {
1476 struct fb_fix_screeninfo *fix = &info->fix;
1477 struct pm3_par *par = info->par;
1da177e4 1478
f23a06f0
KH		 1479 unregister_framebuffer(info);
1480 fb_dealloc_cmap(&info->cmap);
1da177e4 1481
d5383fcc
KH		 1482#ifdef CONFIG_MTRR
1483 if (par->mtrr_handle >= 0)
1484 mtrr_del(par->mtrr_handle, info->fix.smem_start,
1485 info->fix.smem_len);
1486#endif /* CONFIG_MTRR */
f23a06f0
KH		 1487 iounmap(info->screen_base);
1488 release_mem_region(fix->smem_start, fix->smem_len);
1489 iounmap(par->v_regs);
1490 release_mem_region(fix->mmio_start, fix->mmio_len);
1da177e4 1491
f23a06f0 1492 pci_set_drvdata(dev, NULL);
b0a318e2 1493 kfree(info->pixmap.addr);
f23a06f0 1494 framebuffer_release(info);
1da177e4 1495 }
1da177e4
LT		 1496}
1497
f23a06f0
KH		 1498static struct pci_device_id pm3fb_id_table[] = {
1499 { PCI_VENDOR_ID_3DLABS, 0x0a,
2686ba89 1500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
f23a06f0
KH		 1501 { 0, }
1502};
1da177e4 1503
f23a06f0
KH		 1504/* For PCI drivers */
1505static struct pci_driver pm3fb_driver = {
1506 .name = "pm3fb",
1507 .id_table = pm3fb_id_table,
1508 .probe = pm3fb_probe,
48c68c4f 1509 .remove = pm3fb_remove,
f23a06f0 1510};
1da177e4 1511
f23a06f0 1512MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
1da177e4 1513
d5383fcc
KH		 1514#ifndef MODULE
1515 /*
1516 * Setup
1517 */
1518
1519/*
1520 * Only necessary if your driver takes special options,
1521 * otherwise we fall back on the generic fb_setup().
1522 */
1523static int __init pm3fb_setup(char *options)
1524{
1525 char *this_opt;
1526
75e1b6a8 1527 /* Parse user specified options (`video=pm3fb:') */
d5383fcc
KH		 1528 if (!options || !*options)
1529 return 0;
1530
1531 while ((this_opt = strsep(&options, ",")) != NULL) {
1532 if (!*this_opt)
1533 continue;
57bac0f0 1534 else if (!strncmp(this_opt, "noaccel", 7))
d5383fcc 1535 noaccel = 1;
1d677a6d
KH		 1536 else if (!strncmp(this_opt, "hwcursor=", 9))
1537 hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
d5383fcc 1538#ifdef CONFIG_MTRR
57bac0f0 1539 else if (!strncmp(this_opt, "nomtrr", 6))
d5383fcc
KH		 1540 nomtrr = 1;
1541#endif
57bac0f0 1542 else
d5383fcc 1543 mode_option = this_opt;
d5383fcc
KH		 1544 }
1545 return 0;
1546}
1547#endif /* MODULE */
1548
b309c050 1549static int __init pm3fb_init(void)
2686ba89 1550{
d5383fcc
KH		 1551 /*
1552 * For kernel boot options (in 'video=pm3fb:<options>' format)
1553 */
f23a06f0 1554#ifndef MODULE
d5383fcc
KH		 1555 char *option = NULL;
1556
1557 if (fb_get_options("pm3fb", &option))
f23a06f0 1558 return -ENODEV;
d5383fcc 1559 pm3fb_setup(option);
1da177e4 1560#endif
d5383fcc 1561
f23a06f0 1562 return pci_register_driver(&pm3fb_driver);
1da177e4
LT		 1563}
1564
d5383fcc 1565#ifdef MODULE
f23a06f0 1566static void __exit pm3fb_exit(void)
1da177e4 1567{
f23a06f0 1568 pci_unregister_driver(&pm3fb_driver);
1da177e4
LT		 1569}
1570
f23a06f0 1571module_exit(pm3fb_exit);
d5383fcc
KH		 1572#endif
1573module_init(pm3fb_init);
1574
4e65c613
KH		 1575module_param(mode_option, charp, 0);
1576MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
d5383fcc
KH		 1577module_param(noaccel, bool, 0);
1578MODULE_PARM_DESC(noaccel, "Disable acceleration");
1d677a6d
KH		 1579module_param(hwcursor, int, 0644);
1580MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1581 "(1=enable, 0=disable, default=1)");
d5383fcc
KH		 1582#ifdef CONFIG_MTRR
1583module_param(nomtrr, bool, 0);
1584MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1585#endif
f23a06f0 1586
0ddf7849 1587MODULE_DESCRIPTION("Permedia3 framebuffer device driver");
f23a06f0 1588MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)