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Merge tag 'v3.6-rc4'
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
80c39712
TV		 40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
5ed8cf5b
TV		 66enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
80c39712
TV		 72#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
dfc0fd8d
TV		 78struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
dcbe765b
CM		 84struct dispc_features {
85 u8 sw_start;
86 u8 fp_start;
87 u8 bp_start;
88 u16 sw_max;
89 u16 vp_max;
90 u16 hp_max;
91 int (*calc_scaling) (enum omap_channel channel,
92 const struct omap_video_timings *mgr_timings,
93 u16 width, u16 height, u16 out_width, u16 out_height,
94 enum omap_color_mode color_mode, bool *five_taps,
95 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
96 u16 pos_x, unsigned long *core_clk);
97 unsigned long (*calc_core_clk) (enum omap_channel channel,
98 u16 width, u16 height, u16 out_width, u16 out_height);
99};
100
80c39712 101static struct {
060b6d9c 102 struct platform_device *pdev;
80c39712 103 void __iomem *base;
4fbafaf3
TV		 104
105 int ctx_loss_cnt;
106
affe360d 107 int irq;
4fbafaf3 108 struct clk *dss_clk;
80c39712 109
e13a138b 110 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 111
112 spinlock_t irq_lock;
113 u32 irq_error_mask;
114 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
115 u32 error_irqs;
116 struct work_struct error_work;
117
49ea86f3 118 bool ctx_valid;
80c39712 119 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 120
dcbe765b
CM		 121 const struct dispc_features *feat;
122
dfc0fd8d
TV		 123#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
124 spinlock_t irq_stats_lock;
125 struct dispc_irq_stats irq_stats;
126#endif
80c39712
TV		 127} dispc;
128
0d66cbb5
AJ		 129enum omap_color_component {
130 /* used for all color formats for OMAP3 and earlier
131 * and for RGB and Y color component on OMAP4
132 */
133 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
134 /* used for UV component for
135 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
136 * color formats on OMAP4
137 */
138 DISPC_COLOR_COMPONENT_UV = 1 << 1,
139};
140
efa70b3b
CM		 141enum mgr_reg_fields {
142 DISPC_MGR_FLD_ENABLE,
143 DISPC_MGR_FLD_STNTFT,
144 DISPC_MGR_FLD_GO,
145 DISPC_MGR_FLD_TFTDATALINES,
146 DISPC_MGR_FLD_STALLMODE,
147 DISPC_MGR_FLD_TCKENABLE,
148 DISPC_MGR_FLD_TCKSELECTION,
149 DISPC_MGR_FLD_CPR,
150 DISPC_MGR_FLD_FIFOHANDCHECK,
151 /* used to maintain a count of the above fields */
152 DISPC_MGR_FLD_NUM,
153};
154
155static const struct {
156 const char *name;
157 u32 vsync_irq;
158 u32 framedone_irq;
159 u32 sync_lost_irq;
160 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
161} mgr_desc[] = {
162 [OMAP_DSS_CHANNEL_LCD] = {
163 .name = "LCD",
164 .vsync_irq = DISPC_IRQ_VSYNC,
165 .framedone_irq = DISPC_IRQ_FRAMEDONE,
166 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
167 .reg_desc = {
168 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
169 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
170 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
171 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
172 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
173 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
174 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
175 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
176 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
177 },
178 },
179 [OMAP_DSS_CHANNEL_DIGIT] = {
180 .name = "DIGIT",
181 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
182 .framedone_irq = 0,
183 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
184 .reg_desc = {
185 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
186 [DISPC_MGR_FLD_STNTFT] = { },
187 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
188 [DISPC_MGR_FLD_TFTDATALINES] = { },
189 [DISPC_MGR_FLD_STALLMODE] = { },
190 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
191 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
192 [DISPC_MGR_FLD_CPR] = { },
193 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
194 },
195 },
196 [OMAP_DSS_CHANNEL_LCD2] = {
197 .name = "LCD2",
198 .vsync_irq = DISPC_IRQ_VSYNC2,
199 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
200 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
201 .reg_desc = {
202 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
203 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
204 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
205 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
206 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
207 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
208 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
209 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
210 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
211 },
212 },
e86d456a
CM		 213 [OMAP_DSS_CHANNEL_LCD3] = {
214 .name = "LCD3",
215 .vsync_irq = DISPC_IRQ_VSYNC3,
216 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
217 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
218 .reg_desc = {
219 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
220 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
221 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
222 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
223 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
224 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
225 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
226 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
227 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
228 },
229 },
efa70b3b
CM		 230};
231
80c39712
TV		 232static void _omap_dispc_set_irqs(void);
233
55978cc2 234static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 235{
55978cc2 236 __raw_writel(val, dispc.base + idx);
80c39712
TV		 237}
238
55978cc2 239static inline u32 dispc_read_reg(const u16 idx)
80c39712 240{
55978cc2 241 return __raw_readl(dispc.base + idx);
80c39712
TV		 242}
243
efa70b3b
CM		 244static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
245{
246 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
247 return REG_GET(rfld.reg, rfld.high, rfld.low);
248}
249
250static void mgr_fld_write(enum omap_channel channel,
251 enum mgr_reg_fields regfld, int val) {
252 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
253 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
254}
255
80c39712 256#define SR(reg) \
55978cc2 257 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 258#define RR(reg) \
55978cc2 259 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 260
4fbafaf3 261static void dispc_save_context(void)
80c39712 262{
c6104b8e 263 int i, j;
80c39712 264
4fbafaf3
TV		 265 DSSDBG("dispc_save_context\n");
266
80c39712
TV		 267 SR(IRQENABLE);
268 SR(CONTROL);
269 SR(CONFIG);
80c39712 270 SR(LINE_NUMBER);
11354dd5
AT		 271 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
272 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 273 SR(GLOBAL_ALPHA);
2a205f34
SS		 274 if (dss_has_feature(FEAT_MGR_LCD2)) {
275 SR(CONTROL2);
2a205f34
SS		 276 SR(CONFIG2);
277 }
e86d456a
CM		 278 if (dss_has_feature(FEAT_MGR_LCD3)) {
279 SR(CONTROL3);
280 SR(CONFIG3);
281 }
80c39712 282
c6104b8e
AT		 283 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
284 SR(DEFAULT_COLOR(i));
285 SR(TRANS_COLOR(i));
286 SR(SIZE_MGR(i));
287 if (i == OMAP_DSS_CHANNEL_DIGIT)
288 continue;
289 SR(TIMING_H(i));
290 SR(TIMING_V(i));
291 SR(POL_FREQ(i));
292 SR(DIVISORo(i));
293
294 SR(DATA_CYCLE1(i));
295 SR(DATA_CYCLE2(i));
296 SR(DATA_CYCLE3(i));
297
332e9d70 298 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 299 SR(CPR_COEF_R(i));
300 SR(CPR_COEF_G(i));
301 SR(CPR_COEF_B(i));
332e9d70 302 }
2a205f34 303 }
80c39712 304
c6104b8e
AT		 305 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
306 SR(OVL_BA0(i));
307 SR(OVL_BA1(i));
308 SR(OVL_POSITION(i));
309 SR(OVL_SIZE(i));
310 SR(OVL_ATTRIBUTES(i));
311 SR(OVL_FIFO_THRESHOLD(i));
312 SR(OVL_ROW_INC(i));
313 SR(OVL_PIXEL_INC(i));
314 if (dss_has_feature(FEAT_PRELOAD))
315 SR(OVL_PRELOAD(i));
316 if (i == OMAP_DSS_GFX) {
317 SR(OVL_WINDOW_SKIP(i));
318 SR(OVL_TABLE_BA(i));
319 continue;
320 }
321 SR(OVL_FIR(i));
322 SR(OVL_PICTURE_SIZE(i));
323 SR(OVL_ACCU0(i));
324 SR(OVL_ACCU1(i));
9b372c2d 325
c6104b8e
AT		 326 for (j = 0; j < 8; j++)
327 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 328
c6104b8e
AT		 329 for (j = 0; j < 8; j++)
330 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 331
c6104b8e
AT		 332 for (j = 0; j < 5; j++)
333 SR(OVL_CONV_COEF(i, j));
ab5ca071 334
c6104b8e
AT		 335 if (dss_has_feature(FEAT_FIR_COEF_V)) {
336 for (j = 0; j < 8; j++)
337 SR(OVL_FIR_COEF_V(i, j));
338 }
9b372c2d 339
c6104b8e
AT		 340 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
341 SR(OVL_BA0_UV(i));
342 SR(OVL_BA1_UV(i));
343 SR(OVL_FIR2(i));
344 SR(OVL_ACCU2_0(i));
345 SR(OVL_ACCU2_1(i));
ab5ca071 346
c6104b8e
AT		 347 for (j = 0; j < 8; j++)
348 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 349
c6104b8e
AT		 350 for (j = 0; j < 8; j++)
351 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 352
c6104b8e
AT		 353 for (j = 0; j < 8; j++)
354 SR(OVL_FIR_COEF_V2(i, j));
355 }
356 if (dss_has_feature(FEAT_ATTR2))
357 SR(OVL_ATTRIBUTES2(i));
ab5ca071 358 }
0cf35df3
MR		 359
360 if (dss_has_feature(FEAT_CORE_CLK_DIV))
361 SR(DIVISOR);
49ea86f3 362
00928eaf 363 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 364 dispc.ctx_valid = true;
365
366 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 367}
368
4fbafaf3 369static void dispc_restore_context(void)
80c39712 370{
c6104b8e 371 int i, j, ctx;
4fbafaf3
TV		 372
373 DSSDBG("dispc_restore_context\n");
374
49ea86f3
TV		 375 if (!dispc.ctx_valid)
376 return;
377
00928eaf 378 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 379
380 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
381 return;
382
383 DSSDBG("ctx_loss_count: saved %d, current %d\n",
384 dispc.ctx_loss_cnt, ctx);
385
75c7d59d 386 /*RR(IRQENABLE);*/
80c39712
TV		 387 /*RR(CONTROL);*/
388 RR(CONFIG);
80c39712 389 RR(LINE_NUMBER);
11354dd5
AT		 390 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
391 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 392 RR(GLOBAL_ALPHA);
c6104b8e 393 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 394 RR(CONFIG2);
e86d456a
CM		 395 if (dss_has_feature(FEAT_MGR_LCD3))
396 RR(CONFIG3);
80c39712 397
c6104b8e
AT		 398 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
399 RR(DEFAULT_COLOR(i));
400 RR(TRANS_COLOR(i));
401 RR(SIZE_MGR(i));
402 if (i == OMAP_DSS_CHANNEL_DIGIT)
403 continue;
404 RR(TIMING_H(i));
405 RR(TIMING_V(i));
406 RR(POL_FREQ(i));
407 RR(DIVISORo(i));
408
409 RR(DATA_CYCLE1(i));
410 RR(DATA_CYCLE2(i));
411 RR(DATA_CYCLE3(i));
2a205f34 412
332e9d70 413 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 414 RR(CPR_COEF_R(i));
415 RR(CPR_COEF_G(i));
416 RR(CPR_COEF_B(i));
332e9d70 417 }
2a205f34 418 }
80c39712 419
c6104b8e
AT		 420 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
421 RR(OVL_BA0(i));
422 RR(OVL_BA1(i));
423 RR(OVL_POSITION(i));
424 RR(OVL_SIZE(i));
425 RR(OVL_ATTRIBUTES(i));
426 RR(OVL_FIFO_THRESHOLD(i));
427 RR(OVL_ROW_INC(i));
428 RR(OVL_PIXEL_INC(i));
429 if (dss_has_feature(FEAT_PRELOAD))
430 RR(OVL_PRELOAD(i));
431 if (i == OMAP_DSS_GFX) {
432 RR(OVL_WINDOW_SKIP(i));
433 RR(OVL_TABLE_BA(i));
434 continue;
435 }
436 RR(OVL_FIR(i));
437 RR(OVL_PICTURE_SIZE(i));
438 RR(OVL_ACCU0(i));
439 RR(OVL_ACCU1(i));
9b372c2d 440
c6104b8e
AT		 441 for (j = 0; j < 8; j++)
442 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 443
c6104b8e
AT		 444 for (j = 0; j < 8; j++)
445 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 446
c6104b8e
AT		 447 for (j = 0; j < 5; j++)
448 RR(OVL_CONV_COEF(i, j));
ab5ca071 449
c6104b8e
AT		 450 if (dss_has_feature(FEAT_FIR_COEF_V)) {
451 for (j = 0; j < 8; j++)
452 RR(OVL_FIR_COEF_V(i, j));
453 }
9b372c2d 454
c6104b8e
AT		 455 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
456 RR(OVL_BA0_UV(i));
457 RR(OVL_BA1_UV(i));
458 RR(OVL_FIR2(i));
459 RR(OVL_ACCU2_0(i));
460 RR(OVL_ACCU2_1(i));
ab5ca071 461
c6104b8e
AT		 462 for (j = 0; j < 8; j++)
463 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 464
c6104b8e
AT		 465 for (j = 0; j < 8; j++)
466 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 467
c6104b8e
AT		 468 for (j = 0; j < 8; j++)
469 RR(OVL_FIR_COEF_V2(i, j));
470 }
471 if (dss_has_feature(FEAT_ATTR2))
472 RR(OVL_ATTRIBUTES2(i));
ab5ca071 473 }
80c39712 474
0cf35df3
MR		 475 if (dss_has_feature(FEAT_CORE_CLK_DIV))
476 RR(DIVISOR);
477
80c39712
TV		 478 /* enable last, because LCD & DIGIT enable are here */
479 RR(CONTROL);
2a205f34
SS		 480 if (dss_has_feature(FEAT_MGR_LCD2))
481 RR(CONTROL2);
e86d456a
CM		 482 if (dss_has_feature(FEAT_MGR_LCD3))
483 RR(CONTROL3);
75c7d59d
VS		 484 /* clear spurious SYNC_LOST_DIGIT interrupts */
485 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
486
487 /*
488 * enable last so IRQs won't trigger before
489 * the context is fully restored
490 */
491 RR(IRQENABLE);
49ea86f3
TV		 492
493 DSSDBG("context restored\n");
80c39712
TV		 494}
495
496#undef SR
497#undef RR
498
4fbafaf3
TV		 499int dispc_runtime_get(void)
500{
501 int r;
502
503 DSSDBG("dispc_runtime_get\n");
504
505 r = pm_runtime_get_sync(&dispc.pdev->dev);
506 WARN_ON(r < 0);
507 return r < 0 ? r : 0;
508}
509
510void dispc_runtime_put(void)
511{
512 int r;
513
514 DSSDBG("dispc_runtime_put\n");
515
0eaf9f52 516 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 517 WARN_ON(r < 0 && r != -ENOSYS);
80c39712
TV		 518}
519
3dcec4d6
TV		 520u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
521{
efa70b3b 522 return mgr_desc[channel].vsync_irq;
3dcec4d6
TV		 523}
524
7d1365c9
TV		 525u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
526{
efa70b3b 527 return mgr_desc[channel].framedone_irq;
7d1365c9
TV		 528}
529
26d9dd0d 530bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 531{
efa70b3b 532 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712
TV		 533}
534
26d9dd0d 535void dispc_mgr_go(enum omap_channel channel)
80c39712 536{
2a205f34 537 bool enable_bit, go_bit;
80c39712 538
80c39712 539 /* if the channel is not enabled, we don't need GO */
efa70b3b 540 enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
2a205f34
SS		 541
542 if (!enable_bit)
e6d80f95 543 return;
80c39712 544
efa70b3b 545 go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
2a205f34
SS		 546
547 if (go_bit) {
80c39712 548 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 549 return;
80c39712
TV		 550 }
551
efa70b3b 552 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 553
efa70b3b 554 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712
TV		 555}
556
f0e5caab 557static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 558{
9b372c2d 559 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 560}
561
f0e5caab 562static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 563{
9b372c2d 564 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 565}
566
f0e5caab 567static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 568{
9b372c2d 569 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 570}
571
f0e5caab 572static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 573{
574 BUG_ON(plane == OMAP_DSS_GFX);
575
576 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
577}
578
f0e5caab
TV		 579static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
580 u32 value)
ab5ca071
AJ		 581{
582 BUG_ON(plane == OMAP_DSS_GFX);
583
584 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
585}
586
f0e5caab 587static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 588{
589 BUG_ON(plane == OMAP_DSS_GFX);
590
591 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
592}
593
debd9074
CM		 594static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
595 int fir_vinc, int five_taps,
596 enum omap_color_component color_comp)
80c39712 597{
debd9074 598 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 599 int i;
600
debd9074
CM		 601 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
602 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 603
604 for (i = 0; i < 8; i++) {
605 u32 h, hv;
606
debd9074
CM		 607 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
608 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
609 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
610 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
611 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
612 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
613 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
614 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 615
0d66cbb5 616 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 617 dispc_ovl_write_firh_reg(plane, i, h);
618 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 619 } else {
f0e5caab
TV		 620 dispc_ovl_write_firh2_reg(plane, i, h);
621 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 622 }
623
80c39712
TV		 624 }
625
66be8f6c
GI		 626 if (five_taps) {
627 for (i = 0; i < 8; i++) {
628 u32 v;
debd9074
CM		 629 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
630 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 631 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 632 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 633 else
f0e5caab 634 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 635 }
80c39712
TV		 636 }
637}
638
639static void _dispc_setup_color_conv_coef(void)
640{
ac01c29e 641 int i;
80c39712
TV		 642 const struct color_conv_coef {
643 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
644 int full_range;
645 } ctbl_bt601_5 = {
646 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
647 };
648
649 const struct color_conv_coef *ct;
650
651#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
652
653 ct = &ctbl_bt601_5;
654
ac01c29e
AT		 655 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
656 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
657 CVAL(ct->rcr, ct->ry));
658 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
659 CVAL(ct->gy, ct->rcb));
660 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
661 CVAL(ct->gcb, ct->gcr));
662 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
663 CVAL(ct->bcr, ct->by));
664 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
665 CVAL(0, ct->bcb));
666
667 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
668 11, 11);
669 }
80c39712
TV		 670
671#undef CVAL
80c39712
TV		 672}
673
674
f0e5caab 675static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 676{
9b372c2d 677 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 678}
679
f0e5caab 680static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 681{
9b372c2d 682 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 683}
684
f0e5caab 685static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 686{
687 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
688}
689
f0e5caab 690static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 691{
692 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
693}
694
f0e5caab 695static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 696{
80c39712 697 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 698
699 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 700}
701
f0e5caab 702static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 703{
80c39712 704 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 705
706 if (plane == OMAP_DSS_GFX)
707 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
708 else
709 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 710}
711
f0e5caab 712static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 713{
714 u32 val;
80c39712
TV		 715
716 BUG_ON(plane == OMAP_DSS_GFX);
717
718 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 719
720 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 721}
722
54128701
AT		 723static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
724{
725 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
726
727 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
728 return;
729
730 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
731}
732
733static void dispc_ovl_enable_zorder_planes(void)
734{
735 int i;
736
737 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
738 return;
739
740 for (i = 0; i < dss_feat_get_num_ovls(); i++)
741 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
742}
743
f0e5caab 744static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 745{
f6dc8150 746 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 747
f6dc8150 748 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 749 return;
750
9b372c2d 751 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 752}
753
f0e5caab 754static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 755{
b8c095b4 756 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 757 int shift;
f6dc8150 758 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 759
f6dc8150 760 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 761 return;
a0acb557 762
fe3cc9d6
TV		 763 shift = shifts[plane];
764 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 765}
766
f0e5caab 767static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 768{
9b372c2d 769 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 770}
771
f0e5caab 772static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 773{
9b372c2d 774 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 775}
776
f0e5caab 777static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 778 enum omap_color_mode color_mode)
779{
780 u32 m = 0;
f20e4220
AJ		 781 if (plane != OMAP_DSS_GFX) {
782 switch (color_mode) {
783 case OMAP_DSS_COLOR_NV12:
784 m = 0x0; break;
08f3267e 785 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 786 m = 0x1; break;
787 case OMAP_DSS_COLOR_RGBA16:
788 m = 0x2; break;
08f3267e 789 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 790 m = 0x4; break;
791 case OMAP_DSS_COLOR_ARGB16:
792 m = 0x5; break;
793 case OMAP_DSS_COLOR_RGB16:
794 m = 0x6; break;
795 case OMAP_DSS_COLOR_ARGB16_1555:
796 m = 0x7; break;
797 case OMAP_DSS_COLOR_RGB24U:
798 m = 0x8; break;
799 case OMAP_DSS_COLOR_RGB24P:
800 m = 0x9; break;
801 case OMAP_DSS_COLOR_YUV2:
802 m = 0xa; break;
803 case OMAP_DSS_COLOR_UYVY:
804 m = 0xb; break;
805 case OMAP_DSS_COLOR_ARGB32:
806 m = 0xc; break;
807 case OMAP_DSS_COLOR_RGBA32:
808 m = 0xd; break;
809 case OMAP_DSS_COLOR_RGBX32:
810 m = 0xe; break;
811 case OMAP_DSS_COLOR_XRGB16_1555:
812 m = 0xf; break;
813 default:
c6eee968 814 BUG(); return;
f20e4220
AJ		 815 }
816 } else {
817 switch (color_mode) {
818 case OMAP_DSS_COLOR_CLUT1:
819 m = 0x0; break;
820 case OMAP_DSS_COLOR_CLUT2:
821 m = 0x1; break;
822 case OMAP_DSS_COLOR_CLUT4:
823 m = 0x2; break;
824 case OMAP_DSS_COLOR_CLUT8:
825 m = 0x3; break;
826 case OMAP_DSS_COLOR_RGB12U:
827 m = 0x4; break;
828 case OMAP_DSS_COLOR_ARGB16:
829 m = 0x5; break;
830 case OMAP_DSS_COLOR_RGB16:
831 m = 0x6; break;
832 case OMAP_DSS_COLOR_ARGB16_1555:
833 m = 0x7; break;
834 case OMAP_DSS_COLOR_RGB24U:
835 m = 0x8; break;
836 case OMAP_DSS_COLOR_RGB24P:
837 m = 0x9; break;
08f3267e 838 case OMAP_DSS_COLOR_RGBX16:
f20e4220 839 m = 0xa; break;
08f3267e 840 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 841 m = 0xb; break;
842 case OMAP_DSS_COLOR_ARGB32:
843 m = 0xc; break;
844 case OMAP_DSS_COLOR_RGBA32:
845 m = 0xd; break;
846 case OMAP_DSS_COLOR_RGBX32:
847 m = 0xe; break;
848 case OMAP_DSS_COLOR_XRGB16_1555:
849 m = 0xf; break;
850 default:
c6eee968 851 BUG(); return;
f20e4220 852 }
80c39712
TV		 853 }
854
9b372c2d 855 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 856}
857
65e006ff
CM		 858static void dispc_ovl_configure_burst_type(enum omap_plane plane,
859 enum omap_dss_rotation_type rotation_type)
860{
861 if (dss_has_feature(FEAT_BURST_2D) == 0)
862 return;
863
864 if (rotation_type == OMAP_DSS_ROT_TILER)
865 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
866 else
867 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
868}
869
f427984e 870void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 871{
872 int shift;
873 u32 val;
2a205f34 874 int chan = 0, chan2 = 0;
80c39712
TV		 875
876 switch (plane) {
877 case OMAP_DSS_GFX:
878 shift = 8;
879 break;
880 case OMAP_DSS_VIDEO1:
881 case OMAP_DSS_VIDEO2:
b8c095b4 882 case OMAP_DSS_VIDEO3:
80c39712
TV		 883 shift = 16;
884 break;
885 default:
886 BUG();
887 return;
888 }
889
9b372c2d 890 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 891 if (dss_has_feature(FEAT_MGR_LCD2)) {
892 switch (channel) {
893 case OMAP_DSS_CHANNEL_LCD:
894 chan = 0;
895 chan2 = 0;
896 break;
897 case OMAP_DSS_CHANNEL_DIGIT:
898 chan = 1;
899 chan2 = 0;
900 break;
901 case OMAP_DSS_CHANNEL_LCD2:
902 chan = 0;
903 chan2 = 1;
904 break;
e86d456a
CM		 905 case OMAP_DSS_CHANNEL_LCD3:
906 if (dss_has_feature(FEAT_MGR_LCD3)) {
907 chan = 0;
908 chan2 = 2;
909 } else {
910 BUG();
911 return;
912 }
913 break;
2a205f34
SS		 914 default:
915 BUG();
c6eee968 916 return;
2a205f34
SS		 917 }
918
919 val = FLD_MOD(val, chan, shift, shift);
920 val = FLD_MOD(val, chan2, 31, 30);
921 } else {
922 val = FLD_MOD(val, channel, shift, shift);
923 }
9b372c2d 924 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 925}
926
2cc5d1af
TV		 927static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
928{
929 int shift;
930 u32 val;
931 enum omap_channel channel;
932
933 switch (plane) {
934 case OMAP_DSS_GFX:
935 shift = 8;
936 break;
937 case OMAP_DSS_VIDEO1:
938 case OMAP_DSS_VIDEO2:
939 case OMAP_DSS_VIDEO3:
940 shift = 16;
941 break;
942 default:
943 BUG();
c6eee968 944 return 0;
2cc5d1af
TV		 945 }
946
947 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
948
e86d456a
CM		 949 if (dss_has_feature(FEAT_MGR_LCD3)) {
950 if (FLD_GET(val, 31, 30) == 0)
951 channel = FLD_GET(val, shift, shift);
952 else if (FLD_GET(val, 31, 30) == 1)
953 channel = OMAP_DSS_CHANNEL_LCD2;
954 else
955 channel = OMAP_DSS_CHANNEL_LCD3;
956 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 957 if (FLD_GET(val, 31, 30) == 0)
958 channel = FLD_GET(val, shift, shift);
959 else
960 channel = OMAP_DSS_CHANNEL_LCD2;
961 } else {
962 channel = FLD_GET(val, shift, shift);
963 }
964
965 return channel;
966}
967
f0e5caab 968static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 969 enum omap_burst_size burst_size)
970{
b8c095b4 971 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 972 int shift;
80c39712 973
fe3cc9d6 974 shift = shifts[plane];
5ed8cf5b 975 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 976}
977
5ed8cf5b
TV		 978static void dispc_configure_burst_sizes(void)
979{
980 int i;
981 const int burst_size = BURST_SIZE_X8;
982
983 /* Configure burst size always to maximum size */
984 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 985 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 986}
987
83fa2f2e 988static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 989{
990 unsigned unit = dss_feat_get_burst_size_unit();
991 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
992 return unit * 8;
993}
994
d3862610
M		 995void dispc_enable_gamma_table(bool enable)
996{
997 /*
998 * This is partially implemented to support only disabling of
999 * the gamma table.
1000 */
1001 if (enable) {
1002 DSSWARN("Gamma table enabling for TV not yet supported");
1003 return;
1004 }
1005
1006 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1007}
1008
c64dca40 1009static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1010{
efa70b3b 1011 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1012 return;
1013
efa70b3b 1014 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1015}
1016
c64dca40 1017static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 1018 struct omap_dss_cpr_coefs *coefs)
1019{
1020 u32 coef_r, coef_g, coef_b;
1021
dd88b7a6 1022 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1023 return;
1024
1025 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1026 FLD_VAL(coefs->rb, 9, 0);
1027 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1028 FLD_VAL(coefs->gb, 9, 0);
1029 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1030 FLD_VAL(coefs->bb, 9, 0);
1031
1032 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1033 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1034 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1035}
1036
f0e5caab 1037static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1038{
1039 u32 val;
1040
1041 BUG_ON(plane == OMAP_DSS_GFX);
1042
9b372c2d 1043 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1044 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1045 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1046}
1047
c3d92529 1048static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 1049{
b8c095b4 1050 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1051 int shift;
80c39712 1052
fe3cc9d6
TV		 1053 shift = shifts[plane];
1054 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1055}
1056
8f366162 1057static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1058 u16 height)
80c39712
TV		 1059{
1060 u32 val;
80c39712 1061
80c39712 1062 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 1063 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1064}
1065
1066static void dispc_read_plane_fifo_sizes(void)
1067{
80c39712
TV		 1068 u32 size;
1069 int plane;
a0acb557 1070 u8 start, end;
5ed8cf5b
TV		 1071 u32 unit;
1072
1073 unit = dss_feat_get_buffer_size_unit();
80c39712 1074
a0acb557 1075 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1076
e13a138b 1077 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 1078 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1079 size *= unit;
80c39712
TV		 1080 dispc.fifo_size[plane] = size;
1081 }
80c39712
TV		 1082}
1083
83fa2f2e 1084static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1085{
1086 return dispc.fifo_size[plane];
1087}
1088
6f04e1bf 1089void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1090{
a0acb557 1091 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1092 u32 unit;
1093
1094 unit = dss_feat_get_buffer_size_unit();
1095
1096 WARN_ON(low % unit != 0);
1097 WARN_ON(high % unit != 0);
1098
1099 low /= unit;
1100 high /= unit;
a0acb557 1101
9b372c2d
AT		 1102 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1103 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1104
3cb5d966 1105 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1106 plane,
9b372c2d 1107 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1108 lo_start, lo_end) * unit,
9b372c2d 1109 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1110 hi_start, hi_end) * unit,
1111 low * unit, high * unit);
80c39712 1112
9b372c2d 1113 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1114 FLD_VAL(high, hi_start, hi_end) |
1115 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1116}
1117
1118void dispc_enable_fifomerge(bool enable)
1119{
e6b0f884
TV		 1120 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1121 WARN_ON(enable);
1122 return;
1123 }
1124
80c39712
TV		 1125 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1126 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1127}
1128
83fa2f2e 1129void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1130 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1131 bool manual_update)
83fa2f2e
TV		 1132{
1133 /*
1134 * All sizes are in bytes. Both the buffer and burst are made of
1135 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1136 */
1137
1138 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1139 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1140 int i;
83fa2f2e
TV		 1141
1142 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1143 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1144
e0e405b9
TV		 1145 if (use_fifomerge) {
1146 total_fifo_size = 0;
1147 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1148 total_fifo_size += dispc_ovl_get_fifo_size(i);
1149 } else {
1150 total_fifo_size = ovl_fifo_size;
1151 }
1152
1153 /*
1154 * We use the same low threshold for both fifomerge and non-fifomerge
1155 * cases, but for fifomerge we calculate the high threshold using the
1156 * combined fifo size
1157 */
1158
3568f2a4 1159 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1160 *fifo_low = ovl_fifo_size - burst_size * 2;
1161 *fifo_high = total_fifo_size - burst_size;
1162 } else {
1163 *fifo_low = ovl_fifo_size - burst_size;
1164 *fifo_high = total_fifo_size - buf_unit;
1165 }
83fa2f2e
TV		 1166}
1167
f0e5caab 1168static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1169 int hinc, int vinc,
1170 enum omap_color_component color_comp)
80c39712
TV		 1171{
1172 u32 val;
80c39712 1173
0d66cbb5
AJ		 1174 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1175 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1176
0d66cbb5
AJ		 1177 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1178 &hinc_start, &hinc_end);
1179 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1180 &vinc_start, &vinc_end);
1181 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1182 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1183
0d66cbb5
AJ		 1184 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1185 } else {
1186 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1187 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1188 }
80c39712
TV		 1189}
1190
f0e5caab 1191static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1192{
1193 u32 val;
87a7484b 1194 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1195
87a7484b
AT		 1196 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1197 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1198
1199 val = FLD_VAL(vaccu, vert_start, vert_end) |
1200 FLD_VAL(haccu, hor_start, hor_end);
1201
9b372c2d 1202 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1203}
1204
f0e5caab 1205static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1206{
1207 u32 val;
87a7484b 1208 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1209
87a7484b
AT		 1210 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1211 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1212
1213 val = FLD_VAL(vaccu, vert_start, vert_end) |
1214 FLD_VAL(haccu, hor_start, hor_end);
1215
9b372c2d 1216 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1217}
1218
f0e5caab
TV		 1219static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1220 int vaccu)
ab5ca071
AJ		 1221{
1222 u32 val;
1223
1224 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1225 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1226}
1227
f0e5caab
TV		 1228static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1229 int vaccu)
ab5ca071
AJ		 1230{
1231 u32 val;
1232
1233 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1234 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1235}
80c39712 1236
f0e5caab 1237static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1238 u16 orig_width, u16 orig_height,
1239 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1240 bool five_taps, u8 rotation,
1241 enum omap_color_component color_comp)
80c39712 1242{
0d66cbb5 1243 int fir_hinc, fir_vinc;
80c39712 1244
ed14a3ce
AJ		 1245 fir_hinc = 1024 * orig_width / out_width;
1246 fir_vinc = 1024 * orig_height / out_height;
80c39712 1247
debd9074
CM		 1248 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1249 color_comp);
f0e5caab 1250 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1251}
1252
05dd0f53
CM		 1253static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1254 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1255 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1256{
1257 int h_accu2_0, h_accu2_1;
1258 int v_accu2_0, v_accu2_1;
1259 int chroma_hinc, chroma_vinc;
1260 int idx;
1261
1262 struct accu {
1263 s8 h0_m, h0_n;
1264 s8 h1_m, h1_n;
1265 s8 v0_m, v0_n;
1266 s8 v1_m, v1_n;
1267 };
1268
1269 const struct accu *accu_table;
1270 const struct accu *accu_val;
1271
1272 static const struct accu accu_nv12[4] = {
1273 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1274 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1275 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1276 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1277 };
1278
1279 static const struct accu accu_nv12_ilace[4] = {
1280 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1281 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1282 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1283 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1284 };
1285
1286 static const struct accu accu_yuv[4] = {
1287 { 0, 1, 0, 1, 0, 1, 0, 1 },
1288 { 0, 1, 0, 1, 0, 1, 0, 1 },
1289 { -1, 1, 0, 1, 0, 1, 0, 1 },
1290 { 0, 1, 0, 1, -1, 1, 0, 1 },
1291 };
1292
1293 switch (rotation) {
1294 case OMAP_DSS_ROT_0:
1295 idx = 0;
1296 break;
1297 case OMAP_DSS_ROT_90:
1298 idx = 1;
1299 break;
1300 case OMAP_DSS_ROT_180:
1301 idx = 2;
1302 break;
1303 case OMAP_DSS_ROT_270:
1304 idx = 3;
1305 break;
1306 default:
1307 BUG();
c6eee968 1308 return;
05dd0f53
CM		 1309 }
1310
1311 switch (color_mode) {
1312 case OMAP_DSS_COLOR_NV12:
1313 if (ilace)
1314 accu_table = accu_nv12_ilace;
1315 else
1316 accu_table = accu_nv12;
1317 break;
1318 case OMAP_DSS_COLOR_YUV2:
1319 case OMAP_DSS_COLOR_UYVY:
1320 accu_table = accu_yuv;
1321 break;
1322 default:
1323 BUG();
c6eee968 1324 return;
05dd0f53
CM		 1325 }
1326
1327 accu_val = &accu_table[idx];
1328
1329 chroma_hinc = 1024 * orig_width / out_width;
1330 chroma_vinc = 1024 * orig_height / out_height;
1331
1332 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1333 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1334 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1335 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1336
1337 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1338 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1339}
1340
f0e5caab 1341static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1342 u16 orig_width, u16 orig_height,
1343 u16 out_width, u16 out_height,
1344 bool ilace, bool five_taps,
1345 bool fieldmode, enum omap_color_mode color_mode,
1346 u8 rotation)
1347{
1348 int accu0 = 0;
1349 int accu1 = 0;
1350 u32 l;
80c39712 1351
f0e5caab 1352 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1353 out_width, out_height, five_taps,
1354 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1355 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1356
87a7484b
AT		 1357 /* RESIZEENABLE and VERTICALTAPS */
1358 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1359 l |= (orig_width != out_width) ? (1 << 5) : 0;
1360 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1361 l |= five_taps ? (1 << 21) : 0;
80c39712 1362
87a7484b
AT		 1363 /* VRESIZECONF and HRESIZECONF */
1364 if (dss_has_feature(FEAT_RESIZECONF)) {
1365 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1366 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1367 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1368 }
80c39712 1369
87a7484b
AT		 1370 /* LINEBUFFERSPLIT */
1371 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1372 l &= ~(0x1 << 22);
1373 l |= five_taps ? (1 << 22) : 0;
1374 }
80c39712 1375
9b372c2d 1376 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1377
1378 /*
1379 * field 0 = even field = bottom field
1380 * field 1 = odd field = top field
1381 */
1382 if (ilace && !fieldmode) {
1383 accu1 = 0;
0d66cbb5 1384 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1385 if (accu0 >= 1024/2) {
1386 accu1 = 1024/2;
1387 accu0 -= accu1;
1388 }
1389 }
1390
f0e5caab
TV		 1391 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1392 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1393}
1394
f0e5caab 1395static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1396 u16 orig_width, u16 orig_height,
1397 u16 out_width, u16 out_height,
1398 bool ilace, bool five_taps,
1399 bool fieldmode, enum omap_color_mode color_mode,
1400 u8 rotation)
1401{
1402 int scale_x = out_width != orig_width;
1403 int scale_y = out_height != orig_height;
1404
1405 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1406 return;
1407 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1408 color_mode != OMAP_DSS_COLOR_UYVY &&
1409 color_mode != OMAP_DSS_COLOR_NV12)) {
1410 /* reset chroma resampling for RGB formats */
1411 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1412 return;
1413 }
36377357
TV		 1414
1415 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1416 out_height, ilace, color_mode, rotation);
1417
0d66cbb5
AJ		 1418 switch (color_mode) {
1419 case OMAP_DSS_COLOR_NV12:
1420 /* UV is subsampled by 2 vertically*/
1421 orig_height >>= 1;
1422 /* UV is subsampled by 2 horz.*/
1423 orig_width >>= 1;
1424 break;
1425 case OMAP_DSS_COLOR_YUV2:
1426 case OMAP_DSS_COLOR_UYVY:
1427 /*For YUV422 with 90/270 rotation,
1428 *we don't upsample chroma
1429 */
1430 if (rotation == OMAP_DSS_ROT_0 ||
1431 rotation == OMAP_DSS_ROT_180)
1432 /* UV is subsampled by 2 hrz*/
1433 orig_width >>= 1;
1434 /* must use FIR for YUV422 if rotated */
1435 if (rotation != OMAP_DSS_ROT_0)
1436 scale_x = scale_y = true;
1437 break;
1438 default:
1439 BUG();
c6eee968 1440 return;
0d66cbb5
AJ		 1441 }
1442
1443 if (out_width != orig_width)
1444 scale_x = true;
1445 if (out_height != orig_height)
1446 scale_y = true;
1447
f0e5caab 1448 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1449 out_width, out_height, five_taps,
1450 rotation, DISPC_COLOR_COMPONENT_UV);
1451
1452 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1453 (scale_x || scale_y) ? 1 : 0, 8, 8);
1454 /* set H scaling */
1455 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1456 /* set V scaling */
1457 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1458}
1459
f0e5caab 1460static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1461 u16 orig_width, u16 orig_height,
1462 u16 out_width, u16 out_height,
1463 bool ilace, bool five_taps,
1464 bool fieldmode, enum omap_color_mode color_mode,
1465 u8 rotation)
1466{
1467 BUG_ON(plane == OMAP_DSS_GFX);
1468
f0e5caab 1469 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1470 orig_width, orig_height,
1471 out_width, out_height,
1472 ilace, five_taps,
1473 fieldmode, color_mode,
1474 rotation);
1475
f0e5caab 1476 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1477 orig_width, orig_height,
1478 out_width, out_height,
1479 ilace, five_taps,
1480 fieldmode, color_mode,
1481 rotation);
1482}
1483
f0e5caab 1484static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1485 bool mirroring, enum omap_color_mode color_mode)
1486{
87a7484b
AT		 1487 bool row_repeat = false;
1488 int vidrot = 0;
1489
80c39712
TV		 1490 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1491 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1492
1493 if (mirroring) {
1494 switch (rotation) {
1495 case OMAP_DSS_ROT_0:
1496 vidrot = 2;
1497 break;
1498 case OMAP_DSS_ROT_90:
1499 vidrot = 1;
1500 break;
1501 case OMAP_DSS_ROT_180:
1502 vidrot = 0;
1503 break;
1504 case OMAP_DSS_ROT_270:
1505 vidrot = 3;
1506 break;
1507 }
1508 } else {
1509 switch (rotation) {
1510 case OMAP_DSS_ROT_0:
1511 vidrot = 0;
1512 break;
1513 case OMAP_DSS_ROT_90:
1514 vidrot = 1;
1515 break;
1516 case OMAP_DSS_ROT_180:
1517 vidrot = 2;
1518 break;
1519 case OMAP_DSS_ROT_270:
1520 vidrot = 3;
1521 break;
1522 }
1523 }
1524
80c39712 1525 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1526 row_repeat = true;
80c39712 1527 else
87a7484b 1528 row_repeat = false;
80c39712 1529 }
87a7484b 1530
9b372c2d 1531 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1532 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1533 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1534 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1535}
1536
1537static int color_mode_to_bpp(enum omap_color_mode color_mode)
1538{
1539 switch (color_mode) {
1540 case OMAP_DSS_COLOR_CLUT1:
1541 return 1;
1542 case OMAP_DSS_COLOR_CLUT2:
1543 return 2;
1544 case OMAP_DSS_COLOR_CLUT4:
1545 return 4;
1546 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1547 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1548 return 8;
1549 case OMAP_DSS_COLOR_RGB12U:
1550 case OMAP_DSS_COLOR_RGB16:
1551 case OMAP_DSS_COLOR_ARGB16:
1552 case OMAP_DSS_COLOR_YUV2:
1553 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1554 case OMAP_DSS_COLOR_RGBA16:
1555 case OMAP_DSS_COLOR_RGBX16:
1556 case OMAP_DSS_COLOR_ARGB16_1555:
1557 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1558 return 16;
1559 case OMAP_DSS_COLOR_RGB24P:
1560 return 24;
1561 case OMAP_DSS_COLOR_RGB24U:
1562 case OMAP_DSS_COLOR_ARGB32:
1563 case OMAP_DSS_COLOR_RGBA32:
1564 case OMAP_DSS_COLOR_RGBX32:
1565 return 32;
1566 default:
1567 BUG();
c6eee968 1568 return 0;
80c39712
TV		 1569 }
1570}
1571
1572static s32 pixinc(int pixels, u8 ps)
1573{
1574 if (pixels == 1)
1575 return 1;
1576 else if (pixels > 1)
1577 return 1 + (pixels - 1) * ps;
1578 else if (pixels < 0)
1579 return 1 - (-pixels + 1) * ps;
1580 else
1581 BUG();
c6eee968 1582 return 0;
80c39712
TV		 1583}
1584
1585static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1586 u16 screen_width,
1587 u16 width, u16 height,
1588 enum omap_color_mode color_mode, bool fieldmode,
1589 unsigned int field_offset,
1590 unsigned *offset0, unsigned *offset1,
aed74b55 1591 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1592{
1593 u8 ps;
1594
1595 /* FIXME CLUT formats */
1596 switch (color_mode) {
1597 case OMAP_DSS_COLOR_CLUT1:
1598 case OMAP_DSS_COLOR_CLUT2:
1599 case OMAP_DSS_COLOR_CLUT4:
1600 case OMAP_DSS_COLOR_CLUT8:
1601 BUG();
1602 return;
1603 case OMAP_DSS_COLOR_YUV2:
1604 case OMAP_DSS_COLOR_UYVY:
1605 ps = 4;
1606 break;
1607 default:
1608 ps = color_mode_to_bpp(color_mode) / 8;
1609 break;
1610 }
1611
1612 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1613 width, height);
1614
1615 /*
1616 * field 0 = even field = bottom field
1617 * field 1 = odd field = top field
1618 */
1619 switch (rotation + mirror * 4) {
1620 case OMAP_DSS_ROT_0:
1621 case OMAP_DSS_ROT_180:
1622 /*
1623 * If the pixel format is YUV or UYVY divide the width
1624 * of the image by 2 for 0 and 180 degree rotation.
1625 */
1626 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1627 color_mode == OMAP_DSS_COLOR_UYVY)
1628 width = width >> 1;
1629 case OMAP_DSS_ROT_90:
1630 case OMAP_DSS_ROT_270:
1631 *offset1 = 0;
1632 if (field_offset)
1633 *offset0 = field_offset * screen_width * ps;
1634 else
1635 *offset0 = 0;
1636
aed74b55
CM		 1637 *row_inc = pixinc(1 +
1638 (y_predecim * screen_width - x_predecim * width) +
1639 (fieldmode ? screen_width : 0), ps);
1640 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1641 break;
1642
1643 case OMAP_DSS_ROT_0 + 4:
1644 case OMAP_DSS_ROT_180 + 4:
1645 /* If the pixel format is YUV or UYVY divide the width
1646 * of the image by 2 for 0 degree and 180 degree
1647 */
1648 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1649 color_mode == OMAP_DSS_COLOR_UYVY)
1650 width = width >> 1;
1651 case OMAP_DSS_ROT_90 + 4:
1652 case OMAP_DSS_ROT_270 + 4:
1653 *offset1 = 0;
1654 if (field_offset)
1655 *offset0 = field_offset * screen_width * ps;
1656 else
1657 *offset0 = 0;
aed74b55
CM		 1658 *row_inc = pixinc(1 -
1659 (y_predecim * screen_width + x_predecim * width) -
1660 (fieldmode ? screen_width : 0), ps);
1661 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1662 break;
1663
1664 default:
1665 BUG();
c6eee968 1666 return;
80c39712
TV		 1667 }
1668}
1669
1670static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1671 u16 screen_width,
1672 u16 width, u16 height,
1673 enum omap_color_mode color_mode, bool fieldmode,
1674 unsigned int field_offset,
1675 unsigned *offset0, unsigned *offset1,
aed74b55 1676 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1677{
1678 u8 ps;
1679 u16 fbw, fbh;
1680
1681 /* FIXME CLUT formats */
1682 switch (color_mode) {
1683 case OMAP_DSS_COLOR_CLUT1:
1684 case OMAP_DSS_COLOR_CLUT2:
1685 case OMAP_DSS_COLOR_CLUT4:
1686 case OMAP_DSS_COLOR_CLUT8:
1687 BUG();
1688 return;
1689 default:
1690 ps = color_mode_to_bpp(color_mode) / 8;
1691 break;
1692 }
1693
1694 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1695 width, height);
1696
1697 /* width & height are overlay sizes, convert to fb sizes */
1698
1699 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1700 fbw = width;
1701 fbh = height;
1702 } else {
1703 fbw = height;
1704 fbh = width;
1705 }
1706
1707 /*
1708 * field 0 = even field = bottom field
1709 * field 1 = odd field = top field
1710 */
1711 switch (rotation + mirror * 4) {
1712 case OMAP_DSS_ROT_0:
1713 *offset1 = 0;
1714 if (field_offset)
1715 *offset0 = *offset1 + field_offset * screen_width * ps;
1716 else
1717 *offset0 = *offset1;
aed74b55
CM		 1718 *row_inc = pixinc(1 +
1719 (y_predecim * screen_width - fbw * x_predecim) +
1720 (fieldmode ? screen_width : 0), ps);
1721 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1722 color_mode == OMAP_DSS_COLOR_UYVY)
1723 *pix_inc = pixinc(x_predecim, 2 * ps);
1724 else
1725 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1726 break;
1727 case OMAP_DSS_ROT_90:
1728 *offset1 = screen_width * (fbh - 1) * ps;
1729 if (field_offset)
1730 *offset0 = *offset1 + field_offset * ps;
1731 else
1732 *offset0 = *offset1;
aed74b55
CM		 1733 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1734 y_predecim + (fieldmode ? 1 : 0), ps);
1735 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1736 break;
1737 case OMAP_DSS_ROT_180:
1738 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1739 if (field_offset)
1740 *offset0 = *offset1 - field_offset * screen_width * ps;
1741 else
1742 *offset0 = *offset1;
1743 *row_inc = pixinc(-1 -
aed74b55
CM		 1744 (y_predecim * screen_width - fbw * x_predecim) -
1745 (fieldmode ? screen_width : 0), ps);
1746 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1747 color_mode == OMAP_DSS_COLOR_UYVY)
1748 *pix_inc = pixinc(-x_predecim, 2 * ps);
1749 else
1750 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1751 break;
1752 case OMAP_DSS_ROT_270:
1753 *offset1 = (fbw - 1) * ps;
1754 if (field_offset)
1755 *offset0 = *offset1 - field_offset * ps;
1756 else
1757 *offset0 = *offset1;
aed74b55
CM		 1758 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1759 y_predecim - (fieldmode ? 1 : 0), ps);
1760 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1761 break;
1762
1763 /* mirroring */
1764 case OMAP_DSS_ROT_0 + 4:
1765 *offset1 = (fbw - 1) * ps;
1766 if (field_offset)
1767 *offset0 = *offset1 + field_offset * screen_width * ps;
1768 else
1769 *offset0 = *offset1;
aed74b55 1770 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1771 (fieldmode ? screen_width : 0),
1772 ps);
aed74b55
CM		 1773 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1774 color_mode == OMAP_DSS_COLOR_UYVY)
1775 *pix_inc = pixinc(-x_predecim, 2 * ps);
1776 else
1777 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1778 break;
1779
1780 case OMAP_DSS_ROT_90 + 4:
1781 *offset1 = 0;
1782 if (field_offset)
1783 *offset0 = *offset1 + field_offset * ps;
1784 else
1785 *offset0 = *offset1;
aed74b55
CM		 1786 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1787 y_predecim + (fieldmode ? 1 : 0),
80c39712 1788 ps);
aed74b55 1789 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1790 break;
1791
1792 case OMAP_DSS_ROT_180 + 4:
1793 *offset1 = screen_width * (fbh - 1) * ps;
1794 if (field_offset)
1795 *offset0 = *offset1 - field_offset * screen_width * ps;
1796 else
1797 *offset0 = *offset1;
aed74b55 1798 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1799 (fieldmode ? screen_width : 0),
1800 ps);
aed74b55
CM		 1801 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1802 color_mode == OMAP_DSS_COLOR_UYVY)
1803 *pix_inc = pixinc(x_predecim, 2 * ps);
1804 else
1805 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1806 break;
1807
1808 case OMAP_DSS_ROT_270 + 4:
1809 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1810 if (field_offset)
1811 *offset0 = *offset1 - field_offset * ps;
1812 else
1813 *offset0 = *offset1;
aed74b55
CM		 1814 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1815 y_predecim - (fieldmode ? 1 : 0),
80c39712 1816 ps);
aed74b55 1817 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1818 break;
1819
1820 default:
1821 BUG();
c6eee968 1822 return;
80c39712
TV		 1823 }
1824}
1825
65e006ff
CM		 1826static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1827 enum omap_color_mode color_mode, bool fieldmode,
1828 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1829 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1830{
1831 u8 ps;
1832
1833 switch (color_mode) {
1834 case OMAP_DSS_COLOR_CLUT1:
1835 case OMAP_DSS_COLOR_CLUT2:
1836 case OMAP_DSS_COLOR_CLUT4:
1837 case OMAP_DSS_COLOR_CLUT8:
1838 BUG();
1839 return;
1840 default:
1841 ps = color_mode_to_bpp(color_mode) / 8;
1842 break;
1843 }
1844
1845 DSSDBG("scrw %d, width %d\n", screen_width, width);
1846
1847 /*
1848 * field 0 = even field = bottom field
1849 * field 1 = odd field = top field
1850 */
1851 *offset1 = 0;
1852 if (field_offset)
1853 *offset0 = *offset1 + field_offset * screen_width * ps;
1854 else
1855 *offset0 = *offset1;
1856 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1857 (fieldmode ? screen_width : 0), ps);
1858 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1859 color_mode == OMAP_DSS_COLOR_UYVY)
1860 *pix_inc = pixinc(x_predecim, 2 * ps);
1861 else
1862 *pix_inc = pixinc(x_predecim, ps);
1863}
1864
7faa9233
CM		 1865/*
1866 * This function is used to avoid synclosts in OMAP3, because of some
1867 * undocumented horizontal position and timing related limitations.
1868 */
81ab95b7
AT		 1869static int check_horiz_timing_omap3(enum omap_channel channel,
1870 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1871 u16 width, u16 height, u16 out_width, u16 out_height)
1872{
1873 int DS = DIV_ROUND_UP(height, out_height);
7faa9233
CM		 1874 unsigned long nonactive, lclk, pclk;
1875 static const u8 limits[3] = { 8, 10, 20 };
1876 u64 val, blank;
1877 int i;
1878
81ab95b7 1879 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233 1880 pclk = dispc_mgr_pclk_rate(channel);
dd88b7a6 1881 if (dss_mgr_is_lcd(channel))
7faa9233
CM		 1882 lclk = dispc_mgr_lclk_rate(channel);
1883 else
1884 lclk = dispc_fclk_rate();
1885
1886 i = 0;
1887 if (out_height < height)
1888 i++;
1889 if (out_width < width)
1890 i++;
81ab95b7 1891 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1892 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1893 if (blank <= limits[i])
1894 return -EINVAL;
1895
1896 /*
1897 * Pixel data should be prepared before visible display point starts.
1898 * So, atleast DS-2 lines must have already been fetched by DISPC
1899 * during nonactive - pos_x period.
1900 */
1901 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1902 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1903 val, max(0, DS - 2) * width);
1904 if (val < max(0, DS - 2) * width)
1905 return -EINVAL;
1906
1907 /*
1908 * All lines need to be refilled during the nonactive period of which
1909 * only one line can be loaded during the active period. So, atleast
1910 * DS - 1 lines should be loaded during nonactive period.
1911 */
1912 val = div_u64((u64)nonactive * lclk, pclk);
1913 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1914 val, max(0, DS - 1) * width);
1915 if (val < max(0, DS - 1) * width)
1916 return -EINVAL;
1917
1918 return 0;
1919}
1920
8b53d991 1921static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
81ab95b7
AT		 1922 const struct omap_video_timings *mgr_timings, u16 width,
1923 u16 height, u16 out_width, u16 out_height,
ff1b2cde 1924 enum omap_color_mode color_mode)
80c39712 1925{
8b53d991 1926 u32 core_clk = 0;
26d9dd0d 1927 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1928
7282f1b7
CM		 1929 if (height <= out_height && width <= out_width)
1930 return (unsigned long) pclk;
1931
80c39712 1932 if (height > out_height) {
81ab95b7 1933 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 1934
1935 tmp = pclk * height * out_width;
1936 do_div(tmp, 2 * out_height * ppl);
8b53d991 1937 core_clk = tmp;
80c39712 1938
2d9c5597
VS		 1939 if (height > 2 * out_height) {
1940 if (ppl == out_width)
1941 return 0;
1942
80c39712
TV		 1943 tmp = pclk * (height - 2 * out_height) * out_width;
1944 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 1945 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1946 }
1947 }
1948
1949 if (width > out_width) {
1950 tmp = pclk * width;
1951 do_div(tmp, out_width);
8b53d991 1952 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1953
1954 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 1955 core_clk <<= 1;
80c39712
TV		 1956 }
1957
8b53d991 1958 return core_clk;
80c39712
TV		 1959}
1960
dcbe765b
CM		 1961static unsigned long calc_core_clk_24xx(enum omap_channel channel, u16 width,
1962 u16 height, u16 out_width, u16 out_height)
1963{
1964 unsigned long pclk = dispc_mgr_pclk_rate(channel);
1965
1966 if (height > out_height && width > out_width)
1967 return pclk * 4;
1968 else
1969 return pclk * 2;
1970}
1971
1972static unsigned long calc_core_clk_34xx(enum omap_channel channel, u16 width,
ff1b2cde 1973 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1974{
1975 unsigned int hf, vf;
79ee89cd 1976 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1977
1978 /*
1979 * FIXME how to determine the 'A' factor
1980 * for the no downscaling case ?
1981 */
1982
1983 if (width > 3 * out_width)
1984 hf = 4;
1985 else if (width > 2 * out_width)
1986 hf = 3;
1987 else if (width > out_width)
1988 hf = 2;
1989 else
1990 hf = 1;
80c39712
TV		 1991 if (height > out_height)
1992 vf = 2;
1993 else
1994 vf = 1;
1995
dcbe765b
CM		 1996 return pclk * vf * hf;
1997}
1998
1999static unsigned long calc_core_clk_44xx(enum omap_channel channel, u16 width,
2000 u16 height, u16 out_width, u16 out_height)
2001{
2002 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2003
2004 if (width > out_width)
2005 return DIV_ROUND_UP(pclk, out_width) * width;
2006 else
2007 return pclk;
2008}
2009
2010static int dispc_ovl_calc_scaling_24xx(enum omap_channel channel,
2011 const struct omap_video_timings *mgr_timings,
2012 u16 width, u16 height, u16 out_width, u16 out_height,
2013 enum omap_color_mode color_mode, bool *five_taps,
2014 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2015 u16 pos_x, unsigned long *core_clk)
2016{
2017 int error;
2018 u16 in_width, in_height;
2019 int min_factor = min(*decim_x, *decim_y);
2020 const int maxsinglelinewidth =
2021 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2022 *five_taps = false;
2023
2024 do {
2025 in_height = DIV_ROUND_UP(height, *decim_y);
2026 in_width = DIV_ROUND_UP(width, *decim_x);
2027 *core_clk = dispc.feat->calc_core_clk(channel, in_width,
2028 in_height, out_width, out_height);
2029 error = (in_width > maxsinglelinewidth || !*core_clk ||
2030 *core_clk > dispc_core_clk_rate());
2031 if (error) {
2032 if (*decim_x == *decim_y) {
2033 *decim_x = min_factor;
2034 ++*decim_y;
2035 } else {
2036 swap(*decim_x, *decim_y);
2037 if (*decim_x < *decim_y)
2038 ++*decim_x;
2039 }
2040 }
2041 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2042
2043 if (in_width > maxsinglelinewidth) {
2044 DSSERR("Cannot scale max input width exceeded");
2045 return -EINVAL;
2046 }
2047 return 0;
2048}
2049
2050static int dispc_ovl_calc_scaling_34xx(enum omap_channel channel,
2051 const struct omap_video_timings *mgr_timings,
2052 u16 width, u16 height, u16 out_width, u16 out_height,
2053 enum omap_color_mode color_mode, bool *five_taps,
2054 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2055 u16 pos_x, unsigned long *core_clk)
2056{
2057 int error;
2058 u16 in_width, in_height;
2059 int min_factor = min(*decim_x, *decim_y);
2060 const int maxsinglelinewidth =
2061 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2062
2063 do {
2064 in_height = DIV_ROUND_UP(height, *decim_y);
2065 in_width = DIV_ROUND_UP(width, *decim_x);
2066 *core_clk = calc_core_clk_five_taps(channel, mgr_timings,
2067 in_width, in_height, out_width, out_height, color_mode);
2068
2069 error = check_horiz_timing_omap3(channel, mgr_timings, pos_x,
2070 in_width, in_height, out_width, out_height);
2071
2072 if (in_width > maxsinglelinewidth)
2073 if (in_height > out_height &&
2074 in_height < out_height * 2)
2075 *five_taps = false;
2076 if (!*five_taps)
2077 *core_clk = dispc.feat->calc_core_clk(channel, in_width,
2078 in_height, out_width, out_height);
2079
2080 error = (error || in_width > maxsinglelinewidth * 2 ||
2081 (in_width > maxsinglelinewidth && *five_taps) ||
2082 !*core_clk || *core_clk > dispc_core_clk_rate());
2083 if (error) {
2084 if (*decim_x == *decim_y) {
2085 *decim_x = min_factor;
2086 ++*decim_y;
2087 } else {
2088 swap(*decim_x, *decim_y);
2089 if (*decim_x < *decim_y)
2090 ++*decim_x;
2091 }
2092 }
2093 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2094
2095 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width, height,
2096 out_width, out_height)){
2097 DSSERR("horizontal timing too tight\n");
2098 return -EINVAL;
7282f1b7 2099 }
dcbe765b
CM		 2100
2101 if (in_width > (maxsinglelinewidth * 2)) {
2102 DSSERR("Cannot setup scaling");
2103 DSSERR("width exceeds maximum width possible");
2104 return -EINVAL;
2105 }
2106
2107 if (in_width > maxsinglelinewidth && *five_taps) {
2108 DSSERR("cannot setup scaling with five taps");
2109 return -EINVAL;
2110 }
2111 return 0;
2112}
2113
2114static int dispc_ovl_calc_scaling_44xx(enum omap_channel channel,
2115 const struct omap_video_timings *mgr_timings,
2116 u16 width, u16 height, u16 out_width, u16 out_height,
2117 enum omap_color_mode color_mode, bool *five_taps,
2118 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2119 u16 pos_x, unsigned long *core_clk)
2120{
2121 u16 in_width, in_width_max;
2122 int decim_x_min = *decim_x;
2123 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2124 const int maxsinglelinewidth =
2125 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2126
2127 in_width_max = dispc_core_clk_rate() /
2128 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel), out_width);
2129 *decim_x = DIV_ROUND_UP(width, in_width_max);
2130
2131 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2132 if (*decim_x > *x_predecim)
2133 return -EINVAL;
2134
2135 do {
2136 in_width = DIV_ROUND_UP(width, *decim_x);
2137 } while (*decim_x <= *x_predecim &&
2138 in_width > maxsinglelinewidth && ++*decim_x);
2139
2140 if (in_width > maxsinglelinewidth) {
2141 DSSERR("Cannot scale width exceeds max line width");
2142 return -EINVAL;
2143 }
2144
2145 *core_clk = dispc.feat->calc_core_clk(channel, in_width, in_height,
2146 out_width, out_height);
2147 return 0;
80c39712
TV		 2148}
2149
79ad75f2 2150static int dispc_ovl_calc_scaling(enum omap_plane plane,
81ab95b7
AT		 2151 enum omap_channel channel,
2152 const struct omap_video_timings *mgr_timings,
2153 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2154 enum omap_color_mode color_mode, bool *five_taps,
7faa9233 2155 int *x_predecim, int *y_predecim, u16 pos_x)
79ad75f2
AT		 2156{
2157 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 2158 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2159 const int max_decim_limit = 16;
8b53d991 2160 unsigned long core_clk = 0;
dcbe765b 2161 int decim_x, decim_y, ret;
79ad75f2 2162
f95cb5eb
TV		 2163 if (width == out_width && height == out_height)
2164 return 0;
2165
2166 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2167 return -EINVAL;
79ad75f2 2168
aed74b55
CM		 2169 *x_predecim = max_decim_limit;
2170 *y_predecim = max_decim_limit;
2171
2172 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2173 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2174 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2175 color_mode == OMAP_DSS_COLOR_CLUT8) {
2176 *x_predecim = 1;
2177 *y_predecim = 1;
2178 *five_taps = false;
2179 return 0;
2180 }
2181
2182 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2183 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2184
aed74b55 2185 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2186 return -EINVAL;
2187
aed74b55 2188 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2189 return -EINVAL;
2190
dcbe765b
CM		 2191 ret = dispc.feat->calc_scaling(channel, mgr_timings, width, height,
2192 out_width, out_height, color_mode, five_taps, x_predecim,
2193 y_predecim, &decim_x, &decim_y, pos_x, &core_clk);
2194 if (ret)
2195 return ret;
79ad75f2 2196
8b53d991
CM		 2197 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2198 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2199
8b53d991 2200 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2201 DSSERR("failed to set up scaling, "
8b53d991
CM		 2202 "required core clk rate = %lu Hz, "
2203 "current core clk rate = %lu Hz\n",
2204 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2205 return -EINVAL;
2206 }
2207
aed74b55
CM		 2208 *x_predecim = decim_x;
2209 *y_predecim = decim_y;
79ad75f2
AT		 2210 return 0;
2211}
2212
a4273b7c 2213int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
8050cbe4 2214 bool replication, const struct omap_video_timings *mgr_timings)
80c39712 2215{
79ad75f2 2216 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 2217 bool five_taps = true;
80c39712 2218 bool fieldmode = 0;
79ad75f2 2219 int r, cconv = 0;
80c39712
TV		 2220 unsigned offset0, offset1;
2221 s32 row_inc;
2222 s32 pix_inc;
a4273b7c 2223 u16 frame_height = oi->height;
80c39712 2224 unsigned int field_offset = 0;
aed74b55
CM		 2225 u16 in_height = oi->height;
2226 u16 in_width = oi->width;
2227 u16 out_width, out_height;
2cc5d1af 2228 enum omap_channel channel;
aed74b55 2229 int x_predecim = 1, y_predecim = 1;
8050cbe4 2230 bool ilace = mgr_timings->interlace;
2cc5d1af
TV		 2231
2232 channel = dispc_ovl_get_channel_out(plane);
80c39712 2233
a4273b7c 2234 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 2235 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2236 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 2237 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2238 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 2239 oi->mirror, ilace, channel, replication);
e6d80f95 2240
a4273b7c 2241 if (oi->paddr == 0)
80c39712
TV		 2242 return -EINVAL;
2243
aed74b55
CM		 2244 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2245 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
cf073668 2246
aed74b55 2247 if (ilace && oi->height == out_height)
80c39712
TV		 2248 fieldmode = 1;
2249
2250 if (ilace) {
2251 if (fieldmode)
aed74b55 2252 in_height /= 2;
a4273b7c 2253 oi->pos_y /= 2;
aed74b55 2254 out_height /= 2;
80c39712
TV		 2255
2256 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2257 "out_height %d\n",
aed74b55 2258 in_height, oi->pos_y, out_height);
80c39712
TV		 2259 }
2260
a4273b7c 2261 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 2262 return -EINVAL;
2263
81ab95b7
AT		 2264 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2265 in_height, out_width, out_height, oi->color_mode,
2266 &five_taps, &x_predecim, &y_predecim, oi->pos_x);
79ad75f2
AT		 2267 if (r)
2268 return r;
80c39712 2269
aed74b55
CM		 2270 in_width = DIV_ROUND_UP(in_width, x_predecim);
2271 in_height = DIV_ROUND_UP(in_height, y_predecim);
2272
79ad75f2
AT		 2273 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2274 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2275 oi->color_mode == OMAP_DSS_COLOR_NV12)
2276 cconv = 1;
80c39712
TV		 2277
2278 if (ilace && !fieldmode) {
2279 /*
2280 * when downscaling the bottom field may have to start several
2281 * source lines below the top field. Unfortunately ACCUI
2282 * registers will only hold the fractional part of the offset
2283 * so the integer part must be added to the base address of the
2284 * bottom field.
2285 */
aed74b55 2286 if (!in_height || in_height == out_height)
80c39712
TV		 2287 field_offset = 0;
2288 else
aed74b55 2289 field_offset = in_height / out_height / 2;
80c39712
TV		 2290 }
2291
2292 /* Fields are independent but interleaved in memory. */
2293 if (fieldmode)
2294 field_offset = 1;
2295
c6eee968
TV		 2296 offset0 = 0;
2297 offset1 = 0;
2298 row_inc = 0;
2299 pix_inc = 0;
2300
65e006ff
CM		 2301 if (oi->rotation_type == OMAP_DSS_ROT_TILER)
2302 calc_tiler_rotation_offset(oi->screen_width, in_width,
2303 oi->color_mode, fieldmode, field_offset,
2304 &offset0, &offset1, &row_inc, &pix_inc,
2305 x_predecim, y_predecim);
2306 else if (oi->rotation_type == OMAP_DSS_ROT_DMA)
a4273b7c 2307 calc_dma_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2308 oi->screen_width, in_width, frame_height,
a4273b7c 2309 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2310 &offset0, &offset1, &row_inc, &pix_inc,
2311 x_predecim, y_predecim);
80c39712 2312 else
a4273b7c 2313 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2314 oi->screen_width, in_width, frame_height,
a4273b7c 2315 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2316 &offset0, &offset1, &row_inc, &pix_inc,
2317 x_predecim, y_predecim);
80c39712
TV		 2318
2319 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2320 offset0, offset1, row_inc, pix_inc);
2321
a4273b7c 2322 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 2323
65e006ff
CM		 2324 dispc_ovl_configure_burst_type(plane, oi->rotation_type);
2325
a4273b7c
AT		 2326 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2327 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 2328
a4273b7c
AT		 2329 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2330 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2331 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 2332 }
2333
2334
f0e5caab
TV		 2335 dispc_ovl_set_row_inc(plane, row_inc);
2336 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2337
aed74b55
CM		 2338 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2339 in_height, out_width, out_height);
80c39712 2340
a4273b7c 2341 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 2342
aed74b55 2343 dispc_ovl_set_pic_size(plane, in_width, in_height);
80c39712 2344
79ad75f2 2345 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2346 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2347 out_height, ilace, five_taps, fieldmode,
a4273b7c 2348 oi->color_mode, oi->rotation);
aed74b55 2349 dispc_ovl_set_vid_size(plane, out_width, out_height);
f0e5caab 2350 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2351 }
2352
a4273b7c
AT		 2353 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2354 oi->color_mode);
80c39712 2355
54128701 2356 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 2357 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2358 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 2359
c3d92529 2360 dispc_ovl_enable_replication(plane, replication);
c3d92529 2361
80c39712
TV		 2362 return 0;
2363}
2364
f0e5caab 2365int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2366{
e6d80f95
TV		 2367 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2368
9b372c2d 2369 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2370
2371 return 0;
80c39712
TV		 2372}
2373
2374static void dispc_disable_isr(void *data, u32 mask)
2375{
2376 struct completion *compl = data;
2377 complete(compl);
2378}
2379
2a205f34 2380static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2381{
efa70b3b
CM		 2382 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2383 /* flush posted write */
2384 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712
TV		 2385}
2386
26d9dd0d 2387static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2388{
2389 struct completion frame_done_completion;
2390 bool is_on;
2391 int r;
2a205f34 2392 u32 irq;
80c39712 2393
80c39712
TV		 2394 /* When we disable LCD output, we need to wait until frame is done.
2395 * Otherwise the DSS is still working, and turning off the clocks
2396 * prevents DSS from going to OFF mode */
efa70b3b 2397 is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2a205f34 2398
efa70b3b 2399 irq = mgr_desc[channel].framedone_irq;
80c39712
TV		 2400
2401 if (!enable && is_on) {
2402 init_completion(&frame_done_completion);
2403
2404 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2405 &frame_done_completion, irq);
80c39712
TV		 2406
2407 if (r)
2408 DSSERR("failed to register FRAMEDONE isr\n");
2409 }
2410
2a205f34 2411 _enable_lcd_out(channel, enable);
80c39712
TV		 2412
2413 if (!enable && is_on) {
2414 if (!wait_for_completion_timeout(&frame_done_completion,
2415 msecs_to_jiffies(100)))
2416 DSSERR("timeout waiting for FRAME DONE\n");
2417
2418 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2419 &frame_done_completion, irq);
80c39712
TV		 2420
2421 if (r)
2422 DSSERR("failed to unregister FRAMEDONE isr\n");
2423 }
80c39712
TV		 2424}
2425
2426static void _enable_digit_out(bool enable)
2427{
2428 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2429 /* flush posted write */
2430 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2431}
2432
26d9dd0d 2433static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2434{
2435 struct completion frame_done_completion;
e82b090b
TV		 2436 enum dss_hdmi_venc_clk_source_select src;
2437 int r, i;
2438 u32 irq_mask;
2439 int num_irqs;
80c39712 2440
e6d80f95 2441 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2442 return;
80c39712 2443
e82b090b
TV		 2444 src = dss_get_hdmi_venc_clk_source();
2445
80c39712
TV		 2446 if (enable) {
2447 unsigned long flags;
2448 /* When we enable digit output, we'll get an extra digit
2449 * sync lost interrupt, that we need to ignore */
2450 spin_lock_irqsave(&dispc.irq_lock, flags);
2451 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2452 _omap_dispc_set_irqs();
2453 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2454 }
2455
2456 /* When we disable digit output, we need to wait until fields are done.
2457 * Otherwise the DSS is still working, and turning off the clocks
2458 * prevents DSS from going to OFF mode. And when enabling, we need to
2459 * wait for the extra sync losts */
2460 init_completion(&frame_done_completion);
2461
e82b090b
TV		 2462 if (src == DSS_HDMI_M_PCLK && enable == false) {
2463 irq_mask = DISPC_IRQ_FRAMEDONETV;
2464 num_irqs = 1;
2465 } else {
2466 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2467 /* XXX I understand from TRM that we should only wait for the
2468 * current field to complete. But it seems we have to wait for
2469 * both fields */
2470 num_irqs = 2;
2471 }
2472
80c39712 2473 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2474 irq_mask);
80c39712 2475 if (r)
e82b090b 2476 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2477
2478 _enable_digit_out(enable);
2479
e82b090b
TV		 2480 for (i = 0; i < num_irqs; ++i) {
2481 if (!wait_for_completion_timeout(&frame_done_completion,
2482 msecs_to_jiffies(100)))
2483 DSSERR("timeout waiting for digit out to %s\n",
2484 enable ? "start" : "stop");
2485 }
80c39712 2486
e82b090b
TV		 2487 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2488 irq_mask);
80c39712 2489 if (r)
e82b090b 2490 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2491
2492 if (enable) {
2493 unsigned long flags;
2494 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2495 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2496 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2497 _omap_dispc_set_irqs();
2498 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2499 }
80c39712
TV		 2500}
2501
26d9dd0d 2502bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84 2503{
efa70b3b 2504 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
a2faee84
TV		 2505}
2506
26d9dd0d 2507void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2508{
dd88b7a6 2509 if (dss_mgr_is_lcd(channel))
26d9dd0d 2510 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2511 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2512 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2513 else
2514 BUG();
2515}
2516
80c39712
TV		 2517void dispc_lcd_enable_signal_polarity(bool act_high)
2518{
6ced40bf
AT		 2519 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2520 return;
2521
80c39712 2522 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2523}
2524
2525void dispc_lcd_enable_signal(bool enable)
2526{
6ced40bf
AT		 2527 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2528 return;
2529
80c39712 2530 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2531}
2532
2533void dispc_pck_free_enable(bool enable)
2534{
6ced40bf
AT		 2535 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2536 return;
2537
80c39712 2538 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2539}
2540
26d9dd0d 2541void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2542{
efa70b3b 2543 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2544}
2545
2546
d21f43bc 2547void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2548{
d21f43bc 2549 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2550}
2551
2552void dispc_set_loadmode(enum omap_dss_load_mode mode)
2553{
80c39712 2554 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2555}
2556
2557
c64dca40 2558static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2559{
8613b000 2560 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2561}
2562
c64dca40 2563static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2564 enum omap_dss_trans_key_type type,
2565 u32 trans_key)
2566{
efa70b3b 2567 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2568
8613b000 2569 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2570}
2571
c64dca40 2572static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2573{
efa70b3b 2574 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2575}
11354dd5 2576
c64dca40
TV		 2577static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2578 bool enable)
80c39712 2579{
11354dd5 2580 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2581 return;
2582
80c39712
TV		 2583 if (ch == OMAP_DSS_CHANNEL_LCD)
2584 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2585 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2586 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2587}
11354dd5 2588
c64dca40
TV		 2589void dispc_mgr_setup(enum omap_channel channel,
2590 struct omap_overlay_manager_info *info)
2591{
2592 dispc_mgr_set_default_color(channel, info->default_color);
2593 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2594 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2595 dispc_mgr_enable_alpha_fixed_zorder(channel,
2596 info->partial_alpha_enabled);
2597 if (dss_has_feature(FEAT_CPR)) {
2598 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2599 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2600 }
2601}
80c39712 2602
26d9dd0d 2603void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2604{
2605 int code;
2606
2607 switch (data_lines) {
2608 case 12:
2609 code = 0;
2610 break;
2611 case 16:
2612 code = 1;
2613 break;
2614 case 18:
2615 code = 2;
2616 break;
2617 case 24:
2618 code = 3;
2619 break;
2620 default:
2621 BUG();
2622 return;
2623 }
2624
efa70b3b 2625 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2626}
2627
569969d6 2628void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2629{
2630 u32 l;
569969d6 2631 int gpout0, gpout1;
80c39712
TV		 2632
2633 switch (mode) {
569969d6
AT		 2634 case DSS_IO_PAD_MODE_RESET:
2635 gpout0 = 0;
2636 gpout1 = 0;
80c39712 2637 break;
569969d6
AT		 2638 case DSS_IO_PAD_MODE_RFBI:
2639 gpout0 = 1;
80c39712
TV		 2640 gpout1 = 0;
2641 break;
569969d6
AT		 2642 case DSS_IO_PAD_MODE_BYPASS:
2643 gpout0 = 1;
80c39712
TV		 2644 gpout1 = 1;
2645 break;
80c39712
TV		 2646 default:
2647 BUG();
2648 return;
2649 }
2650
569969d6
AT		 2651 l = dispc_read_reg(DISPC_CONTROL);
2652 l = FLD_MOD(l, gpout0, 15, 15);
2653 l = FLD_MOD(l, gpout1, 16, 16);
2654 dispc_write_reg(DISPC_CONTROL, l);
2655}
2656
2657void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2658{
efa70b3b 2659 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2660}
2661
8f366162
AT		 2662static bool _dispc_mgr_size_ok(u16 width, u16 height)
2663{
2664 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2665 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2666}
2667
80c39712
TV		 2668static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2669 int vsw, int vfp, int vbp)
2670{
dcbe765b
CM		 2671 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2672 hfp < 1 || hfp > dispc.feat->hp_max ||
2673 hbp < 1 || hbp > dispc.feat->hp_max ||
2674 vsw < 1 || vsw > dispc.feat->sw_max ||
2675 vfp < 0 || vfp > dispc.feat->vp_max ||
2676 vbp < 0 || vbp > dispc.feat->vp_max)
2677 return false;
80c39712
TV		 2678 return true;
2679}
2680
8f366162 2681bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2682 const struct omap_video_timings *timings)
80c39712 2683{
8f366162
AT		 2684 bool timings_ok;
2685
2686 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2687
dd88b7a6 2688 if (dss_mgr_is_lcd(channel))
8f366162
AT		 2689 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2690 timings->hfp, timings->hbp,
2691 timings->vsw, timings->vfp,
2692 timings->vbp);
2693
2694 return timings_ok;
80c39712
TV		 2695}
2696
26d9dd0d 2697static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 2698 int hfp, int hbp, int vsw, int vfp, int vbp,
2699 enum omap_dss_signal_level vsync_level,
2700 enum omap_dss_signal_level hsync_level,
2701 enum omap_dss_signal_edge data_pclk_edge,
2702 enum omap_dss_signal_level de_level,
2703 enum omap_dss_signal_edge sync_pclk_edge)
2704
80c39712 2705{
655e2941
AT		 2706 u32 timing_h, timing_v, l;
2707 bool onoff, rf, ipc;
80c39712 2708
dcbe765b
CM		 2709 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2710 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2711 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2712 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2713 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2714 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 2715
64ba4f74
SS		 2716 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2717 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 2718
2719 switch (data_pclk_edge) {
2720 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2721 ipc = false;
2722 break;
2723 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2724 ipc = true;
2725 break;
2726 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2727 default:
2728 BUG();
2729 }
2730
2731 switch (sync_pclk_edge) {
2732 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2733 onoff = false;
2734 rf = false;
2735 break;
2736 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2737 onoff = true;
2738 rf = false;
2739 break;
2740 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2741 onoff = true;
2742 rf = true;
2743 break;
2744 default:
2745 BUG();
2746 };
2747
2748 l = dispc_read_reg(DISPC_POL_FREQ(channel));
2749 l |= FLD_VAL(onoff, 17, 17);
2750 l |= FLD_VAL(rf, 16, 16);
2751 l |= FLD_VAL(de_level, 15, 15);
2752 l |= FLD_VAL(ipc, 14, 14);
2753 l |= FLD_VAL(hsync_level, 13, 13);
2754 l |= FLD_VAL(vsync_level, 12, 12);
2755 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2756}
2757
2758/* change name to mode? */
c51d921a 2759void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2760 struct omap_video_timings *timings)
80c39712
TV		 2761{
2762 unsigned xtot, ytot;
2763 unsigned long ht, vt;
2aefad49 2764 struct omap_video_timings t = *timings;
80c39712 2765
2aefad49 2766 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 2767
2aefad49 2768 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 2769 BUG();
c6eee968
TV		 2770 return;
2771 }
80c39712 2772
dd88b7a6 2773 if (dss_mgr_is_lcd(channel)) {
2aefad49 2774 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 2775 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2776 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 2777
2aefad49
AT		 2778 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2779 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 2780
c51d921a
AT		 2781 ht = (timings->pixel_clock * 1000) / xtot;
2782 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2783
2784 DSSDBG("pck %u\n", timings->pixel_clock);
2785 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 2786 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 2787 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2788 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2789 t.de_level, t.sync_pclk_edge);
80c39712 2790
c51d921a 2791 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 2792 } else {
23c8f88e 2793 if (t.interlace == true)
2aefad49 2794 t.y_res /= 2;
c51d921a 2795 }
8f366162 2796
2aefad49 2797 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712
TV		 2798}
2799
26d9dd0d 2800static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2801 u16 pck_div)
80c39712
TV		 2802{
2803 BUG_ON(lck_div < 1);
9eaaf207 2804 BUG_ON(pck_div < 1);
80c39712 2805
ce7fa5eb 2806 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2807 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2808}
2809
26d9dd0d 2810static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2811 int *pck_div)
80c39712
TV		 2812{
2813 u32 l;
ce7fa5eb 2814 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2815 *lck_div = FLD_GET(l, 23, 16);
2816 *pck_div = FLD_GET(l, 7, 0);
2817}
2818
2819unsigned long dispc_fclk_rate(void)
2820{
a72b64b9 2821 struct platform_device *dsidev;
80c39712
TV		 2822 unsigned long r = 0;
2823
66534e8e 2824 switch (dss_get_dispc_clk_source()) {
89a35e51 2825 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2826 r = clk_get_rate(dispc.dss_clk);
66534e8e 2827 break;
89a35e51 2828 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2829 dsidev = dsi_get_dsidev_from_id(0);
2830 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2831 break;
5a8b572d
AT		 2832 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2833 dsidev = dsi_get_dsidev_from_id(1);
2834 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2835 break;
66534e8e
AT		 2836 default:
2837 BUG();
c6eee968 2838 return 0;
66534e8e
AT		 2839 }
2840
80c39712
TV		 2841 return r;
2842}
2843
26d9dd0d 2844unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2845{
a72b64b9 2846 struct platform_device *dsidev;
80c39712
TV		 2847 int lcd;
2848 unsigned long r;
2849 u32 l;
2850
ce7fa5eb 2851 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2852
2853 lcd = FLD_GET(l, 23, 16);
2854
ea75159e 2855 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2856 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2857 r = clk_get_rate(dispc.dss_clk);
ea75159e 2858 break;
89a35e51 2859 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2860 dsidev = dsi_get_dsidev_from_id(0);
2861 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2862 break;
5a8b572d
AT		 2863 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2864 dsidev = dsi_get_dsidev_from_id(1);
2865 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2866 break;
ea75159e
AT		 2867 default:
2868 BUG();
c6eee968 2869 return 0;
ea75159e 2870 }
80c39712
TV		 2871
2872 return r / lcd;
2873}
2874
26d9dd0d 2875unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2876{
80c39712 2877 unsigned long r;
80c39712 2878
dd88b7a6 2879 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 2880 int pcd;
2881 u32 l;
80c39712 2882
c3dc6a7a 2883 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2884
c3dc6a7a 2885 pcd = FLD_GET(l, 7, 0);
80c39712 2886
c3dc6a7a
AT		 2887 r = dispc_mgr_lclk_rate(channel);
2888
2889 return r / pcd;
2890 } else {
3fa03ba8 2891 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 2892
3fa03ba8
AT		 2893 source = dss_get_hdmi_venc_clk_source();
2894
2895 switch (source) {
2896 case DSS_VENC_TV_CLK:
c3dc6a7a 2897 return venc_get_pixel_clock();
3fa03ba8 2898 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 2899 return hdmi_get_pixel_clock();
2900 default:
2901 BUG();
c6eee968 2902 return 0;
c3dc6a7a
AT		 2903 }
2904 }
80c39712
TV		 2905}
2906
8b53d991
CM		 2907unsigned long dispc_core_clk_rate(void)
2908{
2909 int lcd;
2910 unsigned long fclk = dispc_fclk_rate();
2911
2912 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2913 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2914 else
2915 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2916
2917 return fclk / lcd;
2918}
2919
6f1891fc 2920static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 2921{
2922 int lcd, pcd;
6f1891fc
CM		 2923 enum omap_dss_clk_source lcd_clk_src;
2924
2925 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
2926
2927 lcd_clk_src = dss_get_lcd_clk_source(channel);
2928
2929 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
2930 dss_get_generic_clk_source_name(lcd_clk_src),
2931 dss_feat_get_clk_source_name(lcd_clk_src));
2932
2933 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
2934
2935 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2936 dispc_mgr_lclk_rate(channel), lcd);
2937 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2938 dispc_mgr_pclk_rate(channel), pcd);
2939}
2940
2941void dispc_dump_clocks(struct seq_file *s)
2942{
2943 int lcd;
0cf35df3 2944 u32 l;
89a35e51 2945 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 2946
4fbafaf3
TV		 2947 if (dispc_runtime_get())
2948 return;
80c39712 2949
80c39712
TV		 2950 seq_printf(s, "- DISPC -\n");
2951
067a57e4
AT		 2952 seq_printf(s, "dispc fclk source = %s (%s)\n",
2953 dss_get_generic_clk_source_name(dispc_clk_src),
2954 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2955
2956 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2957
0cf35df3
MR		 2958 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2959 seq_printf(s, "- DISPC-CORE-CLK -\n");
2960 l = dispc_read_reg(DISPC_DIVISOR);
2961 lcd = FLD_GET(l, 23, 16);
2962
2963 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2964 (dispc_fclk_rate()/lcd), lcd);
2965 }
2a205f34 2966
6f1891fc 2967 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 2968
6f1891fc
CM		 2969 if (dss_has_feature(FEAT_MGR_LCD2))
2970 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
2971 if (dss_has_feature(FEAT_MGR_LCD3))
2972 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 2973
2974 dispc_runtime_put();
80c39712
TV		 2975}
2976
dfc0fd8d
TV		 2977#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2978void dispc_dump_irqs(struct seq_file *s)
2979{
2980 unsigned long flags;
2981 struct dispc_irq_stats stats;
2982
2983 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2984
2985 stats = dispc.irq_stats;
2986 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2987 dispc.irq_stats.last_reset = jiffies;
2988
2989 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2990
2991 seq_printf(s, "period %u ms\n",
2992 jiffies_to_msecs(jiffies - stats.last_reset));
2993
2994 seq_printf(s, "irqs %d\n", stats.irq_count);
2995#define PIS(x) \
2996 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2997
2998 PIS(FRAMEDONE);
2999 PIS(VSYNC);
3000 PIS(EVSYNC_EVEN);
3001 PIS(EVSYNC_ODD);
3002 PIS(ACBIAS_COUNT_STAT);
3003 PIS(PROG_LINE_NUM);
3004 PIS(GFX_FIFO_UNDERFLOW);
3005 PIS(GFX_END_WIN);
3006 PIS(PAL_GAMMA_MASK);
3007 PIS(OCP_ERR);
3008 PIS(VID1_FIFO_UNDERFLOW);
3009 PIS(VID1_END_WIN);
3010 PIS(VID2_FIFO_UNDERFLOW);
3011 PIS(VID2_END_WIN);
b8c095b4
AT		 3012 if (dss_feat_get_num_ovls() > 3) {
3013 PIS(VID3_FIFO_UNDERFLOW);
3014 PIS(VID3_END_WIN);
3015 }
dfc0fd8d
TV		 3016 PIS(SYNC_LOST);
3017 PIS(SYNC_LOST_DIGIT);
3018 PIS(WAKEUP);
2a205f34
SS		 3019 if (dss_has_feature(FEAT_MGR_LCD2)) {
3020 PIS(FRAMEDONE2);
3021 PIS(VSYNC2);
3022 PIS(ACBIAS_COUNT_STAT2);
3023 PIS(SYNC_LOST2);
3024 }
6f1891fc
CM		 3025 if (dss_has_feature(FEAT_MGR_LCD3)) {
3026 PIS(FRAMEDONE3);
3027 PIS(VSYNC3);
3028 PIS(ACBIAS_COUNT_STAT3);
3029 PIS(SYNC_LOST3);
3030 }
dfc0fd8d
TV		 3031#undef PIS
3032}
dfc0fd8d
TV		 3033#endif
3034
e40402cf 3035static void dispc_dump_regs(struct seq_file *s)
80c39712 3036{
4dd2da15
AT		 3037 int i, j;
3038 const char *mgr_names[] = {
3039 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3040 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3041 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3042 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3043 };
3044 const char *ovl_names[] = {
3045 [OMAP_DSS_GFX] = "GFX",
3046 [OMAP_DSS_VIDEO1] = "VID1",
3047 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3048 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3049 };
3050 const char **p_names;
3051
9b372c2d 3052#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3053
4fbafaf3
TV		 3054 if (dispc_runtime_get())
3055 return;
80c39712 3056
5010be80 3057 /* DISPC common registers */
80c39712
TV		 3058 DUMPREG(DISPC_REVISION);
3059 DUMPREG(DISPC_SYSCONFIG);
3060 DUMPREG(DISPC_SYSSTATUS);
3061 DUMPREG(DISPC_IRQSTATUS);
3062 DUMPREG(DISPC_IRQENABLE);
3063 DUMPREG(DISPC_CONTROL);
3064 DUMPREG(DISPC_CONFIG);
3065 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3066 DUMPREG(DISPC_LINE_STATUS);
3067 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3068 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3069 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3070 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3071 if (dss_has_feature(FEAT_MGR_LCD2)) {
3072 DUMPREG(DISPC_CONTROL2);
3073 DUMPREG(DISPC_CONFIG2);
5010be80 3074 }
6f1891fc
CM		 3075 if (dss_has_feature(FEAT_MGR_LCD3)) {
3076 DUMPREG(DISPC_CONTROL3);
3077 DUMPREG(DISPC_CONFIG3);
3078 }
5010be80
AT		 3079
3080#undef DUMPREG
3081
3082#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 3083#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3084 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 3085 dispc_read_reg(DISPC_REG(i, r)))
3086
4dd2da15 3087 p_names = mgr_names;
5010be80 3088
4dd2da15
AT		 3089 /* DISPC channel specific registers */
3090 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3091 DUMPREG(i, DISPC_DEFAULT_COLOR);
3092 DUMPREG(i, DISPC_TRANS_COLOR);
3093 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3094
4dd2da15
AT		 3095 if (i == OMAP_DSS_CHANNEL_DIGIT)
3096 continue;
5010be80 3097
4dd2da15
AT		 3098 DUMPREG(i, DISPC_DEFAULT_COLOR);
3099 DUMPREG(i, DISPC_TRANS_COLOR);
3100 DUMPREG(i, DISPC_TIMING_H);
3101 DUMPREG(i, DISPC_TIMING_V);
3102 DUMPREG(i, DISPC_POL_FREQ);
3103 DUMPREG(i, DISPC_DIVISORo);
3104 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3105
4dd2da15
AT		 3106 DUMPREG(i, DISPC_DATA_CYCLE1);
3107 DUMPREG(i, DISPC_DATA_CYCLE2);
3108 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3109
332e9d70 3110 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3111 DUMPREG(i, DISPC_CPR_COEF_R);
3112 DUMPREG(i, DISPC_CPR_COEF_G);
3113 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3114 }
2a205f34 3115 }
80c39712 3116
4dd2da15
AT		 3117 p_names = ovl_names;
3118
3119 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3120 DUMPREG(i, DISPC_OVL_BA0);
3121 DUMPREG(i, DISPC_OVL_BA1);
3122 DUMPREG(i, DISPC_OVL_POSITION);
3123 DUMPREG(i, DISPC_OVL_SIZE);
3124 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3125 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3126 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3127 DUMPREG(i, DISPC_OVL_ROW_INC);
3128 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3129 if (dss_has_feature(FEAT_PRELOAD))
3130 DUMPREG(i, DISPC_OVL_PRELOAD);
3131
3132 if (i == OMAP_DSS_GFX) {
3133 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3134 DUMPREG(i, DISPC_OVL_TABLE_BA);
3135 continue;
3136 }
3137
3138 DUMPREG(i, DISPC_OVL_FIR);
3139 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3140 DUMPREG(i, DISPC_OVL_ACCU0);
3141 DUMPREG(i, DISPC_OVL_ACCU1);
3142 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3143 DUMPREG(i, DISPC_OVL_BA0_UV);
3144 DUMPREG(i, DISPC_OVL_BA1_UV);
3145 DUMPREG(i, DISPC_OVL_FIR2);
3146 DUMPREG(i, DISPC_OVL_ACCU2_0);
3147 DUMPREG(i, DISPC_OVL_ACCU2_1);
3148 }
3149 if (dss_has_feature(FEAT_ATTR2))
3150 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3151 if (dss_has_feature(FEAT_PRELOAD))
3152 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3153 }
5010be80
AT		 3154
3155#undef DISPC_REG
3156#undef DUMPREG
3157
3158#define DISPC_REG(plane, name, i) name(plane, i)
3159#define DUMPREG(plane, name, i) \
4dd2da15
AT		 3160 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3161 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 3162 dispc_read_reg(DISPC_REG(plane, name, i)))
3163
4dd2da15 3164 /* Video pipeline coefficient registers */
332e9d70 3165
4dd2da15
AT		 3166 /* start from OMAP_DSS_VIDEO1 */
3167 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3168 for (j = 0; j < 8; j++)
3169 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3170
4dd2da15
AT		 3171 for (j = 0; j < 8; j++)
3172 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3173
4dd2da15
AT		 3174 for (j = 0; j < 5; j++)
3175 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3176
4dd2da15
AT		 3177 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3178 for (j = 0; j < 8; j++)
3179 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3180 }
3181
3182 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3183 for (j = 0; j < 8; j++)
3184 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3185
3186 for (j = 0; j < 8; j++)
3187 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3188
3189 for (j = 0; j < 8; j++)
3190 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3191 }
332e9d70 3192 }
80c39712 3193
4fbafaf3 3194 dispc_runtime_put();
5010be80
AT		 3195
3196#undef DISPC_REG
80c39712
TV		 3197#undef DUMPREG
3198}
3199
80c39712 3200/* with fck as input clock rate, find dispc dividers that produce req_pck */
6d523e7b 3201void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
80c39712
TV		 3202 struct dispc_clock_info *cinfo)
3203{
9eaaf207 3204 u16 pcd_min, pcd_max;
80c39712
TV		 3205 unsigned long best_pck;
3206 u16 best_ld, cur_ld;
3207 u16 best_pd, cur_pd;
3208
9eaaf207
TV		 3209 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3210 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3211
80c39712
TV		 3212 best_pck = 0;
3213 best_ld = 0;
3214 best_pd = 0;
3215
3216 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3217 unsigned long lck = fck / cur_ld;
3218
9eaaf207 3219 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3220 unsigned long pck = lck / cur_pd;
3221 long old_delta = abs(best_pck - req_pck);
3222 long new_delta = abs(pck - req_pck);
3223
3224 if (best_pck == 0 || new_delta < old_delta) {
3225 best_pck = pck;
3226 best_ld = cur_ld;
3227 best_pd = cur_pd;
3228
3229 if (pck == req_pck)
3230 goto found;
3231 }
3232
3233 if (pck < req_pck)
3234 break;
3235 }
3236
3237 if (lck / pcd_min < req_pck)
3238 break;
3239 }
3240
3241found:
3242 cinfo->lck_div = best_ld;
3243 cinfo->pck_div = best_pd;
3244 cinfo->lck = fck / cinfo->lck_div;
3245 cinfo->pck = cinfo->lck / cinfo->pck_div;
3246}
3247
3248/* calculate clock rates using dividers in cinfo */
3249int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3250 struct dispc_clock_info *cinfo)
3251{
3252 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3253 return -EINVAL;
9eaaf207 3254 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3255 return -EINVAL;
3256
3257 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3258 cinfo->pck = cinfo->lck / cinfo->pck_div;
3259
3260 return 0;
3261}
3262
f0d08f89 3263void dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3264 struct dispc_clock_info *cinfo)
80c39712
TV		 3265{
3266 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3267 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3268
26d9dd0d 3269 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3270}
3271
26d9dd0d 3272int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3273 struct dispc_clock_info *cinfo)
80c39712
TV		 3274{
3275 unsigned long fck;
3276
3277 fck = dispc_fclk_rate();
3278
ce7fa5eb
MR		 3279 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3280 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3281
3282 cinfo->lck = fck / cinfo->lck_div;
3283 cinfo->pck = cinfo->lck / cinfo->pck_div;
3284
3285 return 0;
3286}
3287
3288/* dispc.irq_lock has to be locked by the caller */
3289static void _omap_dispc_set_irqs(void)
3290{
3291 u32 mask;
3292 u32 old_mask;
3293 int i;
3294 struct omap_dispc_isr_data *isr_data;
3295
3296 mask = dispc.irq_error_mask;
3297
3298 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3299 isr_data = &dispc.registered_isr[i];
3300
3301 if (isr_data->isr == NULL)
3302 continue;
3303
3304 mask |= isr_data->mask;
3305 }
3306
80c39712
TV		 3307 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3308 /* clear the irqstatus for newly enabled irqs */
3309 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3310
3311 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3312}
3313
3314int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3315{
3316 int i;
3317 int ret;
3318 unsigned long flags;
3319 struct omap_dispc_isr_data *isr_data;
3320
3321 if (isr == NULL)
3322 return -EINVAL;
3323
3324 spin_lock_irqsave(&dispc.irq_lock, flags);
3325
3326 /* check for duplicate entry */
3327 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3328 isr_data = &dispc.registered_isr[i];
3329 if (isr_data->isr == isr && isr_data->arg == arg &&
3330 isr_data->mask == mask) {
3331 ret = -EINVAL;
3332 goto err;
3333 }
3334 }
3335
3336 isr_data = NULL;
3337 ret = -EBUSY;
3338
3339 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3340 isr_data = &dispc.registered_isr[i];
3341
3342 if (isr_data->isr != NULL)
3343 continue;
3344
3345 isr_data->isr = isr;
3346 isr_data->arg = arg;
3347 isr_data->mask = mask;
3348 ret = 0;
3349
3350 break;
3351 }
3352
b9cb0984
TV		 3353 if (ret)
3354 goto err;
3355
80c39712
TV		 3356 _omap_dispc_set_irqs();
3357
3358 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3359
3360 return 0;
3361err:
3362 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3363
3364 return ret;
3365}
3366EXPORT_SYMBOL(omap_dispc_register_isr);
3367
3368int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3369{
3370 int i;
3371 unsigned long flags;
3372 int ret = -EINVAL;
3373 struct omap_dispc_isr_data *isr_data;
3374
3375 spin_lock_irqsave(&dispc.irq_lock, flags);
3376
3377 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3378 isr_data = &dispc.registered_isr[i];
3379 if (isr_data->isr != isr || isr_data->arg != arg ||
3380 isr_data->mask != mask)
3381 continue;
3382
3383 /* found the correct isr */
3384
3385 isr_data->isr = NULL;
3386 isr_data->arg = NULL;
3387 isr_data->mask = 0;
3388
3389 ret = 0;
3390 break;
3391 }
3392
3393 if (ret == 0)
3394 _omap_dispc_set_irqs();
3395
3396 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3397
3398 return ret;
3399}
3400EXPORT_SYMBOL(omap_dispc_unregister_isr);
3401
3402#ifdef DEBUG
3403static void print_irq_status(u32 status)
3404{
3405 if ((status & dispc.irq_error_mask) == 0)
3406 return;
3407
3408 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3409
3410#define PIS(x) \
3411 if (status & DISPC_IRQ_##x) \
3412 printk(#x " ");
3413 PIS(GFX_FIFO_UNDERFLOW);
3414 PIS(OCP_ERR);
3415 PIS(VID1_FIFO_UNDERFLOW);
3416 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3417 if (dss_feat_get_num_ovls() > 3)
3418 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3419 PIS(SYNC_LOST);
3420 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3421 if (dss_has_feature(FEAT_MGR_LCD2))
3422 PIS(SYNC_LOST2);
6f1891fc
CM		 3423 if (dss_has_feature(FEAT_MGR_LCD3))
3424 PIS(SYNC_LOST3);
80c39712
TV		 3425#undef PIS
3426
3427 printk("\n");
3428}
3429#endif
3430
3431/* Called from dss.c. Note that we don't touch clocks here,
3432 * but we presume they are on because we got an IRQ. However,
3433 * an irq handler may turn the clocks off, so we may not have
3434 * clock later in the function. */
affe360d 3435static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3436{
3437 int i;
affe360d 3438 u32 irqstatus, irqenable;
80c39712
TV		 3439 u32 handledirqs = 0;
3440 u32 unhandled_errors;
3441 struct omap_dispc_isr_data *isr_data;
3442 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3443
3444 spin_lock(&dispc.irq_lock);
3445
3446 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d
AT		 3447 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3448
3449 /* IRQ is not for us */
3450 if (!(irqstatus & irqenable)) {
3451 spin_unlock(&dispc.irq_lock);
3452 return IRQ_NONE;
3453 }
80c39712 3454
dfc0fd8d
TV		 3455#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3456 spin_lock(&dispc.irq_stats_lock);
3457 dispc.irq_stats.irq_count++;
3458 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3459 spin_unlock(&dispc.irq_stats_lock);
3460#endif
3461
80c39712
TV		 3462#ifdef DEBUG
3463 if (dss_debug)
3464 print_irq_status(irqstatus);
3465#endif
3466 /* Ack the interrupt. Do it here before clocks are possibly turned
3467 * off */
3468 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3469 /* flush posted write */
3470 dispc_read_reg(DISPC_IRQSTATUS);
3471
3472 /* make a copy and unlock, so that isrs can unregister
3473 * themselves */
3474 memcpy(registered_isr, dispc.registered_isr,
3475 sizeof(registered_isr));
3476
3477 spin_unlock(&dispc.irq_lock);
3478
3479 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3480 isr_data = &registered_isr[i];
3481
3482 if (!isr_data->isr)
3483 continue;
3484
3485 if (isr_data->mask & irqstatus) {
3486 isr_data->isr(isr_data->arg, irqstatus);
3487 handledirqs |= isr_data->mask;
3488 }
3489 }
3490
3491 spin_lock(&dispc.irq_lock);
3492
3493 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3494
3495 if (unhandled_errors) {
3496 dispc.error_irqs |= unhandled_errors;
3497
3498 dispc.irq_error_mask &= ~unhandled_errors;
3499 _omap_dispc_set_irqs();
3500
3501 schedule_work(&dispc.error_work);
3502 }
3503
3504 spin_unlock(&dispc.irq_lock);
affe360d
AT		 3505
3506 return IRQ_HANDLED;
80c39712
TV		 3507}
3508
3509static void dispc_error_worker(struct work_struct *work)
3510{
3511 int i;
3512 u32 errors;
3513 unsigned long flags;
fe3cc9d6
TV		 3514 static const unsigned fifo_underflow_bits[] = {
3515 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3516 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3517 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3518 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3519 };
3520
80c39712
TV		 3521 spin_lock_irqsave(&dispc.irq_lock, flags);
3522 errors = dispc.error_irqs;
3523 dispc.error_irqs = 0;
3524 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3525
13eae1f9
DZ		 3526 dispc_runtime_get();
3527
fe3cc9d6
TV		 3528 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3529 struct omap_overlay *ovl;
3530 unsigned bit;
80c39712 3531
fe3cc9d6
TV		 3532 ovl = omap_dss_get_overlay(i);
3533 bit = fifo_underflow_bits[i];
80c39712 3534
fe3cc9d6
TV		 3535 if (bit & errors) {
3536 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3537 ovl->name);
f0e5caab 3538 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3539 dispc_mgr_go(ovl->manager->id);
d7ad718d 3540 msleep(50);
80c39712
TV		 3541 }
3542 }
3543
fe3cc9d6
TV		 3544 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3545 struct omap_overlay_manager *mgr;
3546 unsigned bit;
80c39712 3547
fe3cc9d6 3548 mgr = omap_dss_get_overlay_manager(i);
efa70b3b 3549 bit = mgr_desc[i].sync_lost_irq;
80c39712 3550
fe3cc9d6
TV		 3551 if (bit & errors) {
3552 struct omap_dss_device *dssdev = mgr->device;
3553 bool enable;
80c39712 3554
fe3cc9d6
TV		 3555 DSSERR("SYNC_LOST on channel %s, restarting the output "
3556 "with video overlays disabled\n",
3557 mgr->name);
2a205f34 3558
fe3cc9d6
TV		 3559 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3560 dssdev->driver->disable(dssdev);
2a205f34 3561
2a205f34
SS		 3562 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3563 struct omap_overlay *ovl;
3564 ovl = omap_dss_get_overlay(i);
3565
fe3cc9d6
TV		 3566 if (ovl->id != OMAP_DSS_GFX &&
3567 ovl->manager == mgr)
f0e5caab 3568 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3569 }
3570
26d9dd0d 3571 dispc_mgr_go(mgr->id);
d7ad718d 3572 msleep(50);
fe3cc9d6 3573
2a205f34
SS		 3574 if (enable)
3575 dssdev->driver->enable(dssdev);
3576 }
3577 }
3578
80c39712
TV		 3579 if (errors & DISPC_IRQ_OCP_ERR) {
3580 DSSERR("OCP_ERR\n");
3581 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3582 struct omap_overlay_manager *mgr;
3583 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3584 if (mgr->device && mgr->device->driver)
3585 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3586 }
3587 }
3588
3589 spin_lock_irqsave(&dispc.irq_lock, flags);
3590 dispc.irq_error_mask |= errors;
3591 _omap_dispc_set_irqs();
3592 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3593
3594 dispc_runtime_put();
80c39712
TV		 3595}
3596
3597int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3598{
3599 void dispc_irq_wait_handler(void *data, u32 mask)
3600 {
3601 complete((struct completion *)data);
3602 }
3603
3604 int r;
3605 DECLARE_COMPLETION_ONSTACK(completion);
3606
3607 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3608 irqmask);
3609
3610 if (r)
3611 return r;
3612
3613 timeout = wait_for_completion_timeout(&completion, timeout);
3614
3615 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3616
3617 if (timeout == 0)
3618 return -ETIMEDOUT;
3619
3620 if (timeout == -ERESTARTSYS)
3621 return -ERESTARTSYS;
3622
3623 return 0;
3624}
3625
3626int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3627 unsigned long timeout)
3628{
3629 void dispc_irq_wait_handler(void *data, u32 mask)
3630 {
3631 complete((struct completion *)data);
3632 }
3633
3634 int r;
3635 DECLARE_COMPLETION_ONSTACK(completion);
3636
3637 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3638 irqmask);
3639
3640 if (r)
3641 return r;
3642
3643 timeout = wait_for_completion_interruptible_timeout(&completion,
3644 timeout);
3645
3646 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3647
3648 if (timeout == 0)
3649 return -ETIMEDOUT;
3650
3651 if (timeout == -ERESTARTSYS)
3652 return -ERESTARTSYS;
3653
3654 return 0;
3655}
3656
80c39712
TV		 3657static void _omap_dispc_initialize_irq(void)
3658{
3659 unsigned long flags;
3660
3661 spin_lock_irqsave(&dispc.irq_lock, flags);
3662
3663 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3664
3665 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3666 if (dss_has_feature(FEAT_MGR_LCD2))
3667 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
e86d456a
CM		 3668 if (dss_has_feature(FEAT_MGR_LCD3))
3669 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
b8c095b4
AT		 3670 if (dss_feat_get_num_ovls() > 3)
3671 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3672
3673 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3674 * so clear it */
3675 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3676
3677 _omap_dispc_set_irqs();
3678
3679 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3680}
3681
3682void dispc_enable_sidle(void)
3683{
3684 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3685}
3686
3687void dispc_disable_sidle(void)
3688{
3689 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3690}
3691
3692static void _omap_dispc_initial_config(void)
3693{
3694 u32 l;
3695
0cf35df3
MR		 3696 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3697 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3698 l = dispc_read_reg(DISPC_DIVISOR);
3699 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3700 l = FLD_MOD(l, 1, 0, 0);
3701 l = FLD_MOD(l, 1, 23, 16);
3702 dispc_write_reg(DISPC_DIVISOR, l);
3703 }
3704
80c39712 3705 /* FUNCGATED */
6ced40bf
AT		 3706 if (dss_has_feature(FEAT_FUNCGATED))
3707 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3708
80c39712
TV		 3709 _dispc_setup_color_conv_coef();
3710
3711 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3712
3713 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3714
3715 dispc_configure_burst_sizes();
54128701
AT		 3716
3717 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3718}
3719
dcbe765b
CM		 3720static const struct dispc_features omap24xx_dispc_feats __initconst = {
3721 .sw_start = 5,
3722 .fp_start = 15,
3723 .bp_start = 27,
3724 .sw_max = 64,
3725 .vp_max = 255,
3726 .hp_max = 256,
3727 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3728 .calc_core_clk = calc_core_clk_24xx,
3729};
3730
3731static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3732 .sw_start = 5,
3733 .fp_start = 15,
3734 .bp_start = 27,
3735 .sw_max = 64,
3736 .vp_max = 255,
3737 .hp_max = 256,
3738 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3739 .calc_core_clk = calc_core_clk_34xx,
3740};
3741
3742static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3743 .sw_start = 7,
3744 .fp_start = 19,
3745 .bp_start = 31,
3746 .sw_max = 256,
3747 .vp_max = 4095,
3748 .hp_max = 4096,
3749 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3750 .calc_core_clk = calc_core_clk_34xx,
3751};
3752
3753static const struct dispc_features omap44xx_dispc_feats __initconst = {
3754 .sw_start = 7,
3755 .fp_start = 19,
3756 .bp_start = 31,
3757 .sw_max = 256,
3758 .vp_max = 4095,
3759 .hp_max = 4096,
3760 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3761 .calc_core_clk = calc_core_clk_44xx,
3762};
3763
3764static int __init dispc_init_features(struct device *dev)
3765{
3766 const struct dispc_features *src;
3767 struct dispc_features *dst;
3768
3769 dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
3770 if (!dst) {
3771 dev_err(dev, "Failed to allocate DISPC Features\n");
3772 return -ENOMEM;
3773 }
3774
3775 if (cpu_is_omap24xx()) {
3776 src = &omap24xx_dispc_feats;
3777 } else if (cpu_is_omap34xx()) {
3778 if (omap_rev() < OMAP3430_REV_ES3_0)
3779 src = &omap34xx_rev1_0_dispc_feats;
3780 else
3781 src = &omap34xx_rev3_0_dispc_feats;
3782 } else if (cpu_is_omap44xx()) {
3783 src = &omap44xx_dispc_feats;
3784 } else {
3785 return -ENODEV;
3786 }
3787
3788 memcpy(dst, src, sizeof(*dst));
3789 dispc.feat = dst;
3790
3791 return 0;
3792}
3793
060b6d9c 3794/* DISPC HW IP initialisation */
6e7e8f06 3795static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3796{
3797 u32 rev;
affe360d 3798 int r = 0;
ea9da36a 3799 struct resource *dispc_mem;
4fbafaf3 3800 struct clk *clk;
ea9da36a 3801
060b6d9c
SG		 3802 dispc.pdev = pdev;
3803
dcbe765b
CM		 3804 r = dispc_init_features(&dispc.pdev->dev);
3805 if (r)
3806 return r;
3807
060b6d9c
SG		 3808 spin_lock_init(&dispc.irq_lock);
3809
3810#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3811 spin_lock_init(&dispc.irq_stats_lock);
3812 dispc.irq_stats.last_reset = jiffies;
3813#endif
3814
3815 INIT_WORK(&dispc.error_work, dispc_error_worker);
3816
ea9da36a
SG		 3817 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3818 if (!dispc_mem) {
3819 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3820 return -EINVAL;
ea9da36a 3821 }
cd3b3449 3822
6e2a14d2
JL		 3823 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3824 resource_size(dispc_mem));
060b6d9c
SG		 3825 if (!dispc.base) {
3826 DSSERR("can't ioremap DISPC\n");
cd3b3449 3827 return -ENOMEM;
affe360d 3828 }
cd3b3449 3829
affe360d
AT		 3830 dispc.irq = platform_get_irq(dispc.pdev, 0);
3831 if (dispc.irq < 0) {
3832 DSSERR("platform_get_irq failed\n");
cd3b3449 3833 return -ENODEV;
affe360d
AT		 3834 }
3835
6e2a14d2
JL		 3836 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3837 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d
AT		 3838 if (r < 0) {
3839 DSSERR("request_irq failed\n");
cd3b3449
TV		 3840 return r;
3841 }
3842
3843 clk = clk_get(&pdev->dev, "fck");
3844 if (IS_ERR(clk)) {
3845 DSSERR("can't get fck\n");
3846 r = PTR_ERR(clk);
3847 return r;
060b6d9c
SG		 3848 }
3849
cd3b3449
TV		 3850 dispc.dss_clk = clk;
3851
4fbafaf3
TV		 3852 pm_runtime_enable(&pdev->dev);
3853
3854 r = dispc_runtime_get();
3855 if (r)
3856 goto err_runtime_get;
060b6d9c
SG		 3857
3858 _omap_dispc_initial_config();
3859
3860 _omap_dispc_initialize_irq();
3861
060b6d9c 3862 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3863 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3864 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3865
4fbafaf3 3866 dispc_runtime_put();
060b6d9c 3867
e40402cf
TV		 3868 dss_debugfs_create_file("dispc", dispc_dump_regs);
3869
3870#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3871 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3872#endif
060b6d9c 3873 return 0;
4fbafaf3
TV		 3874
3875err_runtime_get:
3876 pm_runtime_disable(&pdev->dev);
4fbafaf3 3877 clk_put(dispc.dss_clk);
affe360d 3878 return r;
060b6d9c
SG		 3879}
3880
6e7e8f06 3881static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3882{
4fbafaf3
TV		 3883 pm_runtime_disable(&pdev->dev);
3884
3885 clk_put(dispc.dss_clk);
3886
060b6d9c
SG		 3887 return 0;
3888}
3889
4fbafaf3
TV		 3890static int dispc_runtime_suspend(struct device *dev)
3891{
3892 dispc_save_context();
4fbafaf3
TV		 3893
3894 return 0;
3895}
3896
3897static int dispc_runtime_resume(struct device *dev)
3898{
49ea86f3 3899 dispc_restore_context();
4fbafaf3
TV		 3900
3901 return 0;
3902}
3903
3904static const struct dev_pm_ops dispc_pm_ops = {
3905 .runtime_suspend = dispc_runtime_suspend,
3906 .runtime_resume = dispc_runtime_resume,
3907};
3908
060b6d9c 3909static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3910 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3911 .driver = {
3912 .name = "omapdss_dispc",
3913 .owner = THIS_MODULE,
4fbafaf3 3914 .pm = &dispc_pm_ops,
060b6d9c
SG		 3915 },
3916};
3917
6e7e8f06 3918int __init dispc_init_platform_driver(void)
060b6d9c 3919{
11436e1d 3920 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3921}
3922
6e7e8f06 3923void __exit dispc_uninit_platform_driver(void)
060b6d9c 3924{
04c742c3 3925 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3926}
kernel source for telekom puls (alcatel/mediatek)