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ARM: gpio: omap: convert drivers to use asm/gpio.h rather than mach/gpio.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / atmel_lcdfb.c
CommitLineData
14340586
NF		 1/*
2 * Driver for AT91/AT32 LCD Controller
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/dma-mapping.h>
14#include <linux/interrupt.h>
15#include <linux/clk.h>
16#include <linux/fb.h>
17#include <linux/init.h>
18#include <linux/delay.h>
a9a84c37 19#include <linux/backlight.h>
5a0e3ad6 20#include <linux/gfp.h>
14340586 21
a09e64fb
RK		 22#include <mach/board.h>
23#include <mach/cpu.h>
24#include <mach/gpio.h>
14340586
NF		 25
26#include <video/atmel_lcdc.h>
27
28#define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
29#define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
30
31/* configurable parameters */
32#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
53b7479b
NF		 33#define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */
34#define ATMEL_LCDC_FIFO_SIZE 512 /* words */
14340586
NF		 35
36#if defined(CONFIG_ARCH_AT91)
e730d8b0
HS		 37#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
38 | FBINFO_PARTIAL_PAN_OK \
39 | FBINFO_HWACCEL_YPAN)
14340586
NF		 40
41static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
42 struct fb_var_screeninfo *var)
43{
44
45}
46#elif defined(CONFIG_AVR32)
47#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
48 | FBINFO_PARTIAL_PAN_OK \
49 | FBINFO_HWACCEL_XPAN \
50 | FBINFO_HWACCEL_YPAN)
51
52static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
53 struct fb_var_screeninfo *var)
54{
55 u32 dma2dcfg;
56 u32 pixeloff;
57
58 pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f;
59
60 dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8;
61 dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
62 lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
63
64 /* Update configuration */
65 lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
66 lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
67 | ATMEL_LCDC_DMAUPDT);
68}
69#endif
70
7cdcdb69 71static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
a9a84c37
DB		 72 | ATMEL_LCDC_POL_POSITIVE
73 | ATMEL_LCDC_ENA_PWMENABLE;
74
75#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
76
77/* some bl->props field just changed */
78static int atmel_bl_update_status(struct backlight_device *bl)
79{
80 struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
81 int power = sinfo->bl_power;
82 int brightness = bl->props.brightness;
83
84 /* REVISIT there may be a meaningful difference between
85 * fb_blank and power ... there seem to be some cases
86 * this doesn't handle correctly.
87 */
88 if (bl->props.fb_blank != sinfo->bl_power)
89 power = bl->props.fb_blank;
90 else if (bl->props.power != sinfo->bl_power)
91 power = bl->props.power;
92
93 if (brightness < 0 && power == FB_BLANK_UNBLANK)
94 brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
95 else if (power != FB_BLANK_UNBLANK)
96 brightness = 0;
97
98 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
99 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
100 brightness ? contrast_ctr : 0);
101
102 bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
103
104 return 0;
105}
106
107static int atmel_bl_get_brightness(struct backlight_device *bl)
108{
109 struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
110
111 return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
112}
113
acc2472e 114static const struct backlight_ops atmel_lcdc_bl_ops = {
a9a84c37
DB		 115 .update_status = atmel_bl_update_status,
116 .get_brightness = atmel_bl_get_brightness,
117};
118
119static void init_backlight(struct atmel_lcdfb_info *sinfo)
120{
a19a6ee6 121 struct backlight_properties props;
a9a84c37
DB		 122 struct backlight_device *bl;
123
124 sinfo->bl_power = FB_BLANK_UNBLANK;
125
126 if (sinfo->backlight)
127 return;
128
a19a6ee6 129 memset(&props, 0, sizeof(struct backlight_properties));
bb7ca747 130 props.type = BACKLIGHT_RAW;
a19a6ee6
MG		 131 props.max_brightness = 0xff;
132 bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo,
133 &atmel_lcdc_bl_ops, &props);
cf7b9a1e 134 if (IS_ERR(bl)) {
a9a84c37
DB		 135 dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
136 PTR_ERR(bl));
137 return;
138 }
139 sinfo->backlight = bl;
140
141 bl->props.power = FB_BLANK_UNBLANK;
142 bl->props.fb_blank = FB_BLANK_UNBLANK;
a9a84c37
DB		 143 bl->props.brightness = atmel_bl_get_brightness(bl);
144}
145
146static void exit_backlight(struct atmel_lcdfb_info *sinfo)
147{
148 if (sinfo->backlight)
149 backlight_device_unregister(sinfo->backlight);
150}
151
152#else
153
154static void init_backlight(struct atmel_lcdfb_info *sinfo)
155{
156 dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
157}
158
159static void exit_backlight(struct atmel_lcdfb_info *sinfo)
160{
161}
162
163#endif
164
165static void init_contrast(struct atmel_lcdfb_info *sinfo)
166{
7cdcdb69
AB		 167 /* contrast pwm can be 'inverted' */
168 if (sinfo->lcdcon_pol_negative)
169 contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
170
a9a84c37
DB		 171 /* have some default contrast/backlight settings */
172 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
173 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
174
175 if (sinfo->lcdcon_is_backlight)
176 init_backlight(sinfo);
177}
178
14340586
NF		 179
180static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
181 .type = FB_TYPE_PACKED_PIXELS,
182 .visual = FB_VISUAL_TRUECOLOR,
183 .xpanstep = 0,
e730d8b0 184 .ypanstep = 1,
14340586
NF		 185 .ywrapstep = 0,
186 .accel = FB_ACCEL_NONE,
187};
188
250a269d
NF		 189static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
190{
191 unsigned long value;
192
915190f7
NF		 193 if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
194 || cpu_is_at32ap7000()))
250a269d
NF		 195 return xres;
196
197 value = xres;
198 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
199 /* STN display */
200 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
201 value *= 3;
202 }
203 if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
204 || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
205 && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
206 value = DIV_ROUND_UP(value, 4);
207 else
208 value = DIV_ROUND_UP(value, 8);
209 }
210
211 return value;
212}
14340586 213
3aa04f1b
HS		 214static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
215{
216 /* Turn off the LCD controller and the DMA controller */
217 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
218 sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
219
220 /* Wait for the LCDC core to become idle */
221 while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
222 msleep(10);
223
224 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
225}
226
227static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
228{
229 atmel_lcdfb_stop_nowait(sinfo);
230
231 /* Wait for DMA engine to become idle... */
232 while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
233 msleep(10);
234}
235
236static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
237{
238 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
239 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
240 (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
241 | ATMEL_LCDC_PWR);
242}
243
14340586
NF		 244static void atmel_lcdfb_update_dma(struct fb_info *info,
245 struct fb_var_screeninfo *var)
246{
247 struct atmel_lcdfb_info *sinfo = info->par;
248 struct fb_fix_screeninfo *fix = &info->fix;
249 unsigned long dma_addr;
250
251 dma_addr = (fix->smem_start + var->yoffset * fix->line_length
252 + var->xoffset * var->bits_per_pixel / 8);
253
254 dma_addr &= ~3UL;
255
256 /* Set framebuffer DMA base address and pixel offset */
257 lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
258
259 atmel_lcdfb_update_dma2d(sinfo, var);
260}
261
262static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
263{
264 struct fb_info *info = sinfo->info;
265
266 dma_free_writecombine(info->device, info->fix.smem_len,
267 info->screen_base, info->fix.smem_start);
268}
269
270/**
271 * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
272 * @sinfo: the frame buffer to allocate memory for
1d01e835
KH		 273 *
274 * This function is called only from the atmel_lcdfb_probe()
275 * so no locking by fb_info->mm_lock around smem_len setting is needed.
14340586
NF		 276 */
277static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
278{
279 struct fb_info *info = sinfo->info;
280 struct fb_var_screeninfo *var = &info->var;
ea757aca 281 unsigned int smem_len;
14340586 282
ea757aca
HS		 283 smem_len = (var->xres_virtual * var->yres_virtual
284 * ((var->bits_per_pixel + 7) / 8));
285 info->fix.smem_len = max(smem_len, sinfo->smem_len);
14340586
NF		 286
287 info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len,
288 (dma_addr_t *)&info->fix.smem_start, GFP_KERNEL);
289
290 if (!info->screen_base) {
291 return -ENOMEM;
292 }
293
01d3a5e7
HS		 294 memset(info->screen_base, 0, info->fix.smem_len);
295
14340586
NF		 296 return 0;
297}
298
968910bd
NF		 299static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var,
300 struct fb_info *info)
301{
302 struct fb_videomode varfbmode;
303 const struct fb_videomode *fbmode = NULL;
304
305 fb_var_to_videomode(&varfbmode, var);
306 fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist);
307 if (fbmode)
308 fb_videomode_to_var(var, fbmode);
309 return fbmode;
310}
311
312
14340586
NF		 313/**
314 * atmel_lcdfb_check_var - Validates a var passed in.
315 * @var: frame buffer variable screen structure
316 * @info: frame buffer structure that represents a single frame buffer
317 *
318 * Checks to see if the hardware supports the state requested by
319 * var passed in. This function does not alter the hardware
320 * state!!! This means the data stored in struct fb_info and
321 * struct atmel_lcdfb_info do not change. This includes the var
322 * inside of struct fb_info. Do NOT change these. This function
323 * can be called on its own if we intent to only test a mode and
324 * not actually set it. The stuff in modedb.c is a example of
325 * this. If the var passed in is slightly off by what the
326 * hardware can support then we alter the var PASSED in to what
327 * we can do. If the hardware doesn't support mode change a
328 * -EINVAL will be returned by the upper layers. You don't need
329 * to implement this function then. If you hardware doesn't
330 * support changing the resolution then this function is not
331 * needed. In this case the driver would just provide a var that
332 * represents the static state the screen is in.
333 *
334 * Returns negative errno on error, or zero on success.
335 */
336static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
337 struct fb_info *info)
338{
339 struct device *dev = info->device;
340 struct atmel_lcdfb_info *sinfo = info->par;
341 unsigned long clk_value_khz;
342
343 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
344
345 dev_dbg(dev, "%s:\n", __func__);
968910bd
NF		 346
347 if (!(var->pixclock && var->bits_per_pixel)) {
348 /* choose a suitable mode if possible */
349 if (!atmel_lcdfb_choose_mode(var, info)) {
350 dev_err(dev, "needed value not specified\n");
351 return -EINVAL;
352 }
353 }
354
14340586
NF		 355 dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres);
356 dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock));
357 dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel);
358 dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz);
359
97b9a5a2 360 if (PICOS2KHZ(var->pixclock) > clk_value_khz) {
14340586
NF		 361 dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
362 return -EINVAL;
363 }
364
968910bd
NF		 365 /* Do not allow to have real resoulution larger than virtual */
366 if (var->xres > var->xres_virtual)
367 var->xres_virtual = var->xres;
368
369 if (var->yres > var->yres_virtual)
370 var->yres_virtual = var->yres;
371
14340586
NF		 372 /* Force same alignment for each line */
373 var->xres = (var->xres + 3) & ~3UL;
374 var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
375
376 var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
377 var->transp.msb_right = 0;
378 var->transp.offset = var->transp.length = 0;
379 var->xoffset = var->yoffset = 0;
380
f928ac0a
SG		 381 if (info->fix.smem_len) {
382 unsigned int smem_len = (var->xres_virtual * var->yres_virtual
383 * ((var->bits_per_pixel + 7) / 8));
384 if (smem_len > info->fix.smem_len)
385 return -EINVAL;
386 }
387
162b3a08
HS		 388 /* Saturate vertical and horizontal timings at maximum values */
389 var->vsync_len = min_t(u32, var->vsync_len,
390 (ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
391 var->upper_margin = min_t(u32, var->upper_margin,
392 ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
393 var->lower_margin = min_t(u32, var->lower_margin,
394 ATMEL_LCDC_VFP);
395 var->right_margin = min_t(u32, var->right_margin,
396 (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
397 var->hsync_len = min_t(u32, var->hsync_len,
398 (ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
399 var->left_margin = min_t(u32, var->left_margin,
400 ATMEL_LCDC_HBP + 1);
401
402 /* Some parameters can't be zero */
403 var->vsync_len = max_t(u32, var->vsync_len, 1);
404 var->right_margin = max_t(u32, var->right_margin, 1);
405 var->hsync_len = max_t(u32, var->hsync_len, 1);
406 var->left_margin = max_t(u32, var->left_margin, 1);
407
14340586 408 switch (var->bits_per_pixel) {
250a269d 409 case 1:
14340586
NF		 410 case 2:
411 case 4:
412 case 8:
413 var->red.offset = var->green.offset = var->blue.offset = 0;
414 var->red.length = var->green.length = var->blue.length
415 = var->bits_per_pixel;
416 break;
417 case 15:
418 case 16:
fd085801
NF		 419 if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
420 /* RGB:565 mode */
421 var->red.offset = 11;
422 var->blue.offset = 0;
423 var->green.length = 6;
fbd03a1c
GG		 424 } else if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB555) {
425 var->red.offset = 10;
426 var->blue.offset = 0;
427 var->green.length = 5;
fd085801
NF		 428 } else {
429 /* BGR:555 mode */
430 var->red.offset = 0;
431 var->blue.offset = 10;
432 var->green.length = 5;
433 }
14340586 434 var->green.offset = 5;
fd085801 435 var->red.length = var->blue.length = 5;
14340586 436 break;
14340586 437 case 32:
4440e0e1
HS		 438 var->transp.offset = 24;
439 var->transp.length = 8;
440 /* fall through */
441 case 24:
fd085801
NF		 442 if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
443 /* RGB:888 mode */
444 var->red.offset = 16;
445 var->blue.offset = 0;
446 } else {
447 /* BGR:888 mode */
448 var->red.offset = 0;
449 var->blue.offset = 16;
450 }
14340586 451 var->green.offset = 8;
14340586
NF		 452 var->red.length = var->green.length = var->blue.length = 8;
453 break;
454 default:
455 dev_err(dev, "color depth %d not supported\n",
456 var->bits_per_pixel);
457 return -EINVAL;
458 }
459
460 return 0;
461}
462
d22579b8
NF		 463/*
464 * LCD reset sequence
465 */
466static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
467{
468 might_sleep();
469
3aa04f1b
HS		 470 atmel_lcdfb_stop(sinfo);
471 atmel_lcdfb_start(sinfo);
d22579b8
NF		 472}
473
14340586
NF		 474/**
475 * atmel_lcdfb_set_par - Alters the hardware state.
476 * @info: frame buffer structure that represents a single frame buffer
477 *
478 * Using the fb_var_screeninfo in fb_info we set the resolution
479 * of the this particular framebuffer. This function alters the
480 * par AND the fb_fix_screeninfo stored in fb_info. It doesn't
481 * not alter var in fb_info since we are using that data. This
482 * means we depend on the data in var inside fb_info to be
483 * supported by the hardware. atmel_lcdfb_check_var is always called
484 * before atmel_lcdfb_set_par to ensure this. Again if you can't
485 * change the resolution you don't need this function.
486 *
487 */
488static int atmel_lcdfb_set_par(struct fb_info *info)
489{
490 struct atmel_lcdfb_info *sinfo = info->par;
250a269d 491 unsigned long hozval_linesz;
14340586
NF		 492 unsigned long value;
493 unsigned long clk_value_khz;
250a269d 494 unsigned long bits_per_line;
431861cf 495 unsigned long pix_factor = 2;
14340586 496
d22579b8
NF		 497 might_sleep();
498
14340586
NF		 499 dev_dbg(info->device, "%s:\n", __func__);
500 dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
501 info->var.xres, info->var.yres,
502 info->var.xres_virtual, info->var.yres_virtual);
503
3aa04f1b 504 atmel_lcdfb_stop_nowait(sinfo);
14340586 505
250a269d
NF		 506 if (info->var.bits_per_pixel == 1)
507 info->fix.visual = FB_VISUAL_MONO01;
508 else if (info->var.bits_per_pixel <= 8)
14340586
NF		 509 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
510 else
511 info->fix.visual = FB_VISUAL_TRUECOLOR;
512
250a269d
NF		 513 bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
514 info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
14340586
NF		 515
516 /* Re-initialize the DMA engine... */
517 dev_dbg(info->device, " * update DMA engine\n");
518 atmel_lcdfb_update_dma(info, &info->var);
519
520 /* ...set frame size and burst length = 8 words (?) */
521 value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
522 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
523 lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
524
525 /* Now, the LCDC core... */
526
527 /* Set pixel clock */
431861cf
NF		 528 if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
529 pix_factor = 1;
530
14340586
NF		 531 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
532
250a269d 533 value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
14340586 534
431861cf 535 if (value < pix_factor) {
14340586
NF		 536 dev_notice(info->device, "Bypassing pixel clock divider\n");
537 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
250a269d 538 } else {
431861cf 539 value = (value / pix_factor) - 1;
baf6332a
NF		 540 dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n",
541 value);
542 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
543 value << ATMEL_LCDC_CLKVAL_OFFSET);
431861cf
NF		 544 info->var.pixclock =
545 KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
250a269d
NF		 546 dev_dbg(info->device, " updated pixclk: %lu KHz\n",
547 PICOS2KHZ(info->var.pixclock));
548 }
549
14340586
NF		 550
551 /* Initialize control register 2 */
552 value = sinfo->default_lcdcon2;
553
554 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
555 value |= ATMEL_LCDC_INVLINE_INVERTED;
556 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
557 value |= ATMEL_LCDC_INVFRAME_INVERTED;
558
559 switch (info->var.bits_per_pixel) {
560 case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
561 case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
562 case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
563 case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
564 case 15: /* fall through */
565 case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
566 case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
567 case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
568 default: BUG(); break;
569 }
570 dev_dbg(info->device, " * LCDCON2 = %08lx\n", value);
571 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
572
573 /* Vertical timing */
574 value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
575 value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
576 value |= info->var.lower_margin;
577 dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value);
578 lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
579
580 /* Horizontal timing */
581 value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
582 value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
583 value |= (info->var.left_margin - 1);
584 dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
585 lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
586
250a269d
NF		 587 /* Horizontal value (aka line size) */
588 hozval_linesz = compute_hozval(info->var.xres,
589 lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
590
14340586 591 /* Display size */
250a269d 592 value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
14340586 593 value |= info->var.yres - 1;
250a269d 594 dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
14340586
NF		 595 lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
596
597 /* FIFO Threshold: Use formula from data sheet */
598 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
599 lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
600
601 /* Toggle LCD_MODE every frame */
602 lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
603
604 /* Disable all interrupts */
605 lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
d22579b8
NF		 606 /* Enable FIFO & DMA errors */
607 lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
14340586 608
14340586
NF		 609 /* ...wait for DMA engine to become idle... */
610 while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
611 msleep(10);
612
3aa04f1b 613 atmel_lcdfb_start(sinfo);
14340586
NF		 614
615 dev_dbg(info->device, " * DONE\n");
616
617 return 0;
618}
619
620static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
621{
622 chan &= 0xffff;
623 chan >>= 16 - bf->length;
624 return chan << bf->offset;
625}
626
627/**
628 * atmel_lcdfb_setcolreg - Optional function. Sets a color register.
629 * @regno: Which register in the CLUT we are programming
630 * @red: The red value which can be up to 16 bits wide
631 * @green: The green value which can be up to 16 bits wide
632 * @blue: The blue value which can be up to 16 bits wide.
633 * @transp: If supported the alpha value which can be up to 16 bits wide.
634 * @info: frame buffer info structure
635 *
636 * Set a single color register. The values supplied have a 16 bit
637 * magnitude which needs to be scaled in this function for the hardware.
638 * Things to take into consideration are how many color registers, if
639 * any, are supported with the current color visual. With truecolor mode
25985edc 640 * no color palettes are supported. Here a pseudo palette is created
14340586
NF		 641 * which we store the value in pseudo_palette in struct fb_info. For
642 * pseudocolor mode we have a limited color palette. To deal with this
643 * we can program what color is displayed for a particular pixel value.
644 * DirectColor is similar in that we can program each color field. If
645 * we have a static colormap we don't need to implement this function.
646 *
647 * Returns negative errno on error, or zero on success. In an
648 * ideal world, this would have been the case, but as it turns
649 * out, the other drivers return 1 on failure, so that's what
650 * we're going to do.
651 */
652static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
653 unsigned int green, unsigned int blue,
654 unsigned int transp, struct fb_info *info)
655{
656 struct atmel_lcdfb_info *sinfo = info->par;
657 unsigned int val;
658 u32 *pal;
659 int ret = 1;
660
661 if (info->var.grayscale)
662 red = green = blue = (19595 * red + 38470 * green
663 + 7471 * blue) >> 16;
664
665 switch (info->fix.visual) {
666 case FB_VISUAL_TRUECOLOR:
667 if (regno < 16) {
668 pal = info->pseudo_palette;
669
670 val = chan_to_field(red, &info->var.red);
671 val |= chan_to_field(green, &info->var.green);
672 val |= chan_to_field(blue, &info->var.blue);
673
674 pal[regno] = val;
675 ret = 0;
676 }
677 break;
678
679 case FB_VISUAL_PSEUDOCOLOR:
680 if (regno < 256) {
681 val = ((red >> 11) & 0x001f);
682 val |= ((green >> 6) & 0x03e0);
683 val |= ((blue >> 1) & 0x7c00);
684
685 /*
686 * TODO: intensity bit. Maybe something like
687 * ~(red[10] ^ green[10] ^ blue[10]) & 1
688 */
689
690 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
691 ret = 0;
692 }
693 break;
250a269d
NF		 694
695 case FB_VISUAL_MONO01:
696 if (regno < 2) {
697 val = (regno == 0) ? 0x00 : 0x1F;
698 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
699 ret = 0;
700 }
701 break;
702
14340586
NF		 703 }
704
705 return ret;
706}
707
708static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
709 struct fb_info *info)
710{
711 dev_dbg(info->device, "%s\n", __func__);
712
713 atmel_lcdfb_update_dma(info, var);
714
715 return 0;
716}
717
bed7bddb
AB		 718static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info)
719{
720 struct atmel_lcdfb_info *sinfo = info->par;
721
722 switch (blank_mode) {
723 case FB_BLANK_UNBLANK:
724 case FB_BLANK_NORMAL:
725 atmel_lcdfb_start(sinfo);
726 break;
727 case FB_BLANK_VSYNC_SUSPEND:
728 case FB_BLANK_HSYNC_SUSPEND:
729 break;
730 case FB_BLANK_POWERDOWN:
731 atmel_lcdfb_stop(sinfo);
732 break;
733 default:
734 return -EINVAL;
735 }
736
737 /* let fbcon do a soft blank for us */
738 return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
739}
740
14340586
NF		 741static struct fb_ops atmel_lcdfb_ops = {
742 .owner = THIS_MODULE,
743 .fb_check_var = atmel_lcdfb_check_var,
744 .fb_set_par = atmel_lcdfb_set_par,
745 .fb_setcolreg = atmel_lcdfb_setcolreg,
bed7bddb 746 .fb_blank = atmel_lcdfb_blank,
14340586
NF		 747 .fb_pan_display = atmel_lcdfb_pan_display,
748 .fb_fillrect = cfb_fillrect,
749 .fb_copyarea = cfb_copyarea,
750 .fb_imageblit = cfb_imageblit,
751};
752
753static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
754{
755 struct fb_info *info = dev_id;
756 struct atmel_lcdfb_info *sinfo = info->par;
757 u32 status;
758
759 status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
d22579b8
NF		 760 if (status & ATMEL_LCDC_UFLWI) {
761 dev_warn(info->device, "FIFO underflow %#x\n", status);
762 /* reset DMA and FIFO to avoid screen shifting */
763 schedule_work(&sinfo->task);
764 }
765 lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
14340586
NF		 766 return IRQ_HANDLED;
767}
768
d22579b8
NF		 769/*
770 * LCD controller task (to reset the LCD)
771 */
772static void atmel_lcdfb_task(struct work_struct *work)
773{
774 struct atmel_lcdfb_info *sinfo =
775 container_of(work, struct atmel_lcdfb_info, task);
776
777 atmel_lcdfb_reset(sinfo);
778}
779
14340586
NF		 780static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
781{
782 struct fb_info *info = sinfo->info;
783 int ret = 0;
784
14340586
NF		 785 info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
786
787 dev_info(info->device,
788 "%luKiB frame buffer at %08lx (mapped at %p)\n",
789 (unsigned long)info->fix.smem_len / 1024,
790 (unsigned long)info->fix.smem_start,
791 info->screen_base);
792
793 /* Allocate colormap */
794 ret = fb_alloc_cmap(&info->cmap, 256, 0);
795 if (ret < 0)
796 dev_err(info->device, "Alloc color map failed\n");
797
798 return ret;
799}
800
801static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
802{
803 if (sinfo->bus_clk)
804 clk_enable(sinfo->bus_clk);
805 clk_enable(sinfo->lcdc_clk);
806}
807
808static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
809{
810 if (sinfo->bus_clk)
811 clk_disable(sinfo->bus_clk);
812 clk_disable(sinfo->lcdc_clk);
813}
814
815
816static int __init atmel_lcdfb_probe(struct platform_device *pdev)
817{
818 struct device *dev = &pdev->dev;
819 struct fb_info *info;
820 struct atmel_lcdfb_info *sinfo;
821 struct atmel_lcdfb_info *pdata_sinfo;
968910bd 822 struct fb_videomode fbmode;
14340586
NF		 823 struct resource *regs = NULL;
824 struct resource *map = NULL;
825 int ret;
826
827 dev_dbg(dev, "%s BEGIN\n", __func__);
828
829 ret = -ENOMEM;
830 info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
831 if (!info) {
832 dev_err(dev, "cannot allocate memory\n");
833 goto out;
834 }
835
836 sinfo = info->par;
837
838 if (dev->platform_data) {
839 pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data;
840 sinfo->default_bpp = pdata_sinfo->default_bpp;
841 sinfo->default_dmacon = pdata_sinfo->default_dmacon;
842 sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2;
843 sinfo->default_monspecs = pdata_sinfo->default_monspecs;
844 sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
845 sinfo->guard_time = pdata_sinfo->guard_time;
ea757aca 846 sinfo->smem_len = pdata_sinfo->smem_len;
a9a84c37 847 sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
7cdcdb69 848 sinfo->lcdcon_pol_negative = pdata_sinfo->lcdcon_pol_negative;
fd085801 849 sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode;
14340586
NF		 850 } else {
851 dev_err(dev, "cannot get default configuration\n");
852 goto free_info;
853 }
854 sinfo->info = info;
855 sinfo->pdev = pdev;
856
857 strcpy(info->fix.id, sinfo->pdev->name);
858 info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
859 info->pseudo_palette = sinfo->pseudo_palette;
860 info->fbops = &atmel_lcdfb_ops;
861
862 memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
863 info->fix = atmel_lcdfb_fix;
864
865 /* Enable LCDC Clocks */
915190f7
NF		 866 if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()
867 || cpu_is_at32ap7000()) {
14340586
NF		 868 sinfo->bus_clk = clk_get(dev, "hck1");
869 if (IS_ERR(sinfo->bus_clk)) {
870 ret = PTR_ERR(sinfo->bus_clk);
871 goto free_info;
872 }
873 }
874 sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
875 if (IS_ERR(sinfo->lcdc_clk)) {
876 ret = PTR_ERR(sinfo->lcdc_clk);
877 goto put_bus_clk;
878 }
879 atmel_lcdfb_start_clock(sinfo);
880
881 ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
882 info->monspecs.modedb_len, info->monspecs.modedb,
883 sinfo->default_bpp);
884 if (!ret) {
885 dev_err(dev, "no suitable video mode found\n");
886 goto stop_clk;
887 }
888
889
890 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
891 if (!regs) {
892 dev_err(dev, "resources unusable\n");
893 ret = -ENXIO;
894 goto stop_clk;
895 }
896
897 sinfo->irq_base = platform_get_irq(pdev, 0);
898 if (sinfo->irq_base < 0) {
899 dev_err(dev, "unable to get irq\n");
900 ret = sinfo->irq_base;
901 goto stop_clk;
902 }
903
904 /* Initialize video memory */
905 map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
906 if (map) {
907 /* use a pre-allocated memory buffer */
908 info->fix.smem_start = map->start;
28f65c11 909 info->fix.smem_len = resource_size(map);
14340586
NF		 910 if (!request_mem_region(info->fix.smem_start,
911 info->fix.smem_len, pdev->name)) {
912 ret = -EBUSY;
913 goto stop_clk;
914 }
915
916 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
917 if (!info->screen_base)
918 goto release_intmem;
01d3a5e7
HS		 919
920 /*
921 * Don't clear the framebuffer -- someone may have set
922 * up a splash image.
923 */
14340586
NF		 924 } else {
925 /* alocate memory buffer */
926 ret = atmel_lcdfb_alloc_video_memory(sinfo);
927 if (ret < 0) {
928 dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
929 goto stop_clk;
930 }
931 }
932
933 /* LCDC registers */
934 info->fix.mmio_start = regs->start;
28f65c11 935 info->fix.mmio_len = resource_size(regs);
14340586
NF		 936
937 if (!request_mem_region(info->fix.mmio_start,
938 info->fix.mmio_len, pdev->name)) {
939 ret = -EBUSY;
940 goto free_fb;
941 }
942
943 sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
944 if (!sinfo->mmio) {
945 dev_err(dev, "cannot map LCDC registers\n");
946 goto release_mem;
947 }
948
a9a84c37
DB		 949 /* Initialize PWM for contrast or backlight ("off") */
950 init_contrast(sinfo);
951
14340586
NF		 952 /* interrupt */
953 ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
954 if (ret) {
955 dev_err(dev, "request_irq failed: %d\n", ret);
956 goto unmap_mmio;
957 }
958
d22579b8
NF		 959 /* Some operations on the LCDC might sleep and
960 * require a preemptible task context */
961 INIT_WORK(&sinfo->task, atmel_lcdfb_task);
962
14340586
NF		 963 ret = atmel_lcdfb_init_fbinfo(sinfo);
964 if (ret < 0) {
965 dev_err(dev, "init fbinfo failed: %d\n", ret);
966 goto unregister_irqs;
967 }
968
969 /*
970 * This makes sure that our colour bitfield
971 * descriptors are correctly initialised.
972 */
973 atmel_lcdfb_check_var(&info->var, info);
974
975 ret = fb_set_var(info, &info->var);
976 if (ret) {
977 dev_warn(dev, "unable to set display parameters\n");
978 goto free_cmap;
979 }
980
981 dev_set_drvdata(dev, info);
982
983 /*
984 * Tell the world that we're ready to go
985 */
986 ret = register_framebuffer(info);
987 if (ret < 0) {
988 dev_err(dev, "failed to register framebuffer device: %d\n", ret);
34a35bdd 989 goto reset_drvdata;
14340586
NF		 990 }
991
968910bd
NF		 992 /* add selected videomode to modelist */
993 fb_var_to_videomode(&fbmode, &info->var);
994 fb_add_videomode(&fbmode, &info->modelist);
995
14340586
NF		 996 /* Power up the LCDC screen */
997 if (sinfo->atmel_lcdfb_power_control)
998 sinfo->atmel_lcdfb_power_control(1);
999
93f6ced9 1000 dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n",
14340586
NF		 1001 info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
1002
1003 return 0;
1004
34a35bdd
SG		 1005reset_drvdata:
1006 dev_set_drvdata(dev, NULL);
14340586
NF		 1007free_cmap:
1008 fb_dealloc_cmap(&info->cmap);
1009unregister_irqs:
d22579b8 1010 cancel_work_sync(&sinfo->task);
14340586
NF		 1011 free_irq(sinfo->irq_base, info);
1012unmap_mmio:
a9a84c37 1013 exit_backlight(sinfo);
14340586
NF		 1014 iounmap(sinfo->mmio);
1015release_mem:
1016 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1017free_fb:
1018 if (map)
1019 iounmap(info->screen_base);
1020 else
1021 atmel_lcdfb_free_video_memory(sinfo);
1022
1023release_intmem:
1024 if (map)
1025 release_mem_region(info->fix.smem_start, info->fix.smem_len);
1026stop_clk:
1027 atmel_lcdfb_stop_clock(sinfo);
1028 clk_put(sinfo->lcdc_clk);
1029put_bus_clk:
1030 if (sinfo->bus_clk)
1031 clk_put(sinfo->bus_clk);
1032free_info:
1033 framebuffer_release(info);
1034out:
1035 dev_dbg(dev, "%s FAILED\n", __func__);
1036 return ret;
1037}
1038
1039static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
1040{
1041 struct device *dev = &pdev->dev;
1042 struct fb_info *info = dev_get_drvdata(dev);
34a35bdd 1043 struct atmel_lcdfb_info *sinfo;
14340586 1044
34a35bdd 1045 if (!info || !info->par)
14340586 1046 return 0;
34a35bdd 1047 sinfo = info->par;
14340586 1048
d22579b8 1049 cancel_work_sync(&sinfo->task);
a9a84c37 1050 exit_backlight(sinfo);
14340586
NF		 1051 if (sinfo->atmel_lcdfb_power_control)
1052 sinfo->atmel_lcdfb_power_control(0);
1053 unregister_framebuffer(info);
1054 atmel_lcdfb_stop_clock(sinfo);
1055 clk_put(sinfo->lcdc_clk);
1056 if (sinfo->bus_clk)
1057 clk_put(sinfo->bus_clk);
1058 fb_dealloc_cmap(&info->cmap);
1059 free_irq(sinfo->irq_base, info);
1060 iounmap(sinfo->mmio);
1061 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1062 if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
1063 iounmap(info->screen_base);
1064 release_mem_region(info->fix.smem_start, info->fix.smem_len);
1065 } else {
1066 atmel_lcdfb_free_video_memory(sinfo);
1067 }
1068
1069 dev_set_drvdata(dev, NULL);
1070 framebuffer_release(info);
1071
1072 return 0;
1073}
1074
cf19a37e
DB		 1075#ifdef CONFIG_PM
1076
1077static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
1078{
1079 struct fb_info *info = platform_get_drvdata(pdev);
1080 struct atmel_lcdfb_info *sinfo = info->par;
1081
3aa04f1b
HS		 1082 /*
1083 * We don't want to handle interrupts while the clock is
1084 * stopped. It may take forever.
1085 */
1086 lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
1087
cf19a37e
DB		 1088 sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
1089 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
1090 if (sinfo->atmel_lcdfb_power_control)
1091 sinfo->atmel_lcdfb_power_control(0);
3aa04f1b
HS		 1092
1093 atmel_lcdfb_stop(sinfo);
cf19a37e 1094 atmel_lcdfb_stop_clock(sinfo);
3aa04f1b 1095
cf19a37e
DB		 1096 return 0;
1097}
1098
1099static int atmel_lcdfb_resume(struct platform_device *pdev)
1100{
1101 struct fb_info *info = platform_get_drvdata(pdev);
1102 struct atmel_lcdfb_info *sinfo = info->par;
1103
1104 atmel_lcdfb_start_clock(sinfo);
3aa04f1b 1105 atmel_lcdfb_start(sinfo);
cf19a37e
DB		 1106 if (sinfo->atmel_lcdfb_power_control)
1107 sinfo->atmel_lcdfb_power_control(1);
1108 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
3aa04f1b
HS		 1109
1110 /* Enable FIFO & DMA errors */
1111 lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI
1112 | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
1113
cf19a37e
DB		 1114 return 0;
1115}
1116
1117#else
1118#define atmel_lcdfb_suspend NULL
1119#define atmel_lcdfb_resume NULL
1120#endif
1121
14340586
NF		 1122static struct platform_driver atmel_lcdfb_driver = {
1123 .remove = __exit_p(atmel_lcdfb_remove),
cf19a37e
DB		 1124 .suspend = atmel_lcdfb_suspend,
1125 .resume = atmel_lcdfb_resume,
a9a84c37 1126
14340586
NF		 1127 .driver = {
1128 .name = "atmel_lcdfb",
1129 .owner = THIS_MODULE,
1130 },
1131};
1132
1133static int __init atmel_lcdfb_init(void)
1134{
1135 return platform_driver_probe(&atmel_lcdfb_driver, atmel_lcdfb_probe);
1136}
1137
1138static void __exit atmel_lcdfb_exit(void)
1139{
1140 platform_driver_unregister(&atmel_lcdfb_driver);
1141}
1142
1143module_init(atmel_lcdfb_init);
1144module_exit(atmel_lcdfb_exit);
1145
1146MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver");
8f4c79ce 1147MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
14340586 1148MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)